Macros
#define	ADC_SEQ (ADC_O_SSMUX0)

#define	ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)

#define	ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)

#define	ADC_SSEMUX (ADC_O_SSEMUX0 - ADC_O_SSMUX0)

#define	ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)

#define	ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)

#define	ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)

#define	ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0)

#define	ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0)

#define	ADC_SSTSH (ADC_O_SSTSH0 - ADC_O_SSMUX0)

Functions
void	ADCIntRegister (uint32_t ui32Base, uint32_t ui32SequenceNum, void(*pfnHandler)(void))

void	ADCIntUnregister (uint32_t ui32Base, uint32_t ui32SequenceNum)

void	ADCIntDisable (uint32_t ui32Base, uint32_t ui32SequenceNum)

void	ADCIntEnable (uint32_t ui32Base, uint32_t ui32SequenceNum)

uint32_t	ADCIntStatus (uint32_t ui32Base, uint32_t ui32SequenceNum, bool bMasked)

void	ADCIntClear (uint32_t ui32Base, uint32_t ui32SequenceNum)

void	ADCSequenceEnable (uint32_t ui32Base, uint32_t ui32SequenceNum)

void	ADCSequenceDisable (uint32_t ui32Base, uint32_t ui32SequenceNum)

void	ADCSequenceConfigure (uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t ui32Trigger, uint32_t ui32Priority)

void	ADCSequenceStepConfigure (uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t ui32Step, uint32_t ui32Config)

int32_t	ADCSequenceOverflow (uint32_t ui32Base, uint32_t ui32SequenceNum)

void	ADCSequenceOverflowClear (uint32_t ui32Base, uint32_t ui32SequenceNum)

int32_t	ADCSequenceUnderflow (uint32_t ui32Base, uint32_t ui32SequenceNum)

void	ADCSequenceUnderflowClear (uint32_t ui32Base, uint32_t ui32SequenceNum)

int32_t	ADCSequenceDataGet (uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t *pui32Buffer)

void	ADCProcessorTrigger (uint32_t ui32Base, uint32_t ui32SequenceNum)

void	ADCSoftwareOversampleConfigure (uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t ui32Factor)

void	ADCSoftwareOversampleStepConfigure (uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t ui32Step, uint32_t ui32Config)

void	ADCSoftwareOversampleDataGet (uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t *pui32Buffer, uint32_t ui32Count)

void	ADCHardwareOversampleConfigure (uint32_t ui32Base, uint32_t ui32Factor)

void	ADCComparatorConfigure (uint32_t ui32Base, uint32_t ui32Comp, uint32_t ui32Config)

void	ADCComparatorRegionSet (uint32_t ui32Base, uint32_t ui32Comp, uint32_t ui32LowRef, uint32_t ui32HighRef)

void	ADCComparatorReset (uint32_t ui32Base, uint32_t ui32Comp, bool bTrigger, bool bInterrupt)

void	ADCComparatorIntDisable (uint32_t ui32Base, uint32_t ui32SequenceNum)

void	ADCComparatorIntEnable (uint32_t ui32Base, uint32_t ui32SequenceNum)

uint32_t	ADCComparatorIntStatus (uint32_t ui32Base)

void	ADCComparatorIntClear (uint32_t ui32Base, uint32_t ui32Status)

void	ADCIntDisableEx (uint32_t ui32Base, uint32_t ui32IntFlags)

void	ADCIntEnableEx (uint32_t ui32Base, uint32_t ui32IntFlags)

uint32_t	ADCIntStatusEx (uint32_t ui32Base, bool bMasked)

void	ADCIntClearEx (uint32_t ui32Base, uint32_t ui32IntFlags)

void	ADCReferenceSet (uint32_t ui32Base, uint32_t ui32Ref)

uint32_t	ADCReferenceGet (uint32_t ui32Base)

void	ADCPhaseDelaySet (uint32_t ui32Base, uint32_t ui32Phase)

uint32_t	ADCPhaseDelayGet (uint32_t ui32Base)

void	ADCSequenceDMAEnable (uint32_t ui32Base, uint32_t ui32SequenceNum)

void	ADCSequenceDMADisable (uint32_t ui32Base, uint32_t ui32SequenceNum)

bool	ADCBusy (uint32_t ui32Base)

void	ADCClockConfigSet (uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32ClockDiv)

uint32_t	ADCClockConfigGet (uint32_t ui32Base, uint32_t *pui32ClockDiv)

Detailed Description

Introduction

The analog to digital converter (ADC) API provides a set of functions for programming and operating the ADC. Functions are provided to configure the sample sequencers, read the captured data, register a sample sequence interrupt handler, and handle interrupt masking/clearing.

Depending on the features of the individual microcontroller, the ADC supports up to twenty-four input channels plus an internal temperature sensor. Four sampling sequencers, each with configurable trigger events, can be captured. The first sequencer captures up to eight samples, the second and third sequencers capture up to four samples, and the fourth sequencer captures a single sample. Each sample can be the same channel, different channels, or any combination in any order.

The sample sequencers have configurable priorities that determine the order in which they are captured when multiple triggers occur simultaneously. The highest priority sequencer that is currently triggered is sampled first. Care must be taken with triggers that occur frequently (such as the ``always'' trigger); if their priority is too high, it is possible to starve the lower priority sequencers.

Hardware oversampling of the ADC data is available for improved accuracy. An oversampling factor of 2x, 4x, 8x, 16x, 32x, or 64x is supported, but reduces the throughput of the ADC by a corresponding factor. Hardware oversampling is applied uniformly across all sample sequencers.

Software oversampling of the ADC data is also available (even when hardware oversampling is available). An oversampling factor of 2x, 4x, or 8x is supported, but reduces the depth of the sample sequencers by a corresponding amount. For example, the first sample sequencer captures eight samples; in 4x oversampling mode, it can only capture two samples because the first four samples are used for the first oversampled value and the second four samples are used for the second oversampled value. The amount of software oversampling is configured on a per sample sequencer basis.

A more sophisticated software oversampling can be used to eliminate the reduction of the sample sequencer depth. By increasing the ADC trigger rate by 4x (for example) and averaging four triggers worth of data, 4x oversampling is achieved without any loss of sample sequencer capability. In this case, an increase in the number of ADC triggers (and presumably ADC interrupts) is the consequence. Because this method requires adjustments outside of the ADC driver itself, it is not directly supported by the driver (though nothing in the driver prevents it). The software oversampling APIs should not be used in this case.

API Functions

The analog to digital converter API is broken into three groups of functions: those that deal with the sample sequencers, those that deal with the processor trigger, and those that deal with interrupt handling.

The sample sequencers are configured with ADCSequenceConfigure() and ADCSequenceStepConfigure(). They are enabled and disabled with ADCSequenceEnable() and ADCSequenceDisable(). The captured data is obtained with ADCSequenceDataGet(). Sample sequencer FIFO overflow and underflow is managed with ADCSequenceOverflow(), ADCSequenceOverflowClear(), ADCSequenceUnderflow(), and ADCSequenceUnderflowClear().

Hardware oversampling of the ADC is controlled with ADCHardwareOversampleConfigure(). Software oversampling of the ADC is controlled with ADCSoftwareOversampleConfigure(), ADCSoftwareOversampleStepConfigure(), and ADCSoftwareOversampleDataGet().

The processor trigger is generated with ADCProcessorTrigger().

The interrupt handler for the ADC sample sequencer interrupts are managed with ADCIntRegister() and ADCIntUnregister(). The sample sequencer interrupt sources are managed with ADCIntDisable(), ADCIntEnable(), ADCIntStatus(), and ADCIntClear().

Programming Example

The following example shows how to use the ADC API to initialize a sample sequencer for processor triggering, trigger the sample sequence, and then read back the data when it is ready.

uint32_t ui32Value;
//
// Enable the ADC0 module.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
//
// Wait for the ADC0 module to be ready.
//
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0))
{
}
//
// Enable the first sample sequencer to capture the value of channel 0 when
// the processor trigger occurs.
//
ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_PROCESSOR, 0);
ADCSequenceStepConfigure(ADC0_BASE, 0, 0,
                         ADC_CTL_IE | ADC_CTL_END | ADC_CTL_CH0);
ADCSequenceEnable(ADC0_BASE, 0);
//
// Trigger the sample sequence.
//
ADCProcessorTrigger(ADC0_BASE, 0);
//
// Wait until the sample sequence has completed.
//
while(!ADCIntStatus(ADC0_BASE, 0, false))
{
}
//
// Read the value from the ADC.
//
ADCSequenceDataGet(ADC0_BASE, 0, &ui32Value);

Macro Definition Documentation

§ ADC_SEQ

#define ADC_SEQ (ADC_O_SSMUX0)

Referenced by ADCSequenceDataGet(), and ADCSequenceStepConfigure().

§ ADC_SEQ_STEP

#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)

Referenced by ADCSequenceDataGet(), and ADCSequenceStepConfigure().

§ ADC_SSMUX

#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)

Referenced by ADCSequenceStepConfigure().

§ ADC_SSEMUX

#define ADC_SSEMUX (ADC_O_SSEMUX0 - ADC_O_SSMUX0)

Referenced by ADCSequenceStepConfigure().

§ ADC_SSCTL

#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)

Referenced by ADCSequenceStepConfigure().

§ ADC_SSFIFO

#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)

Referenced by ADCSequenceDataGet().

§ ADC_SSFSTAT

#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)

Referenced by ADCSequenceDataGet().

§ ADC_SSOP

#define ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0)

Referenced by ADCSequenceStepConfigure().

§ ADC_SSDC

#define ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0)

Referenced by ADCSequenceStepConfigure().

§ ADC_SSTSH

#define ADC_SSTSH (ADC_O_SSTSH0 - ADC_O_SSMUX0)

Referenced by ADCSequenceStepConfigure().

Function Documentation

§ ADCIntRegister()

void ADCIntRegister	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum,
		void(*)(void)	pfnHandler
	)

Registers an interrupt handler for an ADC interrupt.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.
pfnHandler	is a pointer to the function to be called when the ADC sample sequence interrupt occurs.

This function sets the handler to be called when a sample sequence interrupt occurs. This function enables the global interrupt in the interrupt controller; the sequence interrupt must be enabled with ADCIntEnable(). It is the interrupt handler's responsibility to clear the interrupt source via ADCIntClear().

See also: IntRegister() for important information about registering interrupt handlers.

Returns: None.

References ASSERT.

§ ADCIntUnregister()

void ADCIntUnregister	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Unregisters the interrupt handler for an ADC interrupt.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

This function unregisters the interrupt handler. This function disables the global interrupt in the interrupt controller; the sequence interrupt must be disabled via ADCIntDisable().

See also: IntRegister() for important information about registering interrupt handlers.

Returns: None.

References ASSERT.

§ ADCIntDisable()

void ADCIntDisable	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Disables a sample sequence interrupt.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

This function disables the requested sample sequence interrupt.

Returns: None.

References ADC_O_IM, ASSERT, and HWREG.

§ ADCIntEnable()

void ADCIntEnable	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Enables a sample sequence interrupt.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

This function enables the requested sample sequence interrupt. Any outstanding interrupts are cleared before enabling the sample sequence interrupt.

Returns: None.

References ADC_O_IM, ADC_O_ISC, ASSERT, and HWREG.

§ ADCIntStatus()

uint32_t ADCIntStatus	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum,
		bool	bMasked
	)

Gets the current interrupt status.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.
bMasked	is false if the raw interrupt status is required and true if the masked interrupt status is required.

This function returns the interrupt status for the specified sample sequence. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Returns: The current raw or masked interrupt status.

References ADC_O_ISC, ADC_O_RIS, ASSERT, and HWREG.

§ ADCIntClear()

void ADCIntClear	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Clears sample sequence interrupt source.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

The specified sample sequence interrupt is cleared, so that it no longer asserts. This function must be called in the interrupt handler to keep the interrupt from being triggered again immediately upon exit.

Note: Because there is a write buffer in the Cortex-M processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared. Failure to do so may result in the interrupt handler being immediately reentered (because the interrupt controller still sees the interrupt source asserted).

Returns: None.

References ADC_O_ISC, ASSERT, and HWREG.

§ ADCSequenceEnable()

void ADCSequenceEnable	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Enables a sample sequence.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

Allows the specified sample sequence to be captured when its trigger is detected. A sample sequence must be configured before it is enabled.

Returns: None.

References ADC_O_ACTSS, ASSERT, and HWREG.

§ ADCSequenceDisable()

void ADCSequenceDisable	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Disables a sample sequence.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

Prevents the specified sample sequence from being captured when its trigger is detected. A sample sequence must be disabled before it is configured.

Returns: None.

References ADC_O_ACTSS, ASSERT, and HWREG.

§ ADCSequenceConfigure()

void ADCSequenceConfigure	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum,
		uint32_t	ui32Trigger,
		uint32_t	ui32Priority
	)

Configures the trigger source and priority of a sample sequence.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.
ui32Trigger	is the trigger source that initiates the sample sequence; must be one of the ADC_TRIGGER_* values.
ui32Priority	is the relative priority of the sample sequence with respect to the other sample sequences.

This function configures the initiation criteria for a sample sequence. Valid sample sequencers range from zero to three; sequencer zero captures up to eight samples, sequencers one and two capture up to four samples, and sequencer three captures a single sample. The trigger condition and priority (with respect to other sample sequencer execution) are set.

The ui32Trigger parameter can take on the following values:

ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the ADCProcessorTrigger() function.
ADC_TRIGGER_COMP0 - A trigger generated by the first analog comparator; configured with ComparatorConfigure().
ADC_TRIGGER_COMP1 - A trigger generated by the second analog comparator; configured with ComparatorConfigure().
ADC_TRIGGER_COMP2 - A trigger generated by the third analog comparator; configured with ComparatorConfigure().
ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port B4 pin. Note that some microcontrollers can select from any GPIO using the GPIOADCTriggerEnable() function.
ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with TimerControlTrigger().
ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; configured with PWMGenIntTrigEnable().
ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; configured with PWMGenIntTrigEnable().
ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; configured with PWMGenIntTrigEnable().
ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator; configured with PWMGenIntTrigEnable().
ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the sample sequence to capture repeatedly (so long as there is not a higher priority source active).

The ui32Priority parameter is a value between 0 and 3, where 0 represents the highest priority and 3 the lowest. Note that when programming the priority among a set of sample sequences, each must have unique priority; it is up to the caller to guarantee the uniqueness of the priorities.

Returns: None.

References ADC_O_EMUX, ADC_O_SSPRI, ADC_TRIGGER_ALWAYS, ADC_TRIGGER_COMP0, ADC_TRIGGER_COMP1, ADC_TRIGGER_COMP2, ADC_TRIGGER_EXTERNAL, ADC_TRIGGER_PROCESSOR, ADC_TRIGGER_PWM0, ADC_TRIGGER_PWM1, ADC_TRIGGER_PWM2, ADC_TRIGGER_PWM3, ADC_TRIGGER_TIMER, ASSERT, and HWREG.

§ ADCSequenceStepConfigure()

void ADCSequenceStepConfigure	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum,
		uint32_t	ui32Step,
		uint32_t	ui32Config
	)

Configure a step of the sample sequencer.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.
ui32Step	is the step to be configured.
ui32Config	is the configuration of this step; must be a logical OR of ADC_CTL_TS, ADC_CTL_IE, ADC_CTL_END, ADC_CTL_D, one of the input channel selects (ADC_CTL_CH0 through ADC_CTL_CH23), and one of the digital comparator selects (ADC_CTL_CMP0 through ADC_CTL_CMP7).

This function configures the ADC for one step of a sample sequence. The ADC can be configured for single-ended or differential operation (the ADC_CTL_D bit selects differential operation when set), the channel to be sampled can be chosen (the ADC_CTL_CH0 through ADC_CTL_CH23 values), and the internal temperature sensor can be selected (the ADC_CTL_TS bit). Additionally, this step can be defined as the last in the sequence (the ADC_CTL_END bit) and it can be configured to cause an interrupt when the step is complete (the ADC_CTL_IE bit). If the digital comparators are present on the device, this step may also be configured to send the ADC sample to the selected comparator using ADC_CTL_CMP0 through ADC_CTL_CMP7. The configuration is used by the ADC at the appropriate time when the trigger for this sequence occurs.

Note: If the Digital Comparator is present and enabled using the ADC_CTL_CMP0 through ADC_CTL_CMP7 selects, the ADC sample is NOT written into the ADC sequence data FIFO.

The ui32Step parameter determines the order in which the samples are captured by the ADC when the trigger occurs. It can range from zero to seven for the first sample sequencer, from zero to three for the second and third sample sequencer, and can only be zero for the fourth sample sequencer.

Differential mode only works with adjacent channel pairs (for example, 0 and 1). The channel select must be the number of the channel pair to sample (for example, ADC_CTL_CH0 for 0 and 1, or ADC_CTL_CH1 for 2 and 3) or undefined results are returned by the ADC. Additionally, if differential mode is selected when the temperature sensor is being sampled, undefined results are returned by the ADC.

It is the responsibility of the caller to ensure that a valid configuration is specified; this function does not check the validity of the specified configuration.

Returns: None.

References ADC_SEQ, ADC_SEQ_STEP, ADC_SSCTL, ADC_SSDC, ADC_SSEMUX, ADC_SSMUX, ADC_SSOP, ADC_SSTSH, ASSERT, and HWREG.

§ ADCSequenceOverflow()

int32_t ADCSequenceOverflow	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Determines if a sample sequence overflow occurred.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

This function determines if a sample sequence overflow has occurred. Overflow happens if the captured samples are not read from the FIFO before the next trigger occurs.

Returns: Returns zero if there was not an overflow, and non-zero if there was.

References ADC_O_OSTAT, ASSERT, and HWREG.

§ ADCSequenceOverflowClear()

void ADCSequenceOverflowClear	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Clears the overflow condition on a sample sequence.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

This function clears an overflow condition on one of the sample sequences. The overflow condition must be cleared in order to detect a subsequent overflow condition (it otherwise causes no harm).

Returns: None.

References ADC_O_OSTAT, ASSERT, and HWREG.

§ ADCSequenceUnderflow()

int32_t ADCSequenceUnderflow	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Determines if a sample sequence underflow occurred.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

This function determines if a sample sequence underflow has occurred. Underflow happens if too many samples are read from the FIFO.

Returns: Returns zero if there was not an underflow, and non-zero if there was.

References ADC_O_USTAT, ASSERT, and HWREG.

§ ADCSequenceUnderflowClear()

void ADCSequenceUnderflowClear	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Clears the underflow condition on a sample sequence.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

This function clears an underflow condition on one of the sample sequencers. The underflow condition must be cleared in order to detect a subsequent underflow condition (it otherwise causes no harm).

Returns: None.

References ADC_O_USTAT, ASSERT, and HWREG.

§ ADCSequenceDataGet()

int32_t ADCSequenceDataGet	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum,
		uint32_t *	pui32Buffer
	)

Gets the captured data for a sample sequence.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.
pui32Buffer	is the address where the data is stored.

This function copies data from the specified sample sequencer output FIFO to a memory resident buffer. The number of samples available in the hardware FIFO are copied into the buffer, which is assumed to be large enough to hold that many samples. This function only returns the samples that are presently available, which may not be the entire sample sequence if it is in the process of being executed.

Returns: Returns the number of samples copied to the buffer.

References ADC_SEQ, ADC_SEQ_STEP, ADC_SSFIFO, ADC_SSFSTAT, ADC_SSFSTAT0_EMPTY, ASSERT, and HWREG.

§ ADCProcessorTrigger()

void ADCProcessorTrigger	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Causes a processor trigger for a sample sequence.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number, with ADC_TRIGGER_WAIT or ADC_TRIGGER_SIGNAL optionally ORed into it.

This function triggers a processor-initiated sample sequence if the sample sequence trigger is configured to ADC_TRIGGER_PROCESSOR. If ADC_TRIGGER_WAIT is ORed into the sequence number, the processor-initiated trigger is delayed until a later processor-initiated trigger to a different ADC module that specifies ADC_TRIGGER_SIGNAL, allowing multiple ADCs to start from a processor-initiated trigger in a synchronous manner.

Returns: None.

References ADC_O_PSSI, ASSERT, and HWREG.

§ ADCSoftwareOversampleConfigure()

void ADCSoftwareOversampleConfigure	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum,
		uint32_t	ui32Factor
	)

Configures the software oversampling factor of the ADC.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.
ui32Factor	is the number of samples to be averaged.

This function configures the software oversampling for the ADC, which can be used to provide better resolution on the sampled data. Oversampling is accomplished by averaging multiple samples from the same analog input. Three different oversampling rates are supported; 2x, 4x, and 8x.

Oversampling is only supported on the sample sequencers that are more than one sample in depth (that is, the fourth sample sequencer is not supported). Oversampling by 2x (for example) divides the depth of the sample sequencer by two; so 2x oversampling on the first sample sequencer can only provide four samples per trigger. This also means that 8x oversampling is only available on the first sample sequencer.

Returns: None.

References ASSERT.

§ ADCSoftwareOversampleStepConfigure()

void ADCSoftwareOversampleStepConfigure	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum,
		uint32_t	ui32Step,
		uint32_t	ui32Config
	)

Configures a step of the software oversampled sequencer.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.
ui32Step	is the step to be configured.
ui32Config	is the configuration of this step.

This function configures a step of the sample sequencer when using the software oversampling feature. The number of steps available depends on the oversampling factor set by ADCSoftwareOversampleConfigure(). The value of ui32Config is the same as defined for ADCSequenceStepConfigure().

Returns: None.

References ASSERT.

§ ADCSoftwareOversampleDataGet()

void ADCSoftwareOversampleDataGet	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum,
		uint32_t *	pui32Buffer,
		uint32_t	ui32Count
	)

Gets the captured data for a sample sequence using software oversampling.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.
pui32Buffer	is the address where the data is stored.
ui32Count	is the number of samples to be read.

This function copies data from the specified sample sequence output FIFO to a memory resident buffer with software oversampling applied. The requested number of samples are copied into the data buffer; if there are not enough samples in the hardware FIFO to satisfy this many oversampled data items, then incorrect results are returned. It is the caller's responsibility to read only the samples that are available and wait until enough data is available, for example as a result of receiving an interrupt.

Returns: None.

References ASSERT.

§ ADCHardwareOversampleConfigure()

void ADCHardwareOversampleConfigure	(	uint32_t	ui32Base,
		uint32_t	ui32Factor
	)

Configures the hardware oversampling factor of the ADC.

Parameters

ui32Base	is the base address of the ADC module.
ui32Factor	is the number of samples to be averaged.

This function configures the hardware oversampling for the ADC, which can be used to provide better resolution on the sampled data. Oversampling is accomplished by averaging multiple samples from the same analog input. Six different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. Specifying an oversampling factor of zero disables hardware oversampling.

Hardware oversampling applies uniformly to all sample sequencers. It does not reduce the depth of the sample sequencers like the software oversampling APIs; each sample written into the sample sequencer FIFO is a fully oversampled analog input reading.

Enabling hardware averaging increases the precision of the ADC at the cost of throughput. For example, enabling 4x oversampling reduces the throughput of a 250 k samples/second ADC to 62.5 k samples/second.

Returns: None.

References ADC_O_SAC, ASSERT, and HWREG.

§ ADCComparatorConfigure()

void ADCComparatorConfigure	(	uint32_t	ui32Base,
		uint32_t	ui32Comp,
		uint32_t	ui32Config
	)

Configures an ADC digital comparator.

Parameters

ui32Base	is the base address of the ADC module.
ui32Comp	is the index of the comparator to configure.
ui32Config	is the configuration of the comparator.

This function configures a comparator. The ui32Config parameter is the result of a logical OR operation between the ADC_COMP_TRIG_xxx, and ADC_COMP_INT_xxx values.

The ADC_COMP_TRIG_xxx term can take on the following values:

ADC_COMP_TRIG_NONE to never trigger PWM fault condition.
ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when ADC output is in the low-band.
ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC output transitions into the low-band.
ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when ADC output is in the low-band only if ADC output has been in the high-band since the last trigger output.
ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC output transitions into low-band only if ADC output has been in the high-band since the last trigger output.
ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when ADC output is in the mid-band.
ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC output transitions into the mid-band.
ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when ADC output is in the high-band.
ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC output transitions into the high-band.
ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when ADC output is in the high-band only if ADC output has been in the low-band since the last trigger output.
ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC output transitions into high-band only if ADC output has been in the low-band since the last trigger output.

The ADC_COMP_INT_xxx term can take on the following values:

ADC_COMP_INT_NONE to never generate ADC interrupt.
ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC output is in the low-band.
ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output transitions into the low-band.
ADC_COMP_INT_LOW_HALWAYS to always generate ADC interrupt when ADC output is in the low-band only if ADC output has been in the high-band since the last trigger output.
ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output transitions into low-band only if ADC output has been in the high-band since the last trigger output.
ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC output is in the mid-band.
ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output transitions into the mid-band.
ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC output is in the high-band.
ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output transitions into the high-band.
ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC output is in the high-band only if ADC output has been in the low-band since the last trigger output.
ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output transitions into high-band only if ADC output has been in the low-band since the last trigger output.

Returns: None.

References ADC_O_DCCTL0, ASSERT, and HWREG.

§ ADCComparatorRegionSet()

void ADCComparatorRegionSet	(	uint32_t	ui32Base,
		uint32_t	ui32Comp,
		uint32_t	ui32LowRef,
		uint32_t	ui32HighRef
	)

Defines the ADC digital comparator regions.

Parameters

ui32Base	is the base address of the ADC module.
ui32Comp	is the index of the comparator to configure.
ui32LowRef	is the reference point for the low/mid band threshold.
ui32HighRef	is the reference point for the mid/high band threshold.

The ADC digital comparator operation is based on three ADC value regions:

low-band is defined as any ADC value less than or equal to the ui32LowRef value.
mid-band is defined as any ADC value greater than the ui32LowRef value but less than or equal to the ui32HighRef value.
high-band is defined as any ADC value greater than the ui32HighRef value.

Returns: None.

References ADC_O_DCCMP0, ASSERT, and HWREG.

§ ADCComparatorReset()

void ADCComparatorReset	(	uint32_t	ui32Base,
		uint32_t	ui32Comp,
		bool	bTrigger,
		bool	bInterrupt
	)

Resets the current ADC digital comparator conditions.

Parameters

ui32Base	is the base address of the ADC module.
ui32Comp	is the index of the comparator.
bTrigger	is the flag to indicate reset of Trigger conditions.
bInterrupt	is the flag to indicate reset of Interrupt conditions.

Because the digital comparator uses current and previous ADC values, this function allows the comparator to be reset to its initial value to prevent stale data from being used when a sequence is enabled.

Returns: None.

References ADC_O_DCRIC, ASSERT, and HWREG.

§ ADCComparatorIntDisable()

void ADCComparatorIntDisable	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Disables a sample sequence comparator interrupt.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

This function disables the requested sample sequence comparator interrupt.

Returns: None.

References ADC_O_IM, ASSERT, and HWREG.

§ ADCComparatorIntEnable()

void ADCComparatorIntEnable	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Enables a sample sequence comparator interrupt.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

This function enables the requested sample sequence comparator interrupt.

Returns: None.

References ADC_O_IM, ASSERT, and HWREG.

§ ADCComparatorIntStatus()

uint32_t ADCComparatorIntStatus ( uint32_t ui32Base )

Gets the current comparator interrupt status.

Parameters

ui32Base is the base address of the ADC module.

This function returns the digital comparator interrupt status bits. This status is sequence agnostic.

Returns: The current comparator interrupt status.

References ADC_O_DCISC, ASSERT, and HWREG.

§ ADCComparatorIntClear()

void ADCComparatorIntClear	(	uint32_t	ui32Base,
		uint32_t	ui32Status
	)

Clears sample sequence comparator interrupt source.

Parameters

ui32Base	is the base address of the ADC module.
ui32Status	is the bit-mapped interrupts status to clear.

The specified interrupt status is cleared.

Returns: None.

References ADC_O_DCISC, ASSERT, and HWREG.

§ ADCIntDisableEx()

void ADCIntDisableEx	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Disables ADC interrupt sources.

Parameters

ui32Base	is the base address of the ADC module.
ui32IntFlags	is the bit mask of the interrupt sources to disable.

This function disables the indicated ADC interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

The ui32IntFlags parameter is the logical OR of any of the following:

ADC_INT_SS0 - interrupt due to ADC sample sequence 0.
ADC_INT_SS1 - interrupt due to ADC sample sequence 1.
ADC_INT_SS2 - interrupt due to ADC sample sequence 2.
ADC_INT_SS3 - interrupt due to ADC sample sequence 3.
ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0.
ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1.
ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2.
ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3.
ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample sequence 0.
ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample sequence 1.
ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample sequence 2.
ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample sequence 3.

Returns: None.

References ADC_O_IM, ASSERT, and HWREG.

§ ADCIntEnableEx()

void ADCIntEnableEx	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Enables ADC interrupt sources.

Parameters

ui32Base	is the base address of the ADC module.
ui32IntFlags	is the bit mask of the interrupt sources to disable.

This function enables the indicated ADC interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

The ui32IntFlags parameter is the logical OR of any of the following:

ADC_INT_SS0 - interrupt due to ADC sample sequence 0.
ADC_INT_SS1 - interrupt due to ADC sample sequence 1.
ADC_INT_SS2 - interrupt due to ADC sample sequence 2.
ADC_INT_SS3 - interrupt due to ADC sample sequence 3.
ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0.
ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1.
ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2.
ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3.
ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample sequence 0.
ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample sequence 1.
ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample sequence 2.
ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample sequence 3.

Returns: None.

References ADC_O_IM, ASSERT, and HWREG.

§ ADCIntStatusEx()

uint32_t ADCIntStatusEx	(	uint32_t	ui32Base,
		bool	bMasked
	)

Gets interrupt status for the specified ADC module.

Parameters

ui32Base	is the base address of the ADC module.
bMasked	specifies whether masked or raw interrupt status is returned.

If bMasked is set as true, then the masked interrupt status is returned; otherwise, the raw interrupt status is returned.

Returns: Returns the current interrupt status for the specified ADC module. The value returned is the logical OR of the ADC_INT_* values that are currently active.

References ADC_INT_DCON_SS0, ADC_INT_DCON_SS1, ADC_INT_DCON_SS2, ADC_INT_DCON_SS3, ADC_O_ISC, ADC_O_RIS, ADC_RIS_INRDC, ASSERT, and HWREG.

§ ADCIntClearEx()

void ADCIntClearEx	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Clears the specified ADC interrupt sources.

Parameters

ui32Base	is the base address of the ADC port.
ui32IntFlags	is the bit mask of the interrupt sources to disable.

Clears the interrupt for the specified interrupt source(s).

The ui32IntFlags parameter is the logical OR of the ADC_INT_* values. See the ADCIntEnableEx() function for the list of possible ADC_INT* values.

Note: Because there is a write buffer in the Cortex-M processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared. Failure to do so may result in the interrupt handler being immediately reentered (because the interrupt controller still sees the interrupt source asserted).

Returns: None.

References ADC_O_ISC, and HWREG.

§ ADCReferenceSet()

void ADCReferenceSet	(	uint32_t	ui32Base,
		uint32_t	ui32Ref
	)

Selects the ADC reference.

Parameters

ui32Base	is the base address of the ADC module.
ui32Ref	is the reference to use.

The ADC reference is set as specified by ui32Ref. It must be one of ADC_REF_INT, or ADC_REF_EXT_3V for internal or external reference If ADC_REF_INT is chosen, then an internal 3V reference is used and no external reference is needed. If ADC_REF_EXT_3V is chosen, then a 3V reference must be supplied to the AVREF pin.

Returns: None.

References ADC_CTL_VREF_M, ADC_O_CTL, ADC_REF_EXT_3V, ADC_REF_INT, ASSERT, and HWREG.

§ ADCReferenceGet()

uint32_t ADCReferenceGet ( uint32_t ui32Base )

Returns the current setting of the ADC reference.

Parameters

ui32Base is the base address of the ADC module.

Returns the value of the ADC reference setting. The returned value is one of ADC_REF_INT, or ADC_REF_EXT_3V.

Returns: The current setting of the ADC reference.

References ADC_CTL_VREF_M, ADC_O_CTL, ASSERT, and HWREG.

§ ADCPhaseDelaySet()

void ADCPhaseDelaySet	(	uint32_t	ui32Base,
		uint32_t	ui32Phase
	)

Sets the phase delay between a trigger and the start of a sequence.

Parameters

ui32Base	is the base address of the ADC module.
ui32Phase	is the phase delay, specified as one of ADC_PHASE_0, ADC_PHASE_22_5, ADC_PHASE_45, ADC_PHASE_67_5, ADC_PHASE_90, ADC_PHASE_112_5, ADC_PHASE_135, ADC_PHASE_157_5, ADC_PHASE_180, ADC_PHASE_202_5, ADC_PHASE_225, ADC_PHASE_247_5, ADC_PHASE_270, ADC_PHASE_292_5, ADC_PHASE_315, or ADC_PHASE_337_5.

This function sets the phase delay between the detection of an ADC trigger event and the start of the sample sequence. By selecting a different phase delay for a pair of ADC modules (such as ADC_PHASE_0 and ADC_PHASE_180) and having each ADC module sample the same analog input, it is possible to increase the sampling rate of the analog input (with samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1, N+3, N+5, and so on, coming from the second ADC). The ADC module has a single phase delay that is applied to all sample sequences within that module.

Returns: None.

References ADC_O_SPC, ADC_PHASE_0, ADC_PHASE_112_5, ADC_PHASE_135, ADC_PHASE_157_5, ADC_PHASE_180, ADC_PHASE_202_5, ADC_PHASE_225, ADC_PHASE_22_5, ADC_PHASE_247_5, ADC_PHASE_270, ADC_PHASE_292_5, ADC_PHASE_315, ADC_PHASE_337_5, ADC_PHASE_45, ADC_PHASE_67_5, ADC_PHASE_90, ASSERT, and HWREG.

§ ADCPhaseDelayGet()

uint32_t ADCPhaseDelayGet ( uint32_t ui32Base )

Gets the phase delay between a trigger and the start of a sequence.

Parameters

ui32Base is the base address of the ADC module.

This function gets the current phase delay between the detection of an ADC trigger event and the start of the sample sequence.

Returns: Returns the phase delay, specified as one of ADC_PHASE_0, ADC_PHASE_22_5, ADC_PHASE_45, ADC_PHASE_67_5, ADC_PHASE_90, ADC_PHASE_112_5, ADC_PHASE_135, ADC_PHASE_157_5, ADC_PHASE_180, ADC_PHASE_202_5, ADC_PHASE_225, ADC_PHASE_247_5, ADC_PHASE_270, ADC_PHASE_292_5, ADC_PHASE_315, or ADC_PHASE_337_5.

References ADC_O_SPC, ASSERT, and HWREG.

§ ADCSequenceDMAEnable()

void ADCSequenceDMAEnable	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Enables DMA for sample sequencers.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

Allows DMA requests to be generated based on the FIFO level of the sample sequencer.

Returns: None.

References ADC_O_ACTSS, ASSERT, and HWREG.

§ ADCSequenceDMADisable()

void ADCSequenceDMADisable	(	uint32_t	ui32Base,
		uint32_t	ui32SequenceNum
	)

Disables DMA for sample sequencers.

Parameters

ui32Base	is the base address of the ADC module.
ui32SequenceNum	is the sample sequence number.

Prevents the specified sample sequencer from generating DMA requests.

Returns: None.

References ADC_O_ACTSS, ASSERT, and HWREG.

§ ADCBusy()

bool ADCBusy ( uint32_t ui32Base )

Determines whether the ADC is busy or not.

Parameters

ui32Base is the base address of the ADC.

This function allows the caller to determine whether or not the ADC is currently sampling . If false is returned, then the ADC is not sampling data.

Use this function to detect that the ADC is finished sampling data before putting the device into deep sleep. Before using this function, it is highly recommended that the event trigger is changed to ADC_TRIGGER_NEVER on all enabled sequencers to prevent the ADC from starting after checking the busy status.

Returns: Returns true if the ADC is sampling or false if all samples are complete.

References ADC_ACTSS_BUSY, ADC_O_ACTSS, ASSERT, and HWREG.

§ ADCClockConfigSet()

void ADCClockConfigSet	(	uint32_t	ui32Base,
		uint32_t	ui32Config,
		uint32_t	ui32ClockDiv
	)

Sets the clock configuration for the ADC.

Parameters

ui32Base	is the base address of the ADC to configure, which must always be ADC0_BASE.
ui32Config	is a combination of the ADC_CLOCK_SRC_ and ADC_CLOCK_RATE_* values used to configure the ADC clock input.
ui32ClockDiv	is the input clock divider for the clock selected by the ADC_CLOCK_SRC value.

This function is used to configure the input clock to the ADC modules. The clock configuration is shared across ADC units so ui32Base must always be ADC0_BASE. The ui32Config value is logical OR of one of the ADC_CLOCK_RATE_ and one of the ADC_CLOCK_SRC_ values defined below. The ADC_CLOCK_SRC_* values determine the input clock for the ADC. Regardless of the source, the final frequency after dividing must be between 16 and 32 MHz.

ADC_CLOCK_SRC_PLL - The main PLL output.
ADC_CLOCK_SRC_ALTCLK - The output of the ALTCLK in the system control module.
ADC_CLOCK_SRC_MOSC - The external MOSC.

ADC_CLOCK_RATE values control how often samples are provided back to the application. The values are the following:

ADC_CLOCK_RATE_FULL - All samples.
ADC_CLOCK_RATE_HALF - Every other sample.
ADC_CLOCK_RATE_QUARTER - Every fourth sample.
ADC_CLOCK_RATE_EIGHTH - Every either sample.

The ui32ClockDiv parameter allows for dividing a higher frequency down into the valid range for the ADCs. This parameter is typically only used ADC_CLOCK_SRC_PLL option because it is the only clock value that can be with the in the correct range to use the divider. The actual value ranges from 1 to 64.

Example: ADC Clock Configurations

//!
//! //
//! // Configure the ADC to use ALTCLK and sample at half the rate.
//! //
//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_ALTCLK | ADC_CLOCK_RATE_HALF, 1);
//!
//! ...
//!
//! //
//! // Configure the ADC to use PLL at 480 MHz divided by 24 to get an ADC
//! // clock of 20 MHz.
//! //
//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 24);
//!

\return None.

References ADC_CC_CLKDIV_M, ADC_CC_CLKDIV_S, ADC_CC_CS_M, ADC_CLOCK_RATE_FULL, ADC_O_CC, ADC_O_PC, ADC_PC_SR_M, ASSERT, and HWREG.

§ ADCClockConfigGet()

uint32_t ADCClockConfigGet	(	uint32_t	ui32Base,
		uint32_t *	pui32ClockDiv
	)

Returns the clock configuration for the ADC.

Parameters

ui32Base	is the base address of the ADC to configure, which must always be ADC0_BASE.
pui32ClockDiv	is a pointer to the input clock divider for the clock selected by the ADC_CLOCK_SRC in use by the ADCs.

This function returns the ADC clock configuration and the clock divider for the ADCs.

Example: Read the current ADC clock configuration.

//! uint32_t ui32Config, ui32ClockDiv;
//!
//! //
//! // Read the current ADC clock configuration.
//! //
//! ui32Config = ADCClockConfigGet(ADC0_BASE, &ui32ClockDiv);
//!

\return The current clock configuration of the ADC defined as a combination
of one of \b ADC_CLOCK_SRC_PLL,
\b ADC_CLOCK_SRC_MOSC, or \b ADC_CLOCK_SRC_ALTCLK logical ORed with one of
\b ADC_CLOCK_RATE_FULL, \b ADC_CLOCK_RATE_HALF, \b ADC_CLOCK_RATE_QUARTER,
or \b ADC_CLOCK_RATE_EIGHTH.  See ADCClockConfigSet() for more information
on these values.

References ADC_CC_CLKDIV_M, ADC_CC_CLKDIV_S, ADC_O_CC, ADC_O_PC, ADC_PC_SR_M, ASSERT, and HWREG.

Macros

Functions

Detailed Description

Introduction

API Functions

Programming Example

Macro Definition Documentation

§ ADC_SEQ

§ ADC_SEQ_STEP

§ ADC_SSMUX

§ ADC_SSEMUX

§ ADC_SSCTL

§ ADC_SSFIFO

§ ADC_SSFSTAT

§ ADC_SSOP

§ ADC_SSDC

§ ADC_SSTSH

Function Documentation

§ ADCIntRegister()

§ ADCIntUnregister()

§ ADCIntDisable()

§ ADCIntEnable()

§ ADCIntStatus()

§ ADCIntClear()

§ ADCSequenceEnable()

§ ADCSequenceDisable()

§ ADCSequenceConfigure()

§ ADCSequenceStepConfigure()

§ ADCSequenceOverflow()

§ ADCSequenceOverflowClear()

§ ADCSequenceUnderflow()

§ ADCSequenceUnderflowClear()

§ ADCSequenceDataGet()

§ ADCProcessorTrigger()

§ ADCSoftwareOversampleConfigure()

§ ADCSoftwareOversampleStepConfigure()

§ ADCSoftwareOversampleDataGet()

§ ADCHardwareOversampleConfigure()

§ ADCComparatorConfigure()

§ ADCComparatorRegionSet()

§ ADCComparatorReset()

§ ADCComparatorIntDisable()

§ ADCComparatorIntEnable()

§ ADCComparatorIntStatus()

§ ADCComparatorIntClear()

§ ADCIntDisableEx()

§ ADCIntEnableEx()

§ ADCIntStatusEx()

§ ADCIntClearEx()

§ ADCReferenceSet()

§ ADCReferenceGet()

§ ADCPhaseDelaySet()

§ ADCPhaseDelayGet()

§ ADCSequenceDMAEnable()

§ ADCSequenceDMADisable()

§ ADCBusy()

§ ADCClockConfigSet()

§ ADCClockConfigGet()