Macros
#define	NUM_INTERRUPTS 155

Functions
bool	IntMasterDisable (void)

void	IntRegister (uint32_t ui32Interrupt, void(*pfnHandler)(void))

void	IntUnregister (uint32_t ui32Interrupt)

void	IntPriorityGroupingSet (uint32_t ui32Bits)

uint32_t	IntPriorityGroupingGet (void)

void	IntPrioritySet (uint32_t ui32Interrupt, uint8_t ui8Priority)

int32_t	IntPriorityGet (uint32_t ui32Interrupt)

void	IntEnable (uint32_t ui32Interrupt)

void	IntDisable (uint32_t ui32Interrupt)

uint32_t	IntIsEnabled (uint32_t ui32Interrupt)

void	IntPendSet (uint32_t ui32Interrupt)

void	IntPendClear (uint32_t ui32Interrupt)

void	IntPriorityMaskSet (uint32_t ui32PriorityMask)

uint32_t	IntPriorityMaskGet (void)

void	IntTrigger (uint32_t ui32Interrupt)

Detailed Description

Introduction

The interrupt controller API provides a set of functions for dealing with the Nested Vectored Interrupt Controller (NVIC). Functions are provided to enable and disable interrupts, register interrupt handlers, and set the priority of interrupts.

The NVIC provides global interrupt masking, prioritization, and handler dispatching. Devices within the MSP432E4 family support up to 154 interrupt sources and eight priority levels. Individual interrupt sources can be masked, and the processor interrupt can be globally masked as well (without affecting the individual source masks).

The NVIC is tightly coupled with the Cortex-M microprocessor. When the processor responds to an interrupt, the NVIC supplies the address of the function to handle the interrupt directly to the processor. This action eliminates the need for a global interrupt handler that queries the interrupt controller to determine the cause of the interrupt and branch to the appropriate handler, reducing interrupt response time.

The interrupt prioritization in the NVIC allows higher priority interrupts to be handled before lower priority interrupts, as well as allowing preemption of lower priority interrupt handlers by higher priority interrupts. Again, this helps reduce interrupt response time (for example, a 1 ms system control interrupt is not held off by the execution of a lower priority 1 second housekeeping interrupt handler).

Sub-prioritization is also possible; instead of having N bits of preemptable prioritization, the NVIC can be configured (via software) for N - M bits of preemptable prioritization and M bits of sub-priority. In this scheme, two interrupts with the same preemptable prioritization but different sub-priorities do not cause a preemption; tail chaining is used instead to process the two interrupts back-to-back.

If two interrupts with the same priority (and sub-priority if so configured) are asserted at the same time, the one with the lower interrupt number is processed first. The NVIC keeps track of the nesting of interrupt handlers, allowing the processor to return from interrupt context only once all nested and pending interrupts have been handled.

Interrupt handlers can be configured in one of two ways; statically at compile time or dynamically at run time. Static configuration of interrupt handlers is accomplished by editing the interrupt handler table in the application's startup code. When statically configured, the interrupts must be explicitly enabled in the NVIC via IntEnable() before the processor can respond to the interrupt (in addition to any interrupt enabling required within the peripheral itself). Statically configuring the interrupt table provides the fastest interrupt response time because the stacking operation (a write to SRAM) can be performed in parallel with the interrupt handler table fetch (a read from Flash), as well as the prefetch of the interrupt handler itself (assuming it is also in Flash).

Alternatively, interrupts can be configured at run-time using IntRegister() (or the analog in each individual driver). When using IntRegister(), the interrupt must also be enabled as before; when using the analogue in each individual driver, IntEnable() is called by the driver and does not need to be called by the application. Run-time configuration of interrupts adds a small latency to the interrupt response time because the stacking operation (a write to SRAM) and the interrupt handler table fetch (a read from SRAM) must be performed sequentially.

Run-time configuration of interrupt handlers requires that the interrupt handler table be placed on a 1-kB boundary in SRAM (typically this is at the beginning of SRAM). Failure to do so results in an incorrect vector address being fetched in response to an interrupt. The vector table is in a section called ``vtable'' and must be placed appropriately with a linker script.

API Functions

The primary function of the interrupt controller API is to manage the interrupt vector table used by the NVIC to dispatch interrupt requests. Registering an interrupt handler is a simple matter of inserting the handler address into the table. By default, the table is filled with pointers to an internal handler that loops forever; it is an error for an interrupt to occur when there is no interrupt handler registered to process it. Therefore, interrupt sources must not be enabled before a handler has been registered, and interrupt sources must be disabled before a handler is unregistered. Interrupt handlers are managed with IntRegister() and IntUnregister().

Each interrupt source can be individually enabled and disabled via IntEnable() and IntDisable(). The processor interrupt can be enabled and disabled via IntMasterEnable() and IntMasterDisable(); this does not affect the individual interrupt enable states. Masking of the processor interrupt can be used as a simple critical section (only an NMI can interrupt the processor while the processor interrupt is disabled), although masking the processor interrupt can have adverse effects on the interrupt response time.

The priority of each interrupt source can be set and examined via IntPrioritySet() and IntPriorityGet(). The priority assignments are defined by the hardware; the upper N bits of the 8-bit priority are examined to determine the priority of an interrupt (for the MSP432E4 family, N is 3). This protocol allows priorities to be defined without knowledge of the exact number of supported priorities; moving to a device with more or fewer priority bits is made easier as the interrupt source continues to have a similar level of priority. Smaller priority numbers correspond to higher interrupt priority, so 0 is the highest priority.

Interrupt Mapping

The TM4C123 and TM4C129 devices have different interrupt mapping for the same peripheral interrupts. This requires that the application have a way to control the mapping of interrupts so that the correct interrupt number is used. For example the same interrupt name INT_USB0 has interrupt number 60 on TM4C123 devices and 58 on TM4C129 devices. All of the interrupt number macros start with INT_* and there are two defines that an application uses to allow the correct interrupt number to be mapped to these INT_* macros. The first set of macros that are the TARGET_IS_TM4C* which are used to define the class of part in use by the application. The second option is to specify the exact part that the application is using by defining one of the PART_<partno> values. For example, for a board using a TM4C129XNCZAD device the application would define the PART_TM4C129XNCZAD and/or one of the TARGET_IS_TM4C129_* macros depending on the revision of the device that is in use by the application. This conditional mapping of the interrupts allows applications to use a common name for the interrupt numbers without having to look up the actual interrupt number.

Note: The TARGET_IS_TM4C* and PART_<partno> macros also control ROM and pin mapping functions as well. See the rom_direct and the GPIO Pin Configuration sections of this document for more details on how these defines are used by these modules.

The valid interrupt for the interrupt API functions are the following: INT_ADC0SS0, INT_ADC0SS1, INT_ADC0SS2, INT_ADC0SS3, INT_ADC1SS0, INT_ADC1SS1, INT_ADC1SS2, INT_ADC1SS3, INT_AES0, INT_CAN0, INT_CAN1, INT_CIR0, INT_COMP0, INT_COMP1, INT_COMP2, INT_DES0, INT_EMAC0, INT_EPI0, INT_FAN0, INT_FAN1, INT_FLASH, INT_GPIOA, INT_GPIOB, INT_GPIOC, INT_GPIOD, INT_GPIOE, INT_GPIOF, INT_GPIOG, INT_GPIOH, INT_GPIOJ, INT_GPIOK, INT_GPIOL, INT_GPIOM, INT_GPION, INT_GPIOP0, INT_GPIOP1, INT_GPIOP2, INT_GPIOP3, INT_GPIOP4, INT_GPIOP5, INT_GPIOP6, INT_GPIOP7, INT_GPIOQ0, INT_GPIOQ1, INT_GPIOQ2, INT_GPIOQ3, INT_GPIOQ4, INT_GPIOQ5, INT_GPIOQ6, INT_GPIOQ7, INT_GPIOR, INT_GPIOS, INT_GPIOT, INT_HIBERNATE, INT_I2C0, INT_I2C1, INT_I2C2, INT_I2C3, INT_I2C4, INT_I2C5, INT_I2C6, INT_I2C7, INT_I2C8, INT_I2C9, INT_KBSCAN0, INT_LCD0, INT_LED0, INT_LPC0, INT_ONEWIRE0, INT_PECI0, INT_PRB0, INT_PS20, INT_PWM0_0, INT_PWM0_1, INT_PWM0_2, INT_PWM0_3, INT_PWM0_FAULT, INT_PWM1_0, INT_PWM1_1, INT_PWM1_2, INT_PWM1_3, INT_PWM1_FAULT, INT_QEI0, INT_QEI1, INT_RTS0, INT_SHA0, INT_SSI0, INT_SSI1, INT_SSI2, INT_SSI3, INT_SYSCTL, INT_SYSEXC, INT_TAMPER0, INT_TIMER0A, INT_TIMER0B, INT_TIMER1A, INT_TIMER1B, INT_TIMER2A, INT_TIMER2B, INT_TIMER3A, INT_TIMER3B, INT_TIMER4A, INT_TIMER4B, INT_TIMER5A, INT_TIMER5B, INT_TIMER6A, INT_TIMER6B, INT_TIMER7A, INT_TIMER7B, INT_UART0, INT_UART1, INT_UART2, INT_UART3, INT_UART4, INT_UART5, INT_UART6, INT_UART7, INT_UDMA, INT_UDMAERR, INT_USB0, INT_WATCHDOG, INT_WTIMER0A, INT_WTIMER0B, INT_WTIMER1A, INT_WTIMER1B, INT_WTIMER2A, INT_WTIMER2B, INT_WTIMER3A, INT_WTIMER3B, INT_WTIMER4A, INT_WTIMER4B, INT_WTIMER5A, INT_WTIMER5B

Programming Example

The following example shows how to use the Interrupt Controller API to register an interrupt handler for UART 0 and enable the interrupt.

//
// The interrupt handler function.
//
extern void IntHandler(void);
//
// Register the interrupt handler function for UART 0.
//
IntRegister(INT_UART0, IntHandler);
//
// Enable the interrupt for UART 0.
//
IntEnable(INT_UART0);
//
// Enable UART 0.
//
IntMasterEnable();

Macro Definition Documentation

§ NUM_INTERRUPTS

#define NUM_INTERRUPTS 155

Referenced by IntDisable(), IntEnable(), IntIsEnabled(), IntPendClear(), IntPendSet(), IntPriorityGet(), IntPrioritySet(), IntRegister(), IntTrigger(), and IntUnregister().

Function Documentation

§ IntMasterDisable()

bool IntMasterDisable ( void )

Disables the processor interrupt.

This function prevents the processor from receiving interrupts. This function does not affect the set of interrupts enabled in the interrupt controller; it just gates the single interrupt from the controller to the processor.

Note: Previously, this function had no return value. As such, it was possible to include interrupt.h and call this function without having included types.h. Now that the return is a bool, a compiler error occurs in this case. The solution is to include types.h before including interrupt.h.

Example: Disable interrupts to the processor.

//! //
//! // Disable interrupts to the processor.
//! //
//! IntMasterDisable();
//!
//!

\return Returns \b true if interrupts were already disabled when the
function was called or \b false if they were initially enabled.

References CPUcpsid().

§ IntRegister()

void IntRegister	(	uint32_t	ui32Interrupt,
		void(*)(void)	pfnHandler
	)

Registers a function to be called when an interrupt occurs.

Parameters

ui32Interrupt	specifies the interrupt in question.
pfnHandler	is a pointer to the function to be called.

This function is used to specify the handler function to be called when the given interrupt is asserted to the processor. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. When the interrupt occurs, if it is enabled (via IntEnable()), the handler function is called in interrupt context. Because the handler function can preempt other code, care must be taken to protect memory or peripherals that are accessed by the handler and other non-handler code.

Note: The use of this function (directly or indirectly via a peripheral driver interrupt register function) moves the interrupt vector table from flash to SRAM. Therefore, care must be taken when linking the application to ensure that the SRAM vector table is located at the beginning of SRAM; otherwise the NVIC does not look in the correct portion of memory for the vector table (it requires the vector table be on a 1 kB memory alignment). Normally, the SRAM vector table is so placed via the use of linker scripts. See the discussion of compile-time versus run-time interrupt handler registration in the introduction to this chapter.

Example: Set the UART 0 interrupt handler.

//!
//! //
//! // UART 0 interrupt handler.
//! //
//! void
//! UART0Handler(void)
//! {
//!     //
//!     // Handle interrupt.
//!     //
//! }
//!
//! //
//! // Set the UART 0 interrupt handler.
//! //
//! IntRegister(INT_UART0, UART0Handler);
//!
//!

\return None.

References ASSERT, HWREG, NUM_INTERRUPTS, and NVIC_VTABLE.

Referenced by AESIntRegister(), ComparatorIntRegister(), DESIntRegister(), EMACIntRegister(), FlashIntRegister(), LCDIntRegister(), MPUIntRegister(), SHAMD5IntRegister(), SysCtlIntRegister(), SysTickIntRegister(), uDMAIntRegister(), and WatchdogIntRegister().

§ IntUnregister()

void IntUnregister ( uint32_t ui32Interrupt )

Unregisters the function to be called when an interrupt occurs.

Parameters

ui32Interrupt specifies the interrupt in question.

This function is used to indicate that no handler is called when the given interrupt is asserted to the processor. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. The interrupt source is automatically disabled (via IntDisable()) if necessary.

See also: IntRegister() for important information about registering interrupt handlers.

Example: Reset the UART 0 interrupt handler to the default handler.

//! //
//! // Reset the UART 0 interrupt handler to the default handler.
//! //
//! IntUnregister(INT_UART0);
//!
//!

\return None.

References ASSERT, and NUM_INTERRUPTS.

Referenced by AESIntUnregister(), ComparatorIntUnregister(), DESIntUnregister(), EMACIntUnregister(), FlashIntUnregister(), LCDIntUnregister(), MPUIntUnregister(), SHAMD5IntUnregister(), SysCtlIntUnregister(), SysTickIntUnregister(), uDMAIntUnregister(), and WatchdogIntUnregister().

§ IntPriorityGroupingSet()

void IntPriorityGroupingSet ( uint32_t ui32Bits )

Sets the priority grouping of the interrupt controller.

Parameters

ui32Bits specifies the number of bits of preemptable priority.

This function specifies the split between preemptable priority levels and sub-priority levels in the interrupt priority specification. Three bits are available for hardware interrupt prioritization and therefore priority grouping values of three through seven have the same effect.

Example: Set the priority grouping for the interrupt controller.

//! //
//! // Set the priority grouping for the interrupt controller to 2 bits.
//! //
//! IntPriorityGroupingSet(2);
//!
//!

\return None.

References ASSERT, HWREG, NUM_PRIORITY, NVIC_APINT, and NVIC_APINT_VECTKEY.

§ IntPriorityGroupingGet()

uint32_t IntPriorityGroupingGet ( void )

Gets the priority grouping of the interrupt controller.

This function returns the split between preemptable priority levels and sub-priority levels in the interrupt priority specification.

Example: Get the priority grouping for the interrupt controller.

//! //
//! // Get the priority grouping for the interrupt controller.
//! //
//! IntPriorityGroupingGet();
//!
//!

\return The number of bits of preemptable priority.

References HWREG, NUM_PRIORITY, NVIC_APINT, and NVIC_APINT_PRIGROUP_M.

§ IntPrioritySet()

void IntPrioritySet	(	uint32_t	ui32Interrupt,
		uint8_t	ui8Priority
	)

Sets the priority of an interrupt.

Parameters

ui32Interrupt	specifies the interrupt in question.
ui8Priority	specifies the priority of the interrupt.

This function is used to set the priority of an interrupt. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. The ui8Priority parameter specifies the interrupts hardware priority level of the interrupt in the interrupt controller. When multiple interrupts are asserted simultaneously, the ones with the highest priority are processed before the lower priority interrupts. Smaller numbers correspond to higher interrupt priorities; priority 0 is the highest interrupt priority.

Note: The hardware priority mechanism only looks at the upper 3 bits of the priority level, so any prioritization must be performed in those bits. The remaining bits can be used to sub-prioritize the interrupt sources, and may be used by the hardware priority mechanism. This arrangement allows priorities to migrate to different NVIC implementations without changing the gross prioritization of the interrupts.

Example: Set priorities for UART 0 and USB interrupts.

//! //
//! // Set the UART 0 interrupt priority to the lowest priority.
//! //
//! IntPrioritySet(INT_UART0, 0xE0);
//!
//! //
//! // Set the USB 0 interrupt priority to the highest priority.
//! //
//! IntPrioritySet(INT_USB0, 0);
//!
//!

\return None.

References ASSERT, HWREG, and NUM_INTERRUPTS.

§ IntPriorityGet()

int32_t IntPriorityGet ( uint32_t ui32Interrupt )

Gets the priority of an interrupt.

Parameters

ui32Interrupt specifies the interrupt in question.

This function gets the priority of an interrupt. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. See IntPrioritySet() for a full definition of the priority value.

Example: Get the current UART 0 interrupt priority.

//! //
//! // Get the current UART 0 interrupt priority.
//! //
//! IntPriorityGet(INT_UART0);
//!
//!

\return Returns the interrupt priority for the given interrupt.

References ASSERT, HWREG, and NUM_INTERRUPTS.

§ IntEnable()

void IntEnable ( uint32_t ui32Interrupt )

Enables an interrupt.

Parameters

ui32Interrupt specifies the interrupt to be enabled.

The specified interrupt is enabled in the interrupt controller. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. Other enables for the interrupt (such as at the peripheral level) are unaffected by this function.

Example: Enable the UART 0 interrupt.

//! //
//! // Enable the UART 0 interrupt in the interrupt controller.
//! //
//! IntEnable(INT_UART0);
//!
//!

\return None.

References ASSERT, FAULT_BUS, FAULT_MPU, FAULT_SYSTICK, FAULT_USAGE, HWREG, NUM_INTERRUPTS, NVIC_ST_CTRL, NVIC_ST_CTRL_INTEN, NVIC_SYS_HND_CTRL, NVIC_SYS_HND_CTRL_BUS, NVIC_SYS_HND_CTRL_MEM, and NVIC_SYS_HND_CTRL_USAGE.

Referenced by AESIntRegister(), ComparatorIntRegister(), DESIntRegister(), EMACIntRegister(), FlashIntRegister(), LCDIntRegister(), MPUIntRegister(), SHAMD5IntRegister(), SysCtlIntRegister(), uDMAIntRegister(), and WatchdogIntRegister().

§ IntDisable()

void IntDisable ( uint32_t ui32Interrupt )

Disables an interrupt.

Parameters

ui32Interrupt specifies the interrupt to be disabled.

The specified interrupt is disabled in the interrupt controller. The ui32Interrupt parameter must be one of the valid INT_* values listed in interrupt.h. Other enables for the interrupt (such as at the peripheral level) are unaffected by this function.

Example: Disable the UART 0 interrupt.

//! //
//! // Disable the UART 0 interrupt in the interrupt controller.
//! //
//! IntDisable(INT_UART0);
//!
//!

\return None.

References ASSERT, FAULT_BUS, FAULT_MPU, FAULT_SYSTICK, FAULT_USAGE, HWREG, NUM_INTERRUPTS, NVIC_ST_CTRL, NVIC_ST_CTRL_INTEN, NVIC_SYS_HND_CTRL, NVIC_SYS_HND_CTRL_BUS, NVIC_SYS_HND_CTRL_MEM, and NVIC_SYS_HND_CTRL_USAGE.

Referenced by AESIntUnregister(), ComparatorIntUnregister(), DESIntUnregister(), EMACIntUnregister(), FlashIntUnregister(), LCDIntUnregister(), MPUIntUnregister(), SHAMD5IntUnregister(), SysCtlIntUnregister(), uDMAIntUnregister(), and WatchdogIntUnregister().

§ IntIsEnabled()

uint32_t IntIsEnabled ( uint32_t ui32Interrupt )

Returns if a peripheral interrupt is enabled.

Parameters

ui32Interrupt specifies the interrupt to check.

This function checks if the specified interrupt is enabled in the interrupt controller. The ui32Interrupt parameter must be one of the valid INT_* values listed in interrupt.h.

Example: Disable the UART 0 interrupt if it is enabled.

//! //
//! // Disable the UART 0 interrupt if it is enabled.
//! //
//! if(IntIsEnabled(INT_UART0))
//! {
//!     IntDisable(INT_UART0);
//! }
//!

\return A non-zero value if the interrupt is enabled.

References ASSERT, FAULT_BUS, FAULT_MPU, FAULT_SYSTICK, FAULT_USAGE, HWREG, NUM_INTERRUPTS, NVIC_ST_CTRL, NVIC_ST_CTRL_INTEN, NVIC_SYS_HND_CTRL, NVIC_SYS_HND_CTRL_BUS, NVIC_SYS_HND_CTRL_MEM, and NVIC_SYS_HND_CTRL_USAGE.

§ IntPendSet()

void IntPendSet ( uint32_t ui32Interrupt )

Pends an interrupt.

Parameters

ui32Interrupt specifies the interrupt to be pended.

The specified interrupt is pended in the interrupt controller. The ui32Interrupt parameter must be one of the valid INT_* values listed in interrupt.h. Pending an interrupt causes the interrupt controller to execute the corresponding interrupt handler at the next available time, based on the current interrupt state priorities. For example, if called by a higher priority interrupt handler, the specified interrupt handler is not called until after the current interrupt handler has completed execution. The interrupt must have been enabled for it to be called.

Example: Pend a UART 0 interrupt.

//! //
//! // Pend a UART 0 interrupt.
//! //
//! IntPendSet(INT_UART0);
//!

\return None.

References ASSERT, FAULT_NMI, FAULT_PENDSV, FAULT_SYSTICK, HWREG, NUM_INTERRUPTS, NVIC_INT_CTRL, NVIC_INT_CTRL_NMI_SET, NVIC_INT_CTRL_PEND_SV, and NVIC_INT_CTRL_PENDSTSET.

§ IntPendClear()

void IntPendClear ( uint32_t ui32Interrupt )

Un-pends an interrupt.

Parameters

ui32Interrupt specifies the interrupt to be un-pended. The ui32Interrupt parameter must be one of the valid INT_* values listed in interrupt.h.

The specified interrupt is un-pended in the interrupt controller. This causes any previously generated interrupts that have not been handled yet (due to higher priority interrupts or the interrupt not having been enabled yet) to be discarded.

Example: Un-pend a UART 0 interrupt.

//! //
//! // Un-pend a UART 0 interrupt.
//! //
//! IntPendClear(INT_UART0);
//!

\return None.

References ASSERT, FAULT_PENDSV, FAULT_SYSTICK, HWREG, NUM_INTERRUPTS, NVIC_INT_CTRL, NVIC_INT_CTRL_PENDSTCLR, and NVIC_INT_CTRL_UNPEND_SV.

§ IntPriorityMaskSet()

void IntPriorityMaskSet ( uint32_t ui32PriorityMask )

Sets the priority masking level

Parameters

ui32PriorityMask is the priority level that is masked.

This function sets the interrupt priority masking level so that all interrupts at the specified or lesser priority level are masked. Masking interrupts can be used to globally disable a set of interrupts with priority below a predetermined threshold. A value of 0 disables priority masking.

Smaller numbers correspond to higher interrupt priorities. So for example a priority level mask of 4 allows interrupts of priority level 0-3, and interrupts with a numerical priority of 4 and greater are blocked.

Note: The hardware priority mechanism only looks at the upper 3 bits of the priority level, so any prioritization must be performed in those bits.

Example: Mask of interrupt priorities greater than or equal to 0x80.

//! //
//! // Mask of interrupt priorities greater than or equal to 0x80.
//! //
//! IntPriorityMaskSet(0x80);
//!

\return None.

References CPUbasepriSet().

§ IntPriorityMaskGet()

uint32_t IntPriorityMaskGet ( void )

Gets the priority masking level

This function gets the current setting of the interrupt priority masking level. The value returned is the priority level such that all interrupts of that and lesser priority are masked. A value of 0 means that priority masking is disabled.

Smaller numbers correspond to higher interrupt priorities. So for example a priority level mask of 4 allows interrupts of priority level 0-3, and interrupts with a numerical priority of 4 and greater are blocked.

The hardware priority mechanism only looks at the upper 3 bits of the priority level, so any prioritization must be performed in those bits.

Example: Get the current interrupt priority mask.

//! //
//! // Get the current interrupt priority mask.
//! //
//! IntPriorityMaskGet();
//!

\return Returns the value of the interrupt priority level mask.

References CPUbasepriGet().

§ IntTrigger()

void IntTrigger ( uint32_t ui32Interrupt )

Triggers an interrupt.

Parameters

ui32Interrupt specifies the interrupt to be triggered.

This function performs a software trigger of an interrupt. The ui32Interrupt parameter must be one of the valid INT_* values listed in interrupt.h. The interrupt controller behaves as if the corresponding interrupt line was asserted, and the interrupt is handled in the same manner (meaning that it must be enabled in order to be processed, and the processing is based on its priority with respect to other unhandled interrupts).

Returns: None.

References ASSERT, HWREG, NUM_INTERRUPTS, and NVIC_SW_TRIG.

Macros

Functions

Detailed Description

Introduction

API Functions

Interrupt Mapping

Programming Example

Macro Definition Documentation

§ NUM_INTERRUPTS

Function Documentation

§ IntMasterDisable()

§ IntRegister()

§ IntUnregister()

§ IntPriorityGroupingSet()

§ IntPriorityGroupingGet()

§ IntPrioritySet()

§ IntPriorityGet()

§ IntEnable()

§ IntDisable()

§ IntIsEnabled()

§ IntPendSet()

§ IntPendClear()

§ IntPriorityMaskSet()

§ IntPriorityMaskGet()

§ IntTrigger()