MSP432E4 DriverLib API Guide  1.11.00.03
Macros
hw_adc.h File Reference
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Macros

#define ADC_O_ACTSS   0x00000000
 
#define ADC_O_RIS   0x00000004
 
#define ADC_O_IM   0x00000008
 
#define ADC_O_ISC   0x0000000C
 
#define ADC_O_OSTAT   0x00000010
 
#define ADC_O_EMUX   0x00000014
 
#define ADC_O_USTAT   0x00000018
 
#define ADC_O_TSSEL   0x0000001C
 
#define ADC_O_SSPRI   0x00000020
 
#define ADC_O_SPC   0x00000024
 
#define ADC_O_PSSI   0x00000028
 
#define ADC_O_SAC   0x00000030
 
#define ADC_O_DCISC   0x00000034
 
#define ADC_O_CTL   0x00000038
 
#define ADC_O_SSMUX0   0x00000040
 
#define ADC_O_SSCTL0   0x00000044
 
#define ADC_O_SSFIFO0   0x00000048
 
#define ADC_O_SSFSTAT0   0x0000004C
 
#define ADC_O_SSOP0   0x00000050
 
#define ADC_O_SSDC0   0x00000054
 
#define ADC_O_SSEMUX0   0x00000058
 
#define ADC_O_SSTSH0   0x0000005C
 
#define ADC_O_SSMUX1   0x00000060
 
#define ADC_O_SSCTL1   0x00000064
 
#define ADC_O_SSFIFO1   0x00000068
 
#define ADC_O_SSFSTAT1   0x0000006C
 
#define ADC_O_SSOP1   0x00000070
 
#define ADC_O_SSDC1   0x00000074
 
#define ADC_O_SSEMUX1   0x00000078
 
#define ADC_O_SSTSH1   0x0000007C
 
#define ADC_O_SSMUX2   0x00000080
 
#define ADC_O_SSCTL2   0x00000084
 
#define ADC_O_SSFIFO2   0x00000088
 
#define ADC_O_SSFSTAT2   0x0000008C
 
#define ADC_O_SSOP2   0x00000090
 
#define ADC_O_SSDC2   0x00000094
 
#define ADC_O_SSEMUX2   0x00000098
 
#define ADC_O_SSTSH2   0x0000009C
 
#define ADC_O_SSMUX3   0x000000A0
 
#define ADC_O_SSCTL3   0x000000A4
 
#define ADC_O_SSFIFO3   0x000000A8
 
#define ADC_O_SSFSTAT3   0x000000AC
 
#define ADC_O_SSOP3   0x000000B0
 
#define ADC_O_SSDC3   0x000000B4
 
#define ADC_O_SSEMUX3   0x000000B8
 
#define ADC_O_SSTSH3   0x000000BC
 
#define ADC_O_DCRIC   0x00000D00
 
#define ADC_O_DCCTL0   0x00000E00
 
#define ADC_O_DCCTL1   0x00000E04
 
#define ADC_O_DCCTL2   0x00000E08
 
#define ADC_O_DCCTL3   0x00000E0C
 
#define ADC_O_DCCTL4   0x00000E10
 
#define ADC_O_DCCTL5   0x00000E14
 
#define ADC_O_DCCTL6   0x00000E18
 
#define ADC_O_DCCTL7   0x00000E1C
 
#define ADC_O_DCCMP0   0x00000E40
 
#define ADC_O_DCCMP1   0x00000E44
 
#define ADC_O_DCCMP2   0x00000E48
 
#define ADC_O_DCCMP3   0x00000E4C
 
#define ADC_O_DCCMP4   0x00000E50
 
#define ADC_O_DCCMP5   0x00000E54
 
#define ADC_O_DCCMP6   0x00000E58
 
#define ADC_O_DCCMP7   0x00000E5C
 
#define ADC_O_PP   0x00000FC0
 
#define ADC_O_PC   0x00000FC4
 
#define ADC_O_CC   0x00000FC8
 
#define ADC_ACTSS_BUSY   0x00010000
 
#define ADC_ACTSS_ADEN3   0x00000800
 
#define ADC_ACTSS_ADEN2   0x00000400
 
#define ADC_ACTSS_ADEN1   0x00000200
 
#define ADC_ACTSS_ADEN0   0x00000100
 
#define ADC_ACTSS_ASEN3   0x00000008
 
#define ADC_ACTSS_ASEN2   0x00000004
 
#define ADC_ACTSS_ASEN1   0x00000002
 
#define ADC_ACTSS_ASEN0   0x00000001
 
#define ADC_RIS_INRDC   0x00010000
 
#define ADC_RIS_DMAINR3   0x00000800
 
#define ADC_RIS_DMAINR2   0x00000400
 
#define ADC_RIS_DMAINR1   0x00000200
 
#define ADC_RIS_DMAINR0   0x00000100
 
#define ADC_RIS_INR3   0x00000008
 
#define ADC_RIS_INR2   0x00000004
 
#define ADC_RIS_INR1   0x00000002
 
#define ADC_RIS_INR0   0x00000001
 
#define ADC_IM_DCONSS3   0x00080000
 
#define ADC_IM_DCONSS2   0x00040000
 
#define ADC_IM_DCONSS1   0x00020000
 
#define ADC_IM_DCONSS0   0x00010000
 
#define ADC_IM_DMAMASK3   0x00000800
 
#define ADC_IM_DMAMASK2   0x00000400
 
#define ADC_IM_DMAMASK1   0x00000200
 
#define ADC_IM_DMAMASK0   0x00000100
 
#define ADC_IM_MASK3   0x00000008
 
#define ADC_IM_MASK2   0x00000004
 
#define ADC_IM_MASK1   0x00000002
 
#define ADC_IM_MASK0   0x00000001
 
#define ADC_ISC_DCINSS3   0x00080000
 
#define ADC_ISC_DCINSS2   0x00040000
 
#define ADC_ISC_DCINSS1   0x00020000
 
#define ADC_ISC_DCINSS0   0x00010000
 
#define ADC_ISC_DMAIN3   0x00000800
 
#define ADC_ISC_DMAIN2   0x00000400
 
#define ADC_ISC_DMAIN1   0x00000200
 
#define ADC_ISC_DMAIN0   0x00000100
 
#define ADC_ISC_IN3   0x00000008
 
#define ADC_ISC_IN2   0x00000004
 
#define ADC_ISC_IN1   0x00000002
 
#define ADC_ISC_IN0   0x00000001
 
#define ADC_OSTAT_OV3   0x00000008
 
#define ADC_OSTAT_OV2   0x00000004
 
#define ADC_OSTAT_OV1   0x00000002
 
#define ADC_OSTAT_OV0   0x00000001
 
#define ADC_EMUX_EM3_M   0x0000F000
 
#define ADC_EMUX_EM3_PROCESSOR   0x00000000
 
#define ADC_EMUX_EM3_COMP0   0x00001000
 
#define ADC_EMUX_EM3_COMP1   0x00002000
 
#define ADC_EMUX_EM3_COMP2   0x00003000
 
#define ADC_EMUX_EM3_EXTERNAL   0x00004000
 
#define ADC_EMUX_EM3_TIMER   0x00005000
 
#define ADC_EMUX_EM3_PWM0   0x00006000
 
#define ADC_EMUX_EM3_PWM1   0x00007000
 
#define ADC_EMUX_EM3_PWM2   0x00008000
 
#define ADC_EMUX_EM3_PWM3   0x00009000
 
#define ADC_EMUX_EM3_NEVER   0x0000E000
 
#define ADC_EMUX_EM3_ALWAYS   0x0000F000
 
#define ADC_EMUX_EM2_M   0x00000F00
 
#define ADC_EMUX_EM2_PROCESSOR   0x00000000
 
#define ADC_EMUX_EM2_COMP0   0x00000100
 
#define ADC_EMUX_EM2_COMP1   0x00000200
 
#define ADC_EMUX_EM2_COMP2   0x00000300
 
#define ADC_EMUX_EM2_EXTERNAL   0x00000400
 
#define ADC_EMUX_EM2_TIMER   0x00000500
 
#define ADC_EMUX_EM2_PWM0   0x00000600
 
#define ADC_EMUX_EM2_PWM1   0x00000700
 
#define ADC_EMUX_EM2_PWM2   0x00000800
 
#define ADC_EMUX_EM2_PWM3   0x00000900
 
#define ADC_EMUX_EM2_NEVER   0x00000E00
 
#define ADC_EMUX_EM2_ALWAYS   0x00000F00
 
#define ADC_EMUX_EM1_M   0x000000F0
 
#define ADC_EMUX_EM1_PROCESSOR   0x00000000
 
#define ADC_EMUX_EM1_COMP0   0x00000010
 
#define ADC_EMUX_EM1_COMP1   0x00000020
 
#define ADC_EMUX_EM1_COMP2   0x00000030
 
#define ADC_EMUX_EM1_EXTERNAL   0x00000040
 
#define ADC_EMUX_EM1_TIMER   0x00000050
 
#define ADC_EMUX_EM1_PWM0   0x00000060
 
#define ADC_EMUX_EM1_PWM1   0x00000070
 
#define ADC_EMUX_EM1_PWM2   0x00000080
 
#define ADC_EMUX_EM1_PWM3   0x00000090
 
#define ADC_EMUX_EM1_NEVER   0x000000E0
 
#define ADC_EMUX_EM1_ALWAYS   0x000000F0
 
#define ADC_EMUX_EM0_M   0x0000000F
 
#define ADC_EMUX_EM0_PROCESSOR   0x00000000
 
#define ADC_EMUX_EM0_COMP0   0x00000001
 
#define ADC_EMUX_EM0_COMP1   0x00000002
 
#define ADC_EMUX_EM0_COMP2   0x00000003
 
#define ADC_EMUX_EM0_EXTERNAL   0x00000004
 
#define ADC_EMUX_EM0_TIMER   0x00000005
 
#define ADC_EMUX_EM0_PWM0   0x00000006
 
#define ADC_EMUX_EM0_PWM1   0x00000007
 
#define ADC_EMUX_EM0_PWM2   0x00000008
 
#define ADC_EMUX_EM0_PWM3   0x00000009
 
#define ADC_EMUX_EM0_NEVER   0x0000000E
 
#define ADC_EMUX_EM0_ALWAYS   0x0000000F
 
#define ADC_USTAT_UV3   0x00000008
 
#define ADC_USTAT_UV2   0x00000004
 
#define ADC_USTAT_UV1   0x00000002
 
#define ADC_USTAT_UV0   0x00000001
 
#define ADC_TSSEL_PS3_M   0x30000000
 
#define ADC_TSSEL_PS3_0   0x00000000
 
#define ADC_TSSEL_PS2_M   0x00300000
 
#define ADC_TSSEL_PS2_0   0x00000000
 
#define ADC_TSSEL_PS1_M   0x00003000
 
#define ADC_TSSEL_PS1_0   0x00000000
 
#define ADC_TSSEL_PS0_M   0x00000030
 
#define ADC_TSSEL_PS0_0   0x00000000
 
#define ADC_SSPRI_SS3_M   0x00003000
 
#define ADC_SSPRI_SS2_M   0x00000300
 
#define ADC_SSPRI_SS1_M   0x00000030
 
#define ADC_SSPRI_SS0_M   0x00000003
 
#define ADC_SPC_PHASE_M   0x0000000F
 
#define ADC_SPC_PHASE_0   0x00000000
 
#define ADC_SPC_PHASE_22_5   0x00000001
 
#define ADC_SPC_PHASE_45   0x00000002
 
#define ADC_SPC_PHASE_67_5   0x00000003
 
#define ADC_SPC_PHASE_90   0x00000004
 
#define ADC_SPC_PHASE_112_5   0x00000005
 
#define ADC_SPC_PHASE_135   0x00000006
 
#define ADC_SPC_PHASE_157_5   0x00000007
 
#define ADC_SPC_PHASE_180   0x00000008
 
#define ADC_SPC_PHASE_202_5   0x00000009
 
#define ADC_SPC_PHASE_225   0x0000000A
 
#define ADC_SPC_PHASE_247_5   0x0000000B
 
#define ADC_SPC_PHASE_270   0x0000000C
 
#define ADC_SPC_PHASE_292_5   0x0000000D
 
#define ADC_SPC_PHASE_315   0x0000000E
 
#define ADC_SPC_PHASE_337_5   0x0000000F
 
#define ADC_PSSI_GSYNC   0x80000000
 
#define ADC_PSSI_SYNCWAIT   0x08000000
 
#define ADC_PSSI_SS3   0x00000008
 
#define ADC_PSSI_SS2   0x00000004
 
#define ADC_PSSI_SS1   0x00000002
 
#define ADC_PSSI_SS0   0x00000001
 
#define ADC_SAC_AVG_M   0x00000007
 
#define ADC_SAC_AVG_OFF   0x00000000
 
#define ADC_SAC_AVG_2X   0x00000001
 
#define ADC_SAC_AVG_4X   0x00000002
 
#define ADC_SAC_AVG_8X   0x00000003
 
#define ADC_SAC_AVG_16X   0x00000004
 
#define ADC_SAC_AVG_32X   0x00000005
 
#define ADC_SAC_AVG_64X   0x00000006
 
#define ADC_DCISC_DCINT7   0x00000080
 
#define ADC_DCISC_DCINT6   0x00000040
 
#define ADC_DCISC_DCINT5   0x00000020
 
#define ADC_DCISC_DCINT4   0x00000010
 
#define ADC_DCISC_DCINT3   0x00000008
 
#define ADC_DCISC_DCINT2   0x00000004
 
#define ADC_DCISC_DCINT1   0x00000002
 
#define ADC_DCISC_DCINT0   0x00000001
 
#define ADC_CTL_VREF_M   0x00000001
 
#define ADC_CTL_VREF_INTERNAL   0x00000000
 
#define ADC_CTL_VREF_EXT_3V   0x00000001
 
#define ADC_SSMUX0_MUX7_M   0xF0000000
 
#define ADC_SSMUX0_MUX6_M   0x0F000000
 
#define ADC_SSMUX0_MUX5_M   0x00F00000
 
#define ADC_SSMUX0_MUX4_M   0x000F0000
 
#define ADC_SSMUX0_MUX3_M   0x0000F000
 
#define ADC_SSMUX0_MUX2_M   0x00000F00
 
#define ADC_SSMUX0_MUX1_M   0x000000F0
 
#define ADC_SSMUX0_MUX0_M   0x0000000F
 
#define ADC_SSMUX0_MUX7_S   28
 
#define ADC_SSMUX0_MUX6_S   24
 
#define ADC_SSMUX0_MUX5_S   20
 
#define ADC_SSMUX0_MUX4_S   16
 
#define ADC_SSMUX0_MUX3_S   12
 
#define ADC_SSMUX0_MUX2_S   8
 
#define ADC_SSMUX0_MUX1_S   4
 
#define ADC_SSMUX0_MUX0_S   0
 
#define ADC_SSCTL0_TS7   0x80000000
 
#define ADC_SSCTL0_IE7   0x40000000
 
#define ADC_SSCTL0_END7   0x20000000
 
#define ADC_SSCTL0_D7   0x10000000
 
#define ADC_SSCTL0_TS6   0x08000000
 
#define ADC_SSCTL0_IE6   0x04000000
 
#define ADC_SSCTL0_END6   0x02000000
 
#define ADC_SSCTL0_D6   0x01000000
 
#define ADC_SSCTL0_TS5   0x00800000
 
#define ADC_SSCTL0_IE5   0x00400000
 
#define ADC_SSCTL0_END5   0x00200000
 
#define ADC_SSCTL0_D5   0x00100000
 
#define ADC_SSCTL0_TS4   0x00080000
 
#define ADC_SSCTL0_IE4   0x00040000
 
#define ADC_SSCTL0_END4   0x00020000
 
#define ADC_SSCTL0_D4   0x00010000
 
#define ADC_SSCTL0_TS3   0x00008000
 
#define ADC_SSCTL0_IE3   0x00004000
 
#define ADC_SSCTL0_END3   0x00002000
 
#define ADC_SSCTL0_D3   0x00001000
 
#define ADC_SSCTL0_TS2   0x00000800
 
#define ADC_SSCTL0_IE2   0x00000400
 
#define ADC_SSCTL0_END2   0x00000200
 
#define ADC_SSCTL0_D2   0x00000100
 
#define ADC_SSCTL0_TS1   0x00000080
 
#define ADC_SSCTL0_IE1   0x00000040
 
#define ADC_SSCTL0_END1   0x00000020
 
#define ADC_SSCTL0_D1   0x00000010
 
#define ADC_SSCTL0_TS0   0x00000008
 
#define ADC_SSCTL0_IE0   0x00000004
 
#define ADC_SSCTL0_END0   0x00000002
 
#define ADC_SSCTL0_D0   0x00000001
 
#define ADC_SSFIFO0_DATA_M   0x00000FFF
 
#define ADC_SSFIFO0_DATA_S   0
 
#define ADC_SSFSTAT0_FULL   0x00001000
 
#define ADC_SSFSTAT0_EMPTY   0x00000100
 
#define ADC_SSFSTAT0_HPTR_M   0x000000F0
 
#define ADC_SSFSTAT0_TPTR_M   0x0000000F
 
#define ADC_SSFSTAT0_HPTR_S   4
 
#define ADC_SSFSTAT0_TPTR_S   0
 
#define ADC_SSOP0_S7DCOP   0x10000000
 
#define ADC_SSOP0_S6DCOP   0x01000000
 
#define ADC_SSOP0_S5DCOP   0x00100000
 
#define ADC_SSOP0_S4DCOP   0x00010000
 
#define ADC_SSOP0_S3DCOP   0x00001000
 
#define ADC_SSOP0_S2DCOP   0x00000100
 
#define ADC_SSOP0_S1DCOP   0x00000010
 
#define ADC_SSOP0_S0DCOP   0x00000001
 
#define ADC_SSDC0_S7DCSEL_M   0xF0000000
 
#define ADC_SSDC0_S6DCSEL_M   0x0F000000
 
#define ADC_SSDC0_S5DCSEL_M   0x00F00000
 
#define ADC_SSDC0_S4DCSEL_M   0x000F0000
 
#define ADC_SSDC0_S3DCSEL_M   0x0000F000
 
#define ADC_SSDC0_S2DCSEL_M   0x00000F00
 
#define ADC_SSDC0_S1DCSEL_M   0x000000F0
 
#define ADC_SSDC0_S0DCSEL_M   0x0000000F
 
#define ADC_SSDC0_S6DCSEL_S   24
 
#define ADC_SSDC0_S5DCSEL_S   20
 
#define ADC_SSDC0_S4DCSEL_S   16
 
#define ADC_SSDC0_S3DCSEL_S   12
 
#define ADC_SSDC0_S2DCSEL_S   8
 
#define ADC_SSDC0_S1DCSEL_S   4
 
#define ADC_SSDC0_S0DCSEL_S   0
 
#define ADC_SSEMUX0_EMUX7   0x10000000
 
#define ADC_SSEMUX0_EMUX6   0x01000000
 
#define ADC_SSEMUX0_EMUX5   0x00100000
 
#define ADC_SSEMUX0_EMUX4   0x00010000
 
#define ADC_SSEMUX0_EMUX3   0x00001000
 
#define ADC_SSEMUX0_EMUX2   0x00000100
 
#define ADC_SSEMUX0_EMUX1   0x00000010
 
#define ADC_SSEMUX0_EMUX0   0x00000001
 
#define ADC_SSTSH0_TSH7_M   0xF0000000
 
#define ADC_SSTSH0_TSH6_M   0x0F000000
 
#define ADC_SSTSH0_TSH5_M   0x00F00000
 
#define ADC_SSTSH0_TSH4_M   0x000F0000
 
#define ADC_SSTSH0_TSH3_M   0x0000F000
 
#define ADC_SSTSH0_TSH2_M   0x00000F00
 
#define ADC_SSTSH0_TSH1_M   0x000000F0
 
#define ADC_SSTSH0_TSH0_M   0x0000000F
 
#define ADC_SSTSH0_TSH7_S   28
 
#define ADC_SSTSH0_TSH6_S   24
 
#define ADC_SSTSH0_TSH5_S   20
 
#define ADC_SSTSH0_TSH4_S   16
 
#define ADC_SSTSH0_TSH3_S   12
 
#define ADC_SSTSH0_TSH2_S   8
 
#define ADC_SSTSH0_TSH1_S   4
 
#define ADC_SSTSH0_TSH0_S   0
 
#define ADC_SSMUX1_MUX3_M   0x0000F000
 
#define ADC_SSMUX1_MUX2_M   0x00000F00
 
#define ADC_SSMUX1_MUX1_M   0x000000F0
 
#define ADC_SSMUX1_MUX0_M   0x0000000F
 
#define ADC_SSMUX1_MUX3_S   12
 
#define ADC_SSMUX1_MUX2_S   8
 
#define ADC_SSMUX1_MUX1_S   4
 
#define ADC_SSMUX1_MUX0_S   0
 
#define ADC_SSCTL1_TS3   0x00008000
 
#define ADC_SSCTL1_IE3   0x00004000
 
#define ADC_SSCTL1_END3   0x00002000
 
#define ADC_SSCTL1_D3   0x00001000
 
#define ADC_SSCTL1_TS2   0x00000800
 
#define ADC_SSCTL1_IE2   0x00000400
 
#define ADC_SSCTL1_END2   0x00000200
 
#define ADC_SSCTL1_D2   0x00000100
 
#define ADC_SSCTL1_TS1   0x00000080
 
#define ADC_SSCTL1_IE1   0x00000040
 
#define ADC_SSCTL1_END1   0x00000020
 
#define ADC_SSCTL1_D1   0x00000010
 
#define ADC_SSCTL1_TS0   0x00000008
 
#define ADC_SSCTL1_IE0   0x00000004
 
#define ADC_SSCTL1_END0   0x00000002
 
#define ADC_SSCTL1_D0   0x00000001
 
#define ADC_SSFIFO1_DATA_M   0x00000FFF
 
#define ADC_SSFIFO1_DATA_S   0
 
#define ADC_SSFSTAT1_FULL   0x00001000
 
#define ADC_SSFSTAT1_EMPTY   0x00000100
 
#define ADC_SSFSTAT1_HPTR_M   0x000000F0
 
#define ADC_SSFSTAT1_TPTR_M   0x0000000F
 
#define ADC_SSFSTAT1_HPTR_S   4
 
#define ADC_SSFSTAT1_TPTR_S   0
 
#define ADC_SSOP1_S3DCOP   0x00001000
 
#define ADC_SSOP1_S2DCOP   0x00000100
 
#define ADC_SSOP1_S1DCOP   0x00000010
 
#define ADC_SSOP1_S0DCOP   0x00000001
 
#define ADC_SSDC1_S3DCSEL_M   0x0000F000
 
#define ADC_SSDC1_S2DCSEL_M   0x00000F00
 
#define ADC_SSDC1_S1DCSEL_M   0x000000F0
 
#define ADC_SSDC1_S0DCSEL_M   0x0000000F
 
#define ADC_SSDC1_S2DCSEL_S   8
 
#define ADC_SSDC1_S1DCSEL_S   4
 
#define ADC_SSDC1_S0DCSEL_S   0
 
#define ADC_SSEMUX1_EMUX3   0x00001000
 
#define ADC_SSEMUX1_EMUX2   0x00000100
 
#define ADC_SSEMUX1_EMUX1   0x00000010
 
#define ADC_SSEMUX1_EMUX0   0x00000001
 
#define ADC_SSTSH1_TSH3_M   0x0000F000
 
#define ADC_SSTSH1_TSH2_M   0x00000F00
 
#define ADC_SSTSH1_TSH1_M   0x000000F0
 
#define ADC_SSTSH1_TSH0_M   0x0000000F
 
#define ADC_SSTSH1_TSH3_S   12
 
#define ADC_SSTSH1_TSH2_S   8
 
#define ADC_SSTSH1_TSH1_S   4
 
#define ADC_SSTSH1_TSH0_S   0
 
#define ADC_SSMUX2_MUX3_M   0x0000F000
 
#define ADC_SSMUX2_MUX2_M   0x00000F00
 
#define ADC_SSMUX2_MUX1_M   0x000000F0
 
#define ADC_SSMUX2_MUX0_M   0x0000000F
 
#define ADC_SSMUX2_MUX3_S   12
 
#define ADC_SSMUX2_MUX2_S   8
 
#define ADC_SSMUX2_MUX1_S   4
 
#define ADC_SSMUX2_MUX0_S   0
 
#define ADC_SSCTL2_TS3   0x00008000
 
#define ADC_SSCTL2_IE3   0x00004000
 
#define ADC_SSCTL2_END3   0x00002000
 
#define ADC_SSCTL2_D3   0x00001000
 
#define ADC_SSCTL2_TS2   0x00000800
 
#define ADC_SSCTL2_IE2   0x00000400
 
#define ADC_SSCTL2_END2   0x00000200
 
#define ADC_SSCTL2_D2   0x00000100
 
#define ADC_SSCTL2_TS1   0x00000080
 
#define ADC_SSCTL2_IE1   0x00000040
 
#define ADC_SSCTL2_END1   0x00000020
 
#define ADC_SSCTL2_D1   0x00000010
 
#define ADC_SSCTL2_TS0   0x00000008
 
#define ADC_SSCTL2_IE0   0x00000004
 
#define ADC_SSCTL2_END0   0x00000002
 
#define ADC_SSCTL2_D0   0x00000001
 
#define ADC_SSFIFO2_DATA_M   0x00000FFF
 
#define ADC_SSFIFO2_DATA_S   0
 
#define ADC_SSFSTAT2_FULL   0x00001000
 
#define ADC_SSFSTAT2_EMPTY   0x00000100
 
#define ADC_SSFSTAT2_HPTR_M   0x000000F0
 
#define ADC_SSFSTAT2_TPTR_M   0x0000000F
 
#define ADC_SSFSTAT2_HPTR_S   4
 
#define ADC_SSFSTAT2_TPTR_S   0
 
#define ADC_SSOP2_S3DCOP   0x00001000
 
#define ADC_SSOP2_S2DCOP   0x00000100
 
#define ADC_SSOP2_S1DCOP   0x00000010
 
#define ADC_SSOP2_S0DCOP   0x00000001
 
#define ADC_SSDC2_S3DCSEL_M   0x0000F000
 
#define ADC_SSDC2_S2DCSEL_M   0x00000F00
 
#define ADC_SSDC2_S1DCSEL_M   0x000000F0
 
#define ADC_SSDC2_S0DCSEL_M   0x0000000F
 
#define ADC_SSDC2_S2DCSEL_S   8
 
#define ADC_SSDC2_S1DCSEL_S   4
 
#define ADC_SSDC2_S0DCSEL_S   0
 
#define ADC_SSEMUX2_EMUX3   0x00001000
 
#define ADC_SSEMUX2_EMUX2   0x00000100
 
#define ADC_SSEMUX2_EMUX1   0x00000010
 
#define ADC_SSEMUX2_EMUX0   0x00000001
 
#define ADC_SSTSH2_TSH3_M   0x0000F000
 
#define ADC_SSTSH2_TSH2_M   0x00000F00
 
#define ADC_SSTSH2_TSH1_M   0x000000F0
 
#define ADC_SSTSH2_TSH0_M   0x0000000F
 
#define ADC_SSTSH2_TSH3_S   12
 
#define ADC_SSTSH2_TSH2_S   8
 
#define ADC_SSTSH2_TSH1_S   4
 
#define ADC_SSTSH2_TSH0_S   0
 
#define ADC_SSMUX3_MUX0_M   0x0000000F
 
#define ADC_SSMUX3_MUX0_S   0
 
#define ADC_SSCTL3_TS0   0x00000008
 
#define ADC_SSCTL3_IE0   0x00000004
 
#define ADC_SSCTL3_END0   0x00000002
 
#define ADC_SSCTL3_D0   0x00000001
 
#define ADC_SSFIFO3_DATA_M   0x00000FFF
 
#define ADC_SSFIFO3_DATA_S   0
 
#define ADC_SSFSTAT3_FULL   0x00001000
 
#define ADC_SSFSTAT3_EMPTY   0x00000100
 
#define ADC_SSFSTAT3_HPTR_M   0x000000F0
 
#define ADC_SSFSTAT3_TPTR_M   0x0000000F
 
#define ADC_SSFSTAT3_HPTR_S   4
 
#define ADC_SSFSTAT3_TPTR_S   0
 
#define ADC_SSOP3_S0DCOP   0x00000001
 
#define ADC_SSDC3_S0DCSEL_M   0x0000000F
 
#define ADC_SSEMUX3_EMUX0   0x00000001
 
#define ADC_SSTSH3_TSH0_M   0x0000000F
 
#define ADC_SSTSH3_TSH0_S   0
 
#define ADC_DCRIC_DCTRIG7   0x00800000
 
#define ADC_DCRIC_DCTRIG6   0x00400000
 
#define ADC_DCRIC_DCTRIG5   0x00200000
 
#define ADC_DCRIC_DCTRIG4   0x00100000
 
#define ADC_DCRIC_DCTRIG3   0x00080000
 
#define ADC_DCRIC_DCTRIG2   0x00040000
 
#define ADC_DCRIC_DCTRIG1   0x00020000
 
#define ADC_DCRIC_DCTRIG0   0x00010000
 
#define ADC_DCRIC_DCINT7   0x00000080
 
#define ADC_DCRIC_DCINT6   0x00000040
 
#define ADC_DCRIC_DCINT5   0x00000020
 
#define ADC_DCRIC_DCINT4   0x00000010
 
#define ADC_DCRIC_DCINT3   0x00000008
 
#define ADC_DCRIC_DCINT2   0x00000004
 
#define ADC_DCRIC_DCINT1   0x00000002
 
#define ADC_DCRIC_DCINT0   0x00000001
 
#define ADC_DCCTL0_CTE   0x00001000
 
#define ADC_DCCTL0_CTC_M   0x00000C00
 
#define ADC_DCCTL0_CTC_LOW   0x00000000
 
#define ADC_DCCTL0_CTC_MID   0x00000400
 
#define ADC_DCCTL0_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL0_CTM_M   0x00000300
 
#define ADC_DCCTL0_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL0_CTM_ONCE   0x00000100
 
#define ADC_DCCTL0_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL0_CTM_HONCE   0x00000300
 
#define ADC_DCCTL0_CIE   0x00000010
 
#define ADC_DCCTL0_CIC_M   0x0000000C
 
#define ADC_DCCTL0_CIC_LOW   0x00000000
 
#define ADC_DCCTL0_CIC_MID   0x00000004
 
#define ADC_DCCTL0_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL0_CIM_M   0x00000003
 
#define ADC_DCCTL0_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL0_CIM_ONCE   0x00000001
 
#define ADC_DCCTL0_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL0_CIM_HONCE   0x00000003
 
#define ADC_DCCTL1_CTE   0x00001000
 
#define ADC_DCCTL1_CTC_M   0x00000C00
 
#define ADC_DCCTL1_CTC_LOW   0x00000000
 
#define ADC_DCCTL1_CTC_MID   0x00000400
 
#define ADC_DCCTL1_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL1_CTM_M   0x00000300
 
#define ADC_DCCTL1_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL1_CTM_ONCE   0x00000100
 
#define ADC_DCCTL1_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL1_CTM_HONCE   0x00000300
 
#define ADC_DCCTL1_CIE   0x00000010
 
#define ADC_DCCTL1_CIC_M   0x0000000C
 
#define ADC_DCCTL1_CIC_LOW   0x00000000
 
#define ADC_DCCTL1_CIC_MID   0x00000004
 
#define ADC_DCCTL1_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL1_CIM_M   0x00000003
 
#define ADC_DCCTL1_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL1_CIM_ONCE   0x00000001
 
#define ADC_DCCTL1_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL1_CIM_HONCE   0x00000003
 
#define ADC_DCCTL2_CTE   0x00001000
 
#define ADC_DCCTL2_CTC_M   0x00000C00
 
#define ADC_DCCTL2_CTC_LOW   0x00000000
 
#define ADC_DCCTL2_CTC_MID   0x00000400
 
#define ADC_DCCTL2_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL2_CTM_M   0x00000300
 
#define ADC_DCCTL2_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL2_CTM_ONCE   0x00000100
 
#define ADC_DCCTL2_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL2_CTM_HONCE   0x00000300
 
#define ADC_DCCTL2_CIE   0x00000010
 
#define ADC_DCCTL2_CIC_M   0x0000000C
 
#define ADC_DCCTL2_CIC_LOW   0x00000000
 
#define ADC_DCCTL2_CIC_MID   0x00000004
 
#define ADC_DCCTL2_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL2_CIM_M   0x00000003
 
#define ADC_DCCTL2_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL2_CIM_ONCE   0x00000001
 
#define ADC_DCCTL2_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL2_CIM_HONCE   0x00000003
 
#define ADC_DCCTL3_CTE   0x00001000
 
#define ADC_DCCTL3_CTC_M   0x00000C00
 
#define ADC_DCCTL3_CTC_LOW   0x00000000
 
#define ADC_DCCTL3_CTC_MID   0x00000400
 
#define ADC_DCCTL3_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL3_CTM_M   0x00000300
 
#define ADC_DCCTL3_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL3_CTM_ONCE   0x00000100
 
#define ADC_DCCTL3_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL3_CTM_HONCE   0x00000300
 
#define ADC_DCCTL3_CIE   0x00000010
 
#define ADC_DCCTL3_CIC_M   0x0000000C
 
#define ADC_DCCTL3_CIC_LOW   0x00000000
 
#define ADC_DCCTL3_CIC_MID   0x00000004
 
#define ADC_DCCTL3_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL3_CIM_M   0x00000003
 
#define ADC_DCCTL3_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL3_CIM_ONCE   0x00000001
 
#define ADC_DCCTL3_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL3_CIM_HONCE   0x00000003
 
#define ADC_DCCTL4_CTE   0x00001000
 
#define ADC_DCCTL4_CTC_M   0x00000C00
 
#define ADC_DCCTL4_CTC_LOW   0x00000000
 
#define ADC_DCCTL4_CTC_MID   0x00000400
 
#define ADC_DCCTL4_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL4_CTM_M   0x00000300
 
#define ADC_DCCTL4_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL4_CTM_ONCE   0x00000100
 
#define ADC_DCCTL4_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL4_CTM_HONCE   0x00000300
 
#define ADC_DCCTL4_CIE   0x00000010
 
#define ADC_DCCTL4_CIC_M   0x0000000C
 
#define ADC_DCCTL4_CIC_LOW   0x00000000
 
#define ADC_DCCTL4_CIC_MID   0x00000004
 
#define ADC_DCCTL4_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL4_CIM_M   0x00000003
 
#define ADC_DCCTL4_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL4_CIM_ONCE   0x00000001
 
#define ADC_DCCTL4_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL4_CIM_HONCE   0x00000003
 
#define ADC_DCCTL5_CTE   0x00001000
 
#define ADC_DCCTL5_CTC_M   0x00000C00
 
#define ADC_DCCTL5_CTC_LOW   0x00000000
 
#define ADC_DCCTL5_CTC_MID   0x00000400
 
#define ADC_DCCTL5_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL5_CTM_M   0x00000300
 
#define ADC_DCCTL5_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL5_CTM_ONCE   0x00000100
 
#define ADC_DCCTL5_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL5_CTM_HONCE   0x00000300
 
#define ADC_DCCTL5_CIE   0x00000010
 
#define ADC_DCCTL5_CIC_M   0x0000000C
 
#define ADC_DCCTL5_CIC_LOW   0x00000000
 
#define ADC_DCCTL5_CIC_MID   0x00000004
 
#define ADC_DCCTL5_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL5_CIM_M   0x00000003
 
#define ADC_DCCTL5_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL5_CIM_ONCE   0x00000001
 
#define ADC_DCCTL5_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL5_CIM_HONCE   0x00000003
 
#define ADC_DCCTL6_CTE   0x00001000
 
#define ADC_DCCTL6_CTC_M   0x00000C00
 
#define ADC_DCCTL6_CTC_LOW   0x00000000
 
#define ADC_DCCTL6_CTC_MID   0x00000400
 
#define ADC_DCCTL6_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL6_CTM_M   0x00000300
 
#define ADC_DCCTL6_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL6_CTM_ONCE   0x00000100
 
#define ADC_DCCTL6_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL6_CTM_HONCE   0x00000300
 
#define ADC_DCCTL6_CIE   0x00000010
 
#define ADC_DCCTL6_CIC_M   0x0000000C
 
#define ADC_DCCTL6_CIC_LOW   0x00000000
 
#define ADC_DCCTL6_CIC_MID   0x00000004
 
#define ADC_DCCTL6_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL6_CIM_M   0x00000003
 
#define ADC_DCCTL6_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL6_CIM_ONCE   0x00000001
 
#define ADC_DCCTL6_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL6_CIM_HONCE   0x00000003
 
#define ADC_DCCTL7_CTE   0x00001000
 
#define ADC_DCCTL7_CTC_M   0x00000C00
 
#define ADC_DCCTL7_CTC_LOW   0x00000000
 
#define ADC_DCCTL7_CTC_MID   0x00000400
 
#define ADC_DCCTL7_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL7_CTM_M   0x00000300
 
#define ADC_DCCTL7_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL7_CTM_ONCE   0x00000100
 
#define ADC_DCCTL7_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL7_CTM_HONCE   0x00000300
 
#define ADC_DCCTL7_CIE   0x00000010
 
#define ADC_DCCTL7_CIC_M   0x0000000C
 
#define ADC_DCCTL7_CIC_LOW   0x00000000
 
#define ADC_DCCTL7_CIC_MID   0x00000004
 
#define ADC_DCCTL7_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL7_CIM_M   0x00000003
 
#define ADC_DCCTL7_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL7_CIM_ONCE   0x00000001
 
#define ADC_DCCTL7_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL7_CIM_HONCE   0x00000003
 
#define ADC_DCCMP0_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP0_COMP0_M   0x00000FFF
 
#define ADC_DCCMP0_COMP1_S   16
 
#define ADC_DCCMP0_COMP0_S   0
 
#define ADC_DCCMP1_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP1_COMP0_M   0x00000FFF
 
#define ADC_DCCMP1_COMP1_S   16
 
#define ADC_DCCMP1_COMP0_S   0
 
#define ADC_DCCMP2_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP2_COMP0_M   0x00000FFF
 
#define ADC_DCCMP2_COMP1_S   16
 
#define ADC_DCCMP2_COMP0_S   0
 
#define ADC_DCCMP3_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP3_COMP0_M   0x00000FFF
 
#define ADC_DCCMP3_COMP1_S   16
 
#define ADC_DCCMP3_COMP0_S   0
 
#define ADC_DCCMP4_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP4_COMP0_M   0x00000FFF
 
#define ADC_DCCMP4_COMP1_S   16
 
#define ADC_DCCMP4_COMP0_S   0
 
#define ADC_DCCMP5_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP5_COMP0_M   0x00000FFF
 
#define ADC_DCCMP5_COMP1_S   16
 
#define ADC_DCCMP5_COMP0_S   0
 
#define ADC_DCCMP6_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP6_COMP0_M   0x00000FFF
 
#define ADC_DCCMP6_COMP1_S   16
 
#define ADC_DCCMP6_COMP0_S   0
 
#define ADC_DCCMP7_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP7_COMP0_M   0x00000FFF
 
#define ADC_DCCMP7_COMP1_S   16
 
#define ADC_DCCMP7_COMP0_S   0
 
#define ADC_PP_APSHT   0x01000000
 
#define ADC_PP_TS   0x00800000
 
#define ADC_PP_RSL_M   0x007C0000
 
#define ADC_PP_TYPE_M   0x00030000
 
#define ADC_PP_TYPE_SAR   0x00000000
 
#define ADC_PP_DC_M   0x0000FC00
 
#define ADC_PP_CH_M   0x000003F0
 
#define ADC_PP_MCR_M   0x0000000F
 
#define ADC_PP_MCR_FULL   0x00000007
 
#define ADC_PP_MSR_M   0x0000000F
 
#define ADC_PP_MSR_125K   0x00000001
 
#define ADC_PP_MSR_250K   0x00000003
 
#define ADC_PP_MSR_500K   0x00000005
 
#define ADC_PP_MSR_1M   0x00000007
 
#define ADC_PP_RSL_S   18
 
#define ADC_PP_DC_S   10
 
#define ADC_PP_CH_S   4
 
#define ADC_PC_SR_M   0x0000000F
 
#define ADC_PC_SR_125K   0x00000001
 
#define ADC_PC_SR_250K   0x00000003
 
#define ADC_PC_SR_500K   0x00000005
 
#define ADC_PC_SR_1M   0x00000007
 
#define ADC_PC_MCR_M   0x0000000F
 
#define ADC_PC_MCR_1_8   0x00000001
 
#define ADC_PC_MCR_1_4   0x00000003
 
#define ADC_PC_MCR_1_2   0x00000005
 
#define ADC_PC_MCR_FULL   0x00000007
 
#define ADC_CC_CLKDIV_M   0x000003F0
 
#define ADC_CC_CS_M   0x0000000F
 
#define ADC_CC_CS_SYSPLL   0x00000000
 
#define ADC_CC_CS_PIOSC   0x00000001
 
#define ADC_CC_CS_MOSC   0x00000002
 
#define ADC_CC_CLKDIV_S   4
 

Macro Definition Documentation

§ ADC_O_ACTSS

#define ADC_O_ACTSS   0x00000000

Referenced by ADCBusy(), ADCSequenceDisable(), ADCSequenceDMADisable(), ADCSequenceDMAEnable(), and ADCSequenceEnable().

§ ADC_O_RIS

#define ADC_O_RIS   0x00000004

Referenced by ADCIntStatus(), and ADCIntStatusEx().

§ ADC_O_IM

#define ADC_O_IM   0x00000008

Referenced by ADCComparatorIntDisable(), ADCComparatorIntEnable(), ADCIntDisable(), ADCIntDisableEx(), ADCIntEnable(), and ADCIntEnableEx().

§ ADC_O_ISC

#define ADC_O_ISC   0x0000000C

Referenced by ADCIntClear(), ADCIntClearEx(), ADCIntEnable(), ADCIntStatus(), and ADCIntStatusEx().

§ ADC_O_OSTAT

#define ADC_O_OSTAT   0x00000010

Referenced by ADCSequenceOverflow(), and ADCSequenceOverflowClear().

§ ADC_O_EMUX

#define ADC_O_EMUX   0x00000014

Referenced by ADCSequenceConfigure().

§ ADC_O_USTAT

#define ADC_O_USTAT   0x00000018

Referenced by ADCSequenceUnderflow(), and ADCSequenceUnderflowClear().

§ ADC_O_TSSEL

#define ADC_O_TSSEL   0x0000001C

§ ADC_O_SSPRI

#define ADC_O_SSPRI   0x00000020

Referenced by ADCSequenceConfigure().

§ ADC_O_SPC

#define ADC_O_SPC   0x00000024

Referenced by ADCPhaseDelayGet(), and ADCPhaseDelaySet().

§ ADC_O_PSSI

#define ADC_O_PSSI   0x00000028

Referenced by ADCProcessorTrigger().

§ ADC_O_SAC

#define ADC_O_SAC   0x00000030

Referenced by ADCHardwareOversampleConfigure().

§ ADC_O_DCISC

#define ADC_O_DCISC   0x00000034

Referenced by ADCComparatorIntClear(), and ADCComparatorIntStatus().

§ ADC_O_CTL

#define ADC_O_CTL   0x00000038

Referenced by ADCReferenceGet(), and ADCReferenceSet().

§ ADC_O_SSMUX0

#define ADC_O_SSMUX0   0x00000040

§ ADC_O_SSCTL0

#define ADC_O_SSCTL0   0x00000044

§ ADC_O_SSFIFO0

#define ADC_O_SSFIFO0   0x00000048

§ ADC_O_SSFSTAT0

#define ADC_O_SSFSTAT0   0x0000004C

§ ADC_O_SSOP0

#define ADC_O_SSOP0   0x00000050

§ ADC_O_SSDC0

#define ADC_O_SSDC0   0x00000054

§ ADC_O_SSEMUX0

#define ADC_O_SSEMUX0   0x00000058

§ ADC_O_SSTSH0

#define ADC_O_SSTSH0   0x0000005C

§ ADC_O_SSMUX1

#define ADC_O_SSMUX1   0x00000060

§ ADC_O_SSCTL1

#define ADC_O_SSCTL1   0x00000064

§ ADC_O_SSFIFO1

#define ADC_O_SSFIFO1   0x00000068

§ ADC_O_SSFSTAT1

#define ADC_O_SSFSTAT1   0x0000006C

§ ADC_O_SSOP1

#define ADC_O_SSOP1   0x00000070

§ ADC_O_SSDC1

#define ADC_O_SSDC1   0x00000074

§ ADC_O_SSEMUX1

#define ADC_O_SSEMUX1   0x00000078

§ ADC_O_SSTSH1

#define ADC_O_SSTSH1   0x0000007C

§ ADC_O_SSMUX2

#define ADC_O_SSMUX2   0x00000080

§ ADC_O_SSCTL2

#define ADC_O_SSCTL2   0x00000084

§ ADC_O_SSFIFO2

#define ADC_O_SSFIFO2   0x00000088

§ ADC_O_SSFSTAT2

#define ADC_O_SSFSTAT2   0x0000008C

§ ADC_O_SSOP2

#define ADC_O_SSOP2   0x00000090

§ ADC_O_SSDC2

#define ADC_O_SSDC2   0x00000094

§ ADC_O_SSEMUX2

#define ADC_O_SSEMUX2   0x00000098

§ ADC_O_SSTSH2

#define ADC_O_SSTSH2   0x0000009C

§ ADC_O_SSMUX3

#define ADC_O_SSMUX3   0x000000A0

§ ADC_O_SSCTL3

#define ADC_O_SSCTL3   0x000000A4

§ ADC_O_SSFIFO3

#define ADC_O_SSFIFO3   0x000000A8

§ ADC_O_SSFSTAT3

#define ADC_O_SSFSTAT3   0x000000AC

§ ADC_O_SSOP3

#define ADC_O_SSOP3   0x000000B0

§ ADC_O_SSDC3

#define ADC_O_SSDC3   0x000000B4

§ ADC_O_SSEMUX3

#define ADC_O_SSEMUX3   0x000000B8

§ ADC_O_SSTSH3

#define ADC_O_SSTSH3   0x000000BC

§ ADC_O_DCRIC

#define ADC_O_DCRIC   0x00000D00

Referenced by ADCComparatorReset().

§ ADC_O_DCCTL0

#define ADC_O_DCCTL0   0x00000E00

Referenced by ADCComparatorConfigure().

§ ADC_O_DCCTL1

#define ADC_O_DCCTL1   0x00000E04

§ ADC_O_DCCTL2

#define ADC_O_DCCTL2   0x00000E08

§ ADC_O_DCCTL3

#define ADC_O_DCCTL3   0x00000E0C

§ ADC_O_DCCTL4

#define ADC_O_DCCTL4   0x00000E10

§ ADC_O_DCCTL5

#define ADC_O_DCCTL5   0x00000E14

§ ADC_O_DCCTL6

#define ADC_O_DCCTL6   0x00000E18

§ ADC_O_DCCTL7

#define ADC_O_DCCTL7   0x00000E1C

§ ADC_O_DCCMP0

#define ADC_O_DCCMP0   0x00000E40

Referenced by ADCComparatorRegionSet().

§ ADC_O_DCCMP1

#define ADC_O_DCCMP1   0x00000E44

§ ADC_O_DCCMP2

#define ADC_O_DCCMP2   0x00000E48

§ ADC_O_DCCMP3

#define ADC_O_DCCMP3   0x00000E4C

§ ADC_O_DCCMP4

#define ADC_O_DCCMP4   0x00000E50

§ ADC_O_DCCMP5

#define ADC_O_DCCMP5   0x00000E54

§ ADC_O_DCCMP6

#define ADC_O_DCCMP6   0x00000E58

§ ADC_O_DCCMP7

#define ADC_O_DCCMP7   0x00000E5C

§ ADC_O_PP

#define ADC_O_PP   0x00000FC0

§ ADC_O_PC

#define ADC_O_PC   0x00000FC4

Referenced by ADCClockConfigGet(), and ADCClockConfigSet().

§ ADC_O_CC

#define ADC_O_CC   0x00000FC8

Referenced by ADCClockConfigGet(), and ADCClockConfigSet().

§ ADC_ACTSS_BUSY

#define ADC_ACTSS_BUSY   0x00010000

Referenced by ADCBusy().

§ ADC_ACTSS_ADEN3

#define ADC_ACTSS_ADEN3   0x00000800

§ ADC_ACTSS_ADEN2

#define ADC_ACTSS_ADEN2   0x00000400

§ ADC_ACTSS_ADEN1

#define ADC_ACTSS_ADEN1   0x00000200

§ ADC_ACTSS_ADEN0

#define ADC_ACTSS_ADEN0   0x00000100

§ ADC_ACTSS_ASEN3

#define ADC_ACTSS_ASEN3   0x00000008

§ ADC_ACTSS_ASEN2

#define ADC_ACTSS_ASEN2   0x00000004

§ ADC_ACTSS_ASEN1

#define ADC_ACTSS_ASEN1   0x00000002

§ ADC_ACTSS_ASEN0

#define ADC_ACTSS_ASEN0   0x00000001

§ ADC_RIS_INRDC

#define ADC_RIS_INRDC   0x00010000

Referenced by ADCIntStatusEx().

§ ADC_RIS_DMAINR3

#define ADC_RIS_DMAINR3   0x00000800

§ ADC_RIS_DMAINR2

#define ADC_RIS_DMAINR2   0x00000400

§ ADC_RIS_DMAINR1

#define ADC_RIS_DMAINR1   0x00000200

§ ADC_RIS_DMAINR0

#define ADC_RIS_DMAINR0   0x00000100

§ ADC_RIS_INR3

#define ADC_RIS_INR3   0x00000008

§ ADC_RIS_INR2

#define ADC_RIS_INR2   0x00000004

§ ADC_RIS_INR1

#define ADC_RIS_INR1   0x00000002

§ ADC_RIS_INR0

#define ADC_RIS_INR0   0x00000001

§ ADC_IM_DCONSS3

#define ADC_IM_DCONSS3   0x00080000

§ ADC_IM_DCONSS2

#define ADC_IM_DCONSS2   0x00040000

§ ADC_IM_DCONSS1

#define ADC_IM_DCONSS1   0x00020000

§ ADC_IM_DCONSS0

#define ADC_IM_DCONSS0   0x00010000

§ ADC_IM_DMAMASK3

#define ADC_IM_DMAMASK3   0x00000800

§ ADC_IM_DMAMASK2

#define ADC_IM_DMAMASK2   0x00000400

§ ADC_IM_DMAMASK1

#define ADC_IM_DMAMASK1   0x00000200

§ ADC_IM_DMAMASK0

#define ADC_IM_DMAMASK0   0x00000100

§ ADC_IM_MASK3

#define ADC_IM_MASK3   0x00000008

§ ADC_IM_MASK2

#define ADC_IM_MASK2   0x00000004

§ ADC_IM_MASK1

#define ADC_IM_MASK1   0x00000002

§ ADC_IM_MASK0

#define ADC_IM_MASK0   0x00000001

§ ADC_ISC_DCINSS3

#define ADC_ISC_DCINSS3   0x00080000

§ ADC_ISC_DCINSS2

#define ADC_ISC_DCINSS2   0x00040000

§ ADC_ISC_DCINSS1

#define ADC_ISC_DCINSS1   0x00020000

§ ADC_ISC_DCINSS0

#define ADC_ISC_DCINSS0   0x00010000

§ ADC_ISC_DMAIN3

#define ADC_ISC_DMAIN3   0x00000800

§ ADC_ISC_DMAIN2

#define ADC_ISC_DMAIN2   0x00000400

§ ADC_ISC_DMAIN1

#define ADC_ISC_DMAIN1   0x00000200

§ ADC_ISC_DMAIN0

#define ADC_ISC_DMAIN0   0x00000100

§ ADC_ISC_IN3

#define ADC_ISC_IN3   0x00000008

§ ADC_ISC_IN2

#define ADC_ISC_IN2   0x00000004

§ ADC_ISC_IN1

#define ADC_ISC_IN1   0x00000002

§ ADC_ISC_IN0

#define ADC_ISC_IN0   0x00000001

§ ADC_OSTAT_OV3

#define ADC_OSTAT_OV3   0x00000008

§ ADC_OSTAT_OV2

#define ADC_OSTAT_OV2   0x00000004

§ ADC_OSTAT_OV1

#define ADC_OSTAT_OV1   0x00000002

§ ADC_OSTAT_OV0

#define ADC_OSTAT_OV0   0x00000001

§ ADC_EMUX_EM3_M

#define ADC_EMUX_EM3_M   0x0000F000

§ ADC_EMUX_EM3_PROCESSOR

#define ADC_EMUX_EM3_PROCESSOR   0x00000000

§ ADC_EMUX_EM3_COMP0

#define ADC_EMUX_EM3_COMP0   0x00001000

§ ADC_EMUX_EM3_COMP1

#define ADC_EMUX_EM3_COMP1   0x00002000

§ ADC_EMUX_EM3_COMP2

#define ADC_EMUX_EM3_COMP2   0x00003000

§ ADC_EMUX_EM3_EXTERNAL

#define ADC_EMUX_EM3_EXTERNAL   0x00004000

§ ADC_EMUX_EM3_TIMER

#define ADC_EMUX_EM3_TIMER   0x00005000

§ ADC_EMUX_EM3_PWM0

#define ADC_EMUX_EM3_PWM0   0x00006000

§ ADC_EMUX_EM3_PWM1

#define ADC_EMUX_EM3_PWM1   0x00007000

§ ADC_EMUX_EM3_PWM2

#define ADC_EMUX_EM3_PWM2   0x00008000

§ ADC_EMUX_EM3_PWM3

#define ADC_EMUX_EM3_PWM3   0x00009000

§ ADC_EMUX_EM3_NEVER

#define ADC_EMUX_EM3_NEVER   0x0000E000

§ ADC_EMUX_EM3_ALWAYS

#define ADC_EMUX_EM3_ALWAYS   0x0000F000

§ ADC_EMUX_EM2_M

#define ADC_EMUX_EM2_M   0x00000F00

§ ADC_EMUX_EM2_PROCESSOR

#define ADC_EMUX_EM2_PROCESSOR   0x00000000

§ ADC_EMUX_EM2_COMP0

#define ADC_EMUX_EM2_COMP0   0x00000100

§ ADC_EMUX_EM2_COMP1

#define ADC_EMUX_EM2_COMP1   0x00000200

§ ADC_EMUX_EM2_COMP2

#define ADC_EMUX_EM2_COMP2   0x00000300

§ ADC_EMUX_EM2_EXTERNAL

#define ADC_EMUX_EM2_EXTERNAL   0x00000400

§ ADC_EMUX_EM2_TIMER

#define ADC_EMUX_EM2_TIMER   0x00000500

§ ADC_EMUX_EM2_PWM0

#define ADC_EMUX_EM2_PWM0   0x00000600

§ ADC_EMUX_EM2_PWM1

#define ADC_EMUX_EM2_PWM1   0x00000700

§ ADC_EMUX_EM2_PWM2

#define ADC_EMUX_EM2_PWM2   0x00000800

§ ADC_EMUX_EM2_PWM3

#define ADC_EMUX_EM2_PWM3   0x00000900

§ ADC_EMUX_EM2_NEVER

#define ADC_EMUX_EM2_NEVER   0x00000E00

§ ADC_EMUX_EM2_ALWAYS

#define ADC_EMUX_EM2_ALWAYS   0x00000F00

§ ADC_EMUX_EM1_M

#define ADC_EMUX_EM1_M   0x000000F0

§ ADC_EMUX_EM1_PROCESSOR

#define ADC_EMUX_EM1_PROCESSOR   0x00000000

§ ADC_EMUX_EM1_COMP0

#define ADC_EMUX_EM1_COMP0   0x00000010

§ ADC_EMUX_EM1_COMP1

#define ADC_EMUX_EM1_COMP1   0x00000020

§ ADC_EMUX_EM1_COMP2

#define ADC_EMUX_EM1_COMP2   0x00000030

§ ADC_EMUX_EM1_EXTERNAL

#define ADC_EMUX_EM1_EXTERNAL   0x00000040

§ ADC_EMUX_EM1_TIMER

#define ADC_EMUX_EM1_TIMER   0x00000050

§ ADC_EMUX_EM1_PWM0

#define ADC_EMUX_EM1_PWM0   0x00000060

§ ADC_EMUX_EM1_PWM1

#define ADC_EMUX_EM1_PWM1   0x00000070

§ ADC_EMUX_EM1_PWM2

#define ADC_EMUX_EM1_PWM2   0x00000080

§ ADC_EMUX_EM1_PWM3

#define ADC_EMUX_EM1_PWM3   0x00000090

§ ADC_EMUX_EM1_NEVER

#define ADC_EMUX_EM1_NEVER   0x000000E0

§ ADC_EMUX_EM1_ALWAYS

#define ADC_EMUX_EM1_ALWAYS   0x000000F0

§ ADC_EMUX_EM0_M

#define ADC_EMUX_EM0_M   0x0000000F

§ ADC_EMUX_EM0_PROCESSOR

#define ADC_EMUX_EM0_PROCESSOR   0x00000000

§ ADC_EMUX_EM0_COMP0

#define ADC_EMUX_EM0_COMP0   0x00000001

§ ADC_EMUX_EM0_COMP1

#define ADC_EMUX_EM0_COMP1   0x00000002

§ ADC_EMUX_EM0_COMP2

#define ADC_EMUX_EM0_COMP2   0x00000003

§ ADC_EMUX_EM0_EXTERNAL

#define ADC_EMUX_EM0_EXTERNAL   0x00000004

§ ADC_EMUX_EM0_TIMER

#define ADC_EMUX_EM0_TIMER   0x00000005

§ ADC_EMUX_EM0_PWM0

#define ADC_EMUX_EM0_PWM0   0x00000006

§ ADC_EMUX_EM0_PWM1

#define ADC_EMUX_EM0_PWM1   0x00000007

§ ADC_EMUX_EM0_PWM2

#define ADC_EMUX_EM0_PWM2   0x00000008

§ ADC_EMUX_EM0_PWM3

#define ADC_EMUX_EM0_PWM3   0x00000009

§ ADC_EMUX_EM0_NEVER

#define ADC_EMUX_EM0_NEVER   0x0000000E

§ ADC_EMUX_EM0_ALWAYS

#define ADC_EMUX_EM0_ALWAYS   0x0000000F

§ ADC_USTAT_UV3

#define ADC_USTAT_UV3   0x00000008

§ ADC_USTAT_UV2

#define ADC_USTAT_UV2   0x00000004

§ ADC_USTAT_UV1

#define ADC_USTAT_UV1   0x00000002

§ ADC_USTAT_UV0

#define ADC_USTAT_UV0   0x00000001

§ ADC_TSSEL_PS3_M

#define ADC_TSSEL_PS3_M   0x30000000

§ ADC_TSSEL_PS3_0

#define ADC_TSSEL_PS3_0   0x00000000

§ ADC_TSSEL_PS2_M

#define ADC_TSSEL_PS2_M   0x00300000

§ ADC_TSSEL_PS2_0

#define ADC_TSSEL_PS2_0   0x00000000

§ ADC_TSSEL_PS1_M

#define ADC_TSSEL_PS1_M   0x00003000

§ ADC_TSSEL_PS1_0

#define ADC_TSSEL_PS1_0   0x00000000

§ ADC_TSSEL_PS0_M

#define ADC_TSSEL_PS0_M   0x00000030

§ ADC_TSSEL_PS0_0

#define ADC_TSSEL_PS0_0   0x00000000

§ ADC_SSPRI_SS3_M

#define ADC_SSPRI_SS3_M   0x00003000

§ ADC_SSPRI_SS2_M

#define ADC_SSPRI_SS2_M   0x00000300

§ ADC_SSPRI_SS1_M

#define ADC_SSPRI_SS1_M   0x00000030

§ ADC_SSPRI_SS0_M

#define ADC_SSPRI_SS0_M   0x00000003

§ ADC_SPC_PHASE_M

#define ADC_SPC_PHASE_M   0x0000000F

§ ADC_SPC_PHASE_0

#define ADC_SPC_PHASE_0   0x00000000

§ ADC_SPC_PHASE_22_5

#define ADC_SPC_PHASE_22_5   0x00000001

§ ADC_SPC_PHASE_45

#define ADC_SPC_PHASE_45   0x00000002

§ ADC_SPC_PHASE_67_5

#define ADC_SPC_PHASE_67_5   0x00000003

§ ADC_SPC_PHASE_90

#define ADC_SPC_PHASE_90   0x00000004

§ ADC_SPC_PHASE_112_5

#define ADC_SPC_PHASE_112_5   0x00000005

§ ADC_SPC_PHASE_135

#define ADC_SPC_PHASE_135   0x00000006

§ ADC_SPC_PHASE_157_5

#define ADC_SPC_PHASE_157_5   0x00000007

§ ADC_SPC_PHASE_180

#define ADC_SPC_PHASE_180   0x00000008

§ ADC_SPC_PHASE_202_5

#define ADC_SPC_PHASE_202_5   0x00000009

§ ADC_SPC_PHASE_225

#define ADC_SPC_PHASE_225   0x0000000A

§ ADC_SPC_PHASE_247_5

#define ADC_SPC_PHASE_247_5   0x0000000B

§ ADC_SPC_PHASE_270

#define ADC_SPC_PHASE_270   0x0000000C

§ ADC_SPC_PHASE_292_5

#define ADC_SPC_PHASE_292_5   0x0000000D

§ ADC_SPC_PHASE_315

#define ADC_SPC_PHASE_315   0x0000000E

§ ADC_SPC_PHASE_337_5

#define ADC_SPC_PHASE_337_5   0x0000000F

§ ADC_PSSI_GSYNC

#define ADC_PSSI_GSYNC   0x80000000

§ ADC_PSSI_SYNCWAIT

#define ADC_PSSI_SYNCWAIT   0x08000000

§ ADC_PSSI_SS3

#define ADC_PSSI_SS3   0x00000008

§ ADC_PSSI_SS2

#define ADC_PSSI_SS2   0x00000004

§ ADC_PSSI_SS1

#define ADC_PSSI_SS1   0x00000002

§ ADC_PSSI_SS0

#define ADC_PSSI_SS0   0x00000001

§ ADC_SAC_AVG_M

#define ADC_SAC_AVG_M   0x00000007

§ ADC_SAC_AVG_OFF

#define ADC_SAC_AVG_OFF   0x00000000

§ ADC_SAC_AVG_2X

#define ADC_SAC_AVG_2X   0x00000001

§ ADC_SAC_AVG_4X

#define ADC_SAC_AVG_4X   0x00000002

§ ADC_SAC_AVG_8X

#define ADC_SAC_AVG_8X   0x00000003

§ ADC_SAC_AVG_16X

#define ADC_SAC_AVG_16X   0x00000004

§ ADC_SAC_AVG_32X

#define ADC_SAC_AVG_32X   0x00000005

§ ADC_SAC_AVG_64X

#define ADC_SAC_AVG_64X   0x00000006

§ ADC_DCISC_DCINT7

#define ADC_DCISC_DCINT7   0x00000080

§ ADC_DCISC_DCINT6

#define ADC_DCISC_DCINT6   0x00000040

§ ADC_DCISC_DCINT5

#define ADC_DCISC_DCINT5   0x00000020

§ ADC_DCISC_DCINT4

#define ADC_DCISC_DCINT4   0x00000010

§ ADC_DCISC_DCINT3

#define ADC_DCISC_DCINT3   0x00000008

§ ADC_DCISC_DCINT2

#define ADC_DCISC_DCINT2   0x00000004

§ ADC_DCISC_DCINT1

#define ADC_DCISC_DCINT1   0x00000002

§ ADC_DCISC_DCINT0

#define ADC_DCISC_DCINT0   0x00000001

§ ADC_CTL_VREF_M

#define ADC_CTL_VREF_M   0x00000001

Referenced by ADCReferenceGet(), and ADCReferenceSet().

§ ADC_CTL_VREF_INTERNAL

#define ADC_CTL_VREF_INTERNAL   0x00000000

§ ADC_CTL_VREF_EXT_3V

#define ADC_CTL_VREF_EXT_3V   0x00000001

§ ADC_SSMUX0_MUX7_M

#define ADC_SSMUX0_MUX7_M   0xF0000000

§ ADC_SSMUX0_MUX6_M

#define ADC_SSMUX0_MUX6_M   0x0F000000

§ ADC_SSMUX0_MUX5_M

#define ADC_SSMUX0_MUX5_M   0x00F00000

§ ADC_SSMUX0_MUX4_M

#define ADC_SSMUX0_MUX4_M   0x000F0000

§ ADC_SSMUX0_MUX3_M

#define ADC_SSMUX0_MUX3_M   0x0000F000

§ ADC_SSMUX0_MUX2_M

#define ADC_SSMUX0_MUX2_M   0x00000F00

§ ADC_SSMUX0_MUX1_M

#define ADC_SSMUX0_MUX1_M   0x000000F0

§ ADC_SSMUX0_MUX0_M

#define ADC_SSMUX0_MUX0_M   0x0000000F

§ ADC_SSMUX0_MUX7_S

#define ADC_SSMUX0_MUX7_S   28

§ ADC_SSMUX0_MUX6_S

#define ADC_SSMUX0_MUX6_S   24

§ ADC_SSMUX0_MUX5_S

#define ADC_SSMUX0_MUX5_S   20

§ ADC_SSMUX0_MUX4_S

#define ADC_SSMUX0_MUX4_S   16

§ ADC_SSMUX0_MUX3_S

#define ADC_SSMUX0_MUX3_S   12

§ ADC_SSMUX0_MUX2_S

#define ADC_SSMUX0_MUX2_S   8

§ ADC_SSMUX0_MUX1_S

#define ADC_SSMUX0_MUX1_S   4

§ ADC_SSMUX0_MUX0_S

#define ADC_SSMUX0_MUX0_S   0

§ ADC_SSCTL0_TS7

#define ADC_SSCTL0_TS7   0x80000000

§ ADC_SSCTL0_IE7

#define ADC_SSCTL0_IE7   0x40000000

§ ADC_SSCTL0_END7

#define ADC_SSCTL0_END7   0x20000000

§ ADC_SSCTL0_D7

#define ADC_SSCTL0_D7   0x10000000

§ ADC_SSCTL0_TS6

#define ADC_SSCTL0_TS6   0x08000000

§ ADC_SSCTL0_IE6

#define ADC_SSCTL0_IE6   0x04000000

§ ADC_SSCTL0_END6

#define ADC_SSCTL0_END6   0x02000000

§ ADC_SSCTL0_D6

#define ADC_SSCTL0_D6   0x01000000

§ ADC_SSCTL0_TS5

#define ADC_SSCTL0_TS5   0x00800000

§ ADC_SSCTL0_IE5

#define ADC_SSCTL0_IE5   0x00400000

§ ADC_SSCTL0_END5

#define ADC_SSCTL0_END5   0x00200000

§ ADC_SSCTL0_D5

#define ADC_SSCTL0_D5   0x00100000

§ ADC_SSCTL0_TS4

#define ADC_SSCTL0_TS4   0x00080000

§ ADC_SSCTL0_IE4

#define ADC_SSCTL0_IE4   0x00040000

§ ADC_SSCTL0_END4

#define ADC_SSCTL0_END4   0x00020000

§ ADC_SSCTL0_D4

#define ADC_SSCTL0_D4   0x00010000

§ ADC_SSCTL0_TS3

#define ADC_SSCTL0_TS3   0x00008000

§ ADC_SSCTL0_IE3

#define ADC_SSCTL0_IE3   0x00004000

§ ADC_SSCTL0_END3

#define ADC_SSCTL0_END3   0x00002000

§ ADC_SSCTL0_D3

#define ADC_SSCTL0_D3   0x00001000

§ ADC_SSCTL0_TS2

#define ADC_SSCTL0_TS2   0x00000800

§ ADC_SSCTL0_IE2

#define ADC_SSCTL0_IE2   0x00000400

§ ADC_SSCTL0_END2

#define ADC_SSCTL0_END2   0x00000200

§ ADC_SSCTL0_D2

#define ADC_SSCTL0_D2   0x00000100

§ ADC_SSCTL0_TS1

#define ADC_SSCTL0_TS1   0x00000080

§ ADC_SSCTL0_IE1

#define ADC_SSCTL0_IE1   0x00000040

§ ADC_SSCTL0_END1

#define ADC_SSCTL0_END1   0x00000020

§ ADC_SSCTL0_D1

#define ADC_SSCTL0_D1   0x00000010

§ ADC_SSCTL0_TS0

#define ADC_SSCTL0_TS0   0x00000008

§ ADC_SSCTL0_IE0

#define ADC_SSCTL0_IE0   0x00000004

§ ADC_SSCTL0_END0

#define ADC_SSCTL0_END0   0x00000002

§ ADC_SSCTL0_D0

#define ADC_SSCTL0_D0   0x00000001

§ ADC_SSFIFO0_DATA_M

#define ADC_SSFIFO0_DATA_M   0x00000FFF

§ ADC_SSFIFO0_DATA_S

#define ADC_SSFIFO0_DATA_S   0

§ ADC_SSFSTAT0_FULL

#define ADC_SSFSTAT0_FULL   0x00001000

§ ADC_SSFSTAT0_EMPTY

#define ADC_SSFSTAT0_EMPTY   0x00000100

Referenced by ADCSequenceDataGet().

§ ADC_SSFSTAT0_HPTR_M

#define ADC_SSFSTAT0_HPTR_M   0x000000F0

§ ADC_SSFSTAT0_TPTR_M

#define ADC_SSFSTAT0_TPTR_M   0x0000000F

§ ADC_SSFSTAT0_HPTR_S

#define ADC_SSFSTAT0_HPTR_S   4

§ ADC_SSFSTAT0_TPTR_S

#define ADC_SSFSTAT0_TPTR_S   0

§ ADC_SSOP0_S7DCOP

#define ADC_SSOP0_S7DCOP   0x10000000

§ ADC_SSOP0_S6DCOP

#define ADC_SSOP0_S6DCOP   0x01000000

§ ADC_SSOP0_S5DCOP

#define ADC_SSOP0_S5DCOP   0x00100000

§ ADC_SSOP0_S4DCOP

#define ADC_SSOP0_S4DCOP   0x00010000

§ ADC_SSOP0_S3DCOP

#define ADC_SSOP0_S3DCOP   0x00001000

§ ADC_SSOP0_S2DCOP

#define ADC_SSOP0_S2DCOP   0x00000100

§ ADC_SSOP0_S1DCOP

#define ADC_SSOP0_S1DCOP   0x00000010

§ ADC_SSOP0_S0DCOP

#define ADC_SSOP0_S0DCOP   0x00000001

§ ADC_SSDC0_S7DCSEL_M

#define ADC_SSDC0_S7DCSEL_M   0xF0000000

§ ADC_SSDC0_S6DCSEL_M

#define ADC_SSDC0_S6DCSEL_M   0x0F000000

§ ADC_SSDC0_S5DCSEL_M

#define ADC_SSDC0_S5DCSEL_M   0x00F00000

§ ADC_SSDC0_S4DCSEL_M

#define ADC_SSDC0_S4DCSEL_M   0x000F0000

§ ADC_SSDC0_S3DCSEL_M

#define ADC_SSDC0_S3DCSEL_M   0x0000F000

§ ADC_SSDC0_S2DCSEL_M

#define ADC_SSDC0_S2DCSEL_M   0x00000F00

§ ADC_SSDC0_S1DCSEL_M

#define ADC_SSDC0_S1DCSEL_M   0x000000F0

§ ADC_SSDC0_S0DCSEL_M

#define ADC_SSDC0_S0DCSEL_M   0x0000000F

§ ADC_SSDC0_S6DCSEL_S

#define ADC_SSDC0_S6DCSEL_S   24

§ ADC_SSDC0_S5DCSEL_S

#define ADC_SSDC0_S5DCSEL_S   20

§ ADC_SSDC0_S4DCSEL_S

#define ADC_SSDC0_S4DCSEL_S   16

§ ADC_SSDC0_S3DCSEL_S

#define ADC_SSDC0_S3DCSEL_S   12

§ ADC_SSDC0_S2DCSEL_S

#define ADC_SSDC0_S2DCSEL_S   8

§ ADC_SSDC0_S1DCSEL_S

#define ADC_SSDC0_S1DCSEL_S   4

§ ADC_SSDC0_S0DCSEL_S

#define ADC_SSDC0_S0DCSEL_S   0

§ ADC_SSEMUX0_EMUX7

#define ADC_SSEMUX0_EMUX7   0x10000000

§ ADC_SSEMUX0_EMUX6

#define ADC_SSEMUX0_EMUX6   0x01000000

§ ADC_SSEMUX0_EMUX5

#define ADC_SSEMUX0_EMUX5   0x00100000

§ ADC_SSEMUX0_EMUX4

#define ADC_SSEMUX0_EMUX4   0x00010000

§ ADC_SSEMUX0_EMUX3

#define ADC_SSEMUX0_EMUX3   0x00001000

§ ADC_SSEMUX0_EMUX2

#define ADC_SSEMUX0_EMUX2   0x00000100

§ ADC_SSEMUX0_EMUX1

#define ADC_SSEMUX0_EMUX1   0x00000010

§ ADC_SSEMUX0_EMUX0

#define ADC_SSEMUX0_EMUX0   0x00000001

§ ADC_SSTSH0_TSH7_M

#define ADC_SSTSH0_TSH7_M   0xF0000000

§ ADC_SSTSH0_TSH6_M

#define ADC_SSTSH0_TSH6_M   0x0F000000

§ ADC_SSTSH0_TSH5_M

#define ADC_SSTSH0_TSH5_M   0x00F00000

§ ADC_SSTSH0_TSH4_M

#define ADC_SSTSH0_TSH4_M   0x000F0000

§ ADC_SSTSH0_TSH3_M

#define ADC_SSTSH0_TSH3_M   0x0000F000

§ ADC_SSTSH0_TSH2_M

#define ADC_SSTSH0_TSH2_M   0x00000F00

§ ADC_SSTSH0_TSH1_M

#define ADC_SSTSH0_TSH1_M   0x000000F0

§ ADC_SSTSH0_TSH0_M

#define ADC_SSTSH0_TSH0_M   0x0000000F

§ ADC_SSTSH0_TSH7_S

#define ADC_SSTSH0_TSH7_S   28

§ ADC_SSTSH0_TSH6_S

#define ADC_SSTSH0_TSH6_S   24

§ ADC_SSTSH0_TSH5_S

#define ADC_SSTSH0_TSH5_S   20

§ ADC_SSTSH0_TSH4_S

#define ADC_SSTSH0_TSH4_S   16

§ ADC_SSTSH0_TSH3_S

#define ADC_SSTSH0_TSH3_S   12

§ ADC_SSTSH0_TSH2_S

#define ADC_SSTSH0_TSH2_S   8

§ ADC_SSTSH0_TSH1_S

#define ADC_SSTSH0_TSH1_S   4

§ ADC_SSTSH0_TSH0_S

#define ADC_SSTSH0_TSH0_S   0

§ ADC_SSMUX1_MUX3_M

#define ADC_SSMUX1_MUX3_M   0x0000F000

§ ADC_SSMUX1_MUX2_M

#define ADC_SSMUX1_MUX2_M   0x00000F00

§ ADC_SSMUX1_MUX1_M

#define ADC_SSMUX1_MUX1_M   0x000000F0

§ ADC_SSMUX1_MUX0_M

#define ADC_SSMUX1_MUX0_M   0x0000000F

§ ADC_SSMUX1_MUX3_S

#define ADC_SSMUX1_MUX3_S   12

§ ADC_SSMUX1_MUX2_S

#define ADC_SSMUX1_MUX2_S   8

§ ADC_SSMUX1_MUX1_S

#define ADC_SSMUX1_MUX1_S   4

§ ADC_SSMUX1_MUX0_S

#define ADC_SSMUX1_MUX0_S   0

§ ADC_SSCTL1_TS3

#define ADC_SSCTL1_TS3   0x00008000

§ ADC_SSCTL1_IE3

#define ADC_SSCTL1_IE3   0x00004000

§ ADC_SSCTL1_END3

#define ADC_SSCTL1_END3   0x00002000

§ ADC_SSCTL1_D3

#define ADC_SSCTL1_D3   0x00001000

§ ADC_SSCTL1_TS2

#define ADC_SSCTL1_TS2   0x00000800

§ ADC_SSCTL1_IE2

#define ADC_SSCTL1_IE2   0x00000400

§ ADC_SSCTL1_END2

#define ADC_SSCTL1_END2   0x00000200

§ ADC_SSCTL1_D2

#define ADC_SSCTL1_D2   0x00000100

§ ADC_SSCTL1_TS1

#define ADC_SSCTL1_TS1   0x00000080

§ ADC_SSCTL1_IE1

#define ADC_SSCTL1_IE1   0x00000040

§ ADC_SSCTL1_END1

#define ADC_SSCTL1_END1   0x00000020

§ ADC_SSCTL1_D1

#define ADC_SSCTL1_D1   0x00000010

§ ADC_SSCTL1_TS0

#define ADC_SSCTL1_TS0   0x00000008

§ ADC_SSCTL1_IE0

#define ADC_SSCTL1_IE0   0x00000004

§ ADC_SSCTL1_END0

#define ADC_SSCTL1_END0   0x00000002

§ ADC_SSCTL1_D0

#define ADC_SSCTL1_D0   0x00000001

§ ADC_SSFIFO1_DATA_M

#define ADC_SSFIFO1_DATA_M   0x00000FFF

§ ADC_SSFIFO1_DATA_S

#define ADC_SSFIFO1_DATA_S   0

§ ADC_SSFSTAT1_FULL

#define ADC_SSFSTAT1_FULL   0x00001000

§ ADC_SSFSTAT1_EMPTY

#define ADC_SSFSTAT1_EMPTY   0x00000100

§ ADC_SSFSTAT1_HPTR_M

#define ADC_SSFSTAT1_HPTR_M   0x000000F0

§ ADC_SSFSTAT1_TPTR_M

#define ADC_SSFSTAT1_TPTR_M   0x0000000F

§ ADC_SSFSTAT1_HPTR_S

#define ADC_SSFSTAT1_HPTR_S   4

§ ADC_SSFSTAT1_TPTR_S

#define ADC_SSFSTAT1_TPTR_S   0

§ ADC_SSOP1_S3DCOP

#define ADC_SSOP1_S3DCOP   0x00001000

§ ADC_SSOP1_S2DCOP

#define ADC_SSOP1_S2DCOP   0x00000100

§ ADC_SSOP1_S1DCOP

#define ADC_SSOP1_S1DCOP   0x00000010

§ ADC_SSOP1_S0DCOP

#define ADC_SSOP1_S0DCOP   0x00000001

§ ADC_SSDC1_S3DCSEL_M

#define ADC_SSDC1_S3DCSEL_M   0x0000F000

§ ADC_SSDC1_S2DCSEL_M

#define ADC_SSDC1_S2DCSEL_M   0x00000F00

§ ADC_SSDC1_S1DCSEL_M

#define ADC_SSDC1_S1DCSEL_M   0x000000F0

§ ADC_SSDC1_S0DCSEL_M

#define ADC_SSDC1_S0DCSEL_M   0x0000000F

§ ADC_SSDC1_S2DCSEL_S

#define ADC_SSDC1_S2DCSEL_S   8

§ ADC_SSDC1_S1DCSEL_S

#define ADC_SSDC1_S1DCSEL_S   4

§ ADC_SSDC1_S0DCSEL_S

#define ADC_SSDC1_S0DCSEL_S   0

§ ADC_SSEMUX1_EMUX3

#define ADC_SSEMUX1_EMUX3   0x00001000

§ ADC_SSEMUX1_EMUX2

#define ADC_SSEMUX1_EMUX2   0x00000100

§ ADC_SSEMUX1_EMUX1

#define ADC_SSEMUX1_EMUX1   0x00000010

§ ADC_SSEMUX1_EMUX0

#define ADC_SSEMUX1_EMUX0   0x00000001

§ ADC_SSTSH1_TSH3_M

#define ADC_SSTSH1_TSH3_M   0x0000F000

§ ADC_SSTSH1_TSH2_M

#define ADC_SSTSH1_TSH2_M   0x00000F00

§ ADC_SSTSH1_TSH1_M

#define ADC_SSTSH1_TSH1_M   0x000000F0

§ ADC_SSTSH1_TSH0_M

#define ADC_SSTSH1_TSH0_M   0x0000000F

§ ADC_SSTSH1_TSH3_S

#define ADC_SSTSH1_TSH3_S   12

§ ADC_SSTSH1_TSH2_S

#define ADC_SSTSH1_TSH2_S   8

§ ADC_SSTSH1_TSH1_S

#define ADC_SSTSH1_TSH1_S   4

§ ADC_SSTSH1_TSH0_S

#define ADC_SSTSH1_TSH0_S   0

§ ADC_SSMUX2_MUX3_M

#define ADC_SSMUX2_MUX3_M   0x0000F000

§ ADC_SSMUX2_MUX2_M

#define ADC_SSMUX2_MUX2_M   0x00000F00

§ ADC_SSMUX2_MUX1_M

#define ADC_SSMUX2_MUX1_M   0x000000F0

§ ADC_SSMUX2_MUX0_M

#define ADC_SSMUX2_MUX0_M   0x0000000F

§ ADC_SSMUX2_MUX3_S

#define ADC_SSMUX2_MUX3_S   12

§ ADC_SSMUX2_MUX2_S

#define ADC_SSMUX2_MUX2_S   8

§ ADC_SSMUX2_MUX1_S

#define ADC_SSMUX2_MUX1_S   4

§ ADC_SSMUX2_MUX0_S

#define ADC_SSMUX2_MUX0_S   0

§ ADC_SSCTL2_TS3

#define ADC_SSCTL2_TS3   0x00008000

§ ADC_SSCTL2_IE3

#define ADC_SSCTL2_IE3   0x00004000

§ ADC_SSCTL2_END3

#define ADC_SSCTL2_END3   0x00002000

§ ADC_SSCTL2_D3

#define ADC_SSCTL2_D3   0x00001000

§ ADC_SSCTL2_TS2

#define ADC_SSCTL2_TS2   0x00000800

§ ADC_SSCTL2_IE2

#define ADC_SSCTL2_IE2   0x00000400

§ ADC_SSCTL2_END2

#define ADC_SSCTL2_END2   0x00000200

§ ADC_SSCTL2_D2

#define ADC_SSCTL2_D2   0x00000100

§ ADC_SSCTL2_TS1

#define ADC_SSCTL2_TS1   0x00000080

§ ADC_SSCTL2_IE1

#define ADC_SSCTL2_IE1   0x00000040

§ ADC_SSCTL2_END1

#define ADC_SSCTL2_END1   0x00000020

§ ADC_SSCTL2_D1

#define ADC_SSCTL2_D1   0x00000010

§ ADC_SSCTL2_TS0

#define ADC_SSCTL2_TS0   0x00000008

§ ADC_SSCTL2_IE0

#define ADC_SSCTL2_IE0   0x00000004

§ ADC_SSCTL2_END0

#define ADC_SSCTL2_END0   0x00000002

§ ADC_SSCTL2_D0

#define ADC_SSCTL2_D0   0x00000001

§ ADC_SSFIFO2_DATA_M

#define ADC_SSFIFO2_DATA_M   0x00000FFF

§ ADC_SSFIFO2_DATA_S

#define ADC_SSFIFO2_DATA_S   0

§ ADC_SSFSTAT2_FULL

#define ADC_SSFSTAT2_FULL   0x00001000

§ ADC_SSFSTAT2_EMPTY

#define ADC_SSFSTAT2_EMPTY   0x00000100

§ ADC_SSFSTAT2_HPTR_M

#define ADC_SSFSTAT2_HPTR_M   0x000000F0

§ ADC_SSFSTAT2_TPTR_M

#define ADC_SSFSTAT2_TPTR_M   0x0000000F

§ ADC_SSFSTAT2_HPTR_S

#define ADC_SSFSTAT2_HPTR_S   4

§ ADC_SSFSTAT2_TPTR_S

#define ADC_SSFSTAT2_TPTR_S   0

§ ADC_SSOP2_S3DCOP

#define ADC_SSOP2_S3DCOP   0x00001000

§ ADC_SSOP2_S2DCOP

#define ADC_SSOP2_S2DCOP   0x00000100

§ ADC_SSOP2_S1DCOP

#define ADC_SSOP2_S1DCOP   0x00000010

§ ADC_SSOP2_S0DCOP

#define ADC_SSOP2_S0DCOP   0x00000001

§ ADC_SSDC2_S3DCSEL_M

#define ADC_SSDC2_S3DCSEL_M   0x0000F000

§ ADC_SSDC2_S2DCSEL_M

#define ADC_SSDC2_S2DCSEL_M   0x00000F00

§ ADC_SSDC2_S1DCSEL_M

#define ADC_SSDC2_S1DCSEL_M   0x000000F0

§ ADC_SSDC2_S0DCSEL_M

#define ADC_SSDC2_S0DCSEL_M   0x0000000F

§ ADC_SSDC2_S2DCSEL_S

#define ADC_SSDC2_S2DCSEL_S   8

§ ADC_SSDC2_S1DCSEL_S

#define ADC_SSDC2_S1DCSEL_S   4

§ ADC_SSDC2_S0DCSEL_S

#define ADC_SSDC2_S0DCSEL_S   0

§ ADC_SSEMUX2_EMUX3

#define ADC_SSEMUX2_EMUX3   0x00001000

§ ADC_SSEMUX2_EMUX2

#define ADC_SSEMUX2_EMUX2   0x00000100

§ ADC_SSEMUX2_EMUX1

#define ADC_SSEMUX2_EMUX1   0x00000010

§ ADC_SSEMUX2_EMUX0

#define ADC_SSEMUX2_EMUX0   0x00000001

§ ADC_SSTSH2_TSH3_M

#define ADC_SSTSH2_TSH3_M   0x0000F000

§ ADC_SSTSH2_TSH2_M

#define ADC_SSTSH2_TSH2_M   0x00000F00

§ ADC_SSTSH2_TSH1_M

#define ADC_SSTSH2_TSH1_M   0x000000F0

§ ADC_SSTSH2_TSH0_M

#define ADC_SSTSH2_TSH0_M   0x0000000F

§ ADC_SSTSH2_TSH3_S

#define ADC_SSTSH2_TSH3_S   12

§ ADC_SSTSH2_TSH2_S

#define ADC_SSTSH2_TSH2_S   8

§ ADC_SSTSH2_TSH1_S

#define ADC_SSTSH2_TSH1_S   4

§ ADC_SSTSH2_TSH0_S

#define ADC_SSTSH2_TSH0_S   0

§ ADC_SSMUX3_MUX0_M

#define ADC_SSMUX3_MUX0_M   0x0000000F

§ ADC_SSMUX3_MUX0_S

#define ADC_SSMUX3_MUX0_S   0

§ ADC_SSCTL3_TS0

#define ADC_SSCTL3_TS0   0x00000008

§ ADC_SSCTL3_IE0

#define ADC_SSCTL3_IE0   0x00000004

§ ADC_SSCTL3_END0

#define ADC_SSCTL3_END0   0x00000002

§ ADC_SSCTL3_D0

#define ADC_SSCTL3_D0   0x00000001

§ ADC_SSFIFO3_DATA_M

#define ADC_SSFIFO3_DATA_M   0x00000FFF

§ ADC_SSFIFO3_DATA_S

#define ADC_SSFIFO3_DATA_S   0

§ ADC_SSFSTAT3_FULL

#define ADC_SSFSTAT3_FULL   0x00001000

§ ADC_SSFSTAT3_EMPTY

#define ADC_SSFSTAT3_EMPTY   0x00000100

§ ADC_SSFSTAT3_HPTR_M

#define ADC_SSFSTAT3_HPTR_M   0x000000F0

§ ADC_SSFSTAT3_TPTR_M

#define ADC_SSFSTAT3_TPTR_M   0x0000000F

§ ADC_SSFSTAT3_HPTR_S

#define ADC_SSFSTAT3_HPTR_S   4

§ ADC_SSFSTAT3_TPTR_S

#define ADC_SSFSTAT3_TPTR_S   0

§ ADC_SSOP3_S0DCOP

#define ADC_SSOP3_S0DCOP   0x00000001

§ ADC_SSDC3_S0DCSEL_M

#define ADC_SSDC3_S0DCSEL_M   0x0000000F

§ ADC_SSEMUX3_EMUX0

#define ADC_SSEMUX3_EMUX0   0x00000001

§ ADC_SSTSH3_TSH0_M

#define ADC_SSTSH3_TSH0_M   0x0000000F

§ ADC_SSTSH3_TSH0_S

#define ADC_SSTSH3_TSH0_S   0

§ ADC_DCRIC_DCTRIG7

#define ADC_DCRIC_DCTRIG7   0x00800000

§ ADC_DCRIC_DCTRIG6

#define ADC_DCRIC_DCTRIG6   0x00400000

§ ADC_DCRIC_DCTRIG5

#define ADC_DCRIC_DCTRIG5   0x00200000

§ ADC_DCRIC_DCTRIG4

#define ADC_DCRIC_DCTRIG4   0x00100000

§ ADC_DCRIC_DCTRIG3

#define ADC_DCRIC_DCTRIG3   0x00080000

§ ADC_DCRIC_DCTRIG2

#define ADC_DCRIC_DCTRIG2   0x00040000

§ ADC_DCRIC_DCTRIG1

#define ADC_DCRIC_DCTRIG1   0x00020000

§ ADC_DCRIC_DCTRIG0

#define ADC_DCRIC_DCTRIG0   0x00010000

§ ADC_DCRIC_DCINT7

#define ADC_DCRIC_DCINT7   0x00000080

§ ADC_DCRIC_DCINT6

#define ADC_DCRIC_DCINT6   0x00000040

§ ADC_DCRIC_DCINT5

#define ADC_DCRIC_DCINT5   0x00000020

§ ADC_DCRIC_DCINT4

#define ADC_DCRIC_DCINT4   0x00000010

§ ADC_DCRIC_DCINT3

#define ADC_DCRIC_DCINT3   0x00000008

§ ADC_DCRIC_DCINT2

#define ADC_DCRIC_DCINT2   0x00000004

§ ADC_DCRIC_DCINT1

#define ADC_DCRIC_DCINT1   0x00000002

§ ADC_DCRIC_DCINT0

#define ADC_DCRIC_DCINT0   0x00000001

§ ADC_DCCTL0_CTE

#define ADC_DCCTL0_CTE   0x00001000

§ ADC_DCCTL0_CTC_M

#define ADC_DCCTL0_CTC_M   0x00000C00

§ ADC_DCCTL0_CTC_LOW

#define ADC_DCCTL0_CTC_LOW   0x00000000

§ ADC_DCCTL0_CTC_MID

#define ADC_DCCTL0_CTC_MID   0x00000400

§ ADC_DCCTL0_CTC_HIGH

#define ADC_DCCTL0_CTC_HIGH   0x00000C00

§ ADC_DCCTL0_CTM_M

#define ADC_DCCTL0_CTM_M   0x00000300

§ ADC_DCCTL0_CTM_ALWAYS

#define ADC_DCCTL0_CTM_ALWAYS   0x00000000

§ ADC_DCCTL0_CTM_ONCE

#define ADC_DCCTL0_CTM_ONCE   0x00000100

§ ADC_DCCTL0_CTM_HALWAYS

#define ADC_DCCTL0_CTM_HALWAYS   0x00000200

§ ADC_DCCTL0_CTM_HONCE

#define ADC_DCCTL0_CTM_HONCE   0x00000300

§ ADC_DCCTL0_CIE

#define ADC_DCCTL0_CIE   0x00000010

§ ADC_DCCTL0_CIC_M

#define ADC_DCCTL0_CIC_M   0x0000000C

§ ADC_DCCTL0_CIC_LOW

#define ADC_DCCTL0_CIC_LOW   0x00000000

§ ADC_DCCTL0_CIC_MID

#define ADC_DCCTL0_CIC_MID   0x00000004

§ ADC_DCCTL0_CIC_HIGH

#define ADC_DCCTL0_CIC_HIGH   0x0000000C

§ ADC_DCCTL0_CIM_M

#define ADC_DCCTL0_CIM_M   0x00000003

§ ADC_DCCTL0_CIM_ALWAYS

#define ADC_DCCTL0_CIM_ALWAYS   0x00000000

§ ADC_DCCTL0_CIM_ONCE

#define ADC_DCCTL0_CIM_ONCE   0x00000001

§ ADC_DCCTL0_CIM_HALWAYS

#define ADC_DCCTL0_CIM_HALWAYS   0x00000002

§ ADC_DCCTL0_CIM_HONCE

#define ADC_DCCTL0_CIM_HONCE   0x00000003

§ ADC_DCCTL1_CTE

#define ADC_DCCTL1_CTE   0x00001000

§ ADC_DCCTL1_CTC_M

#define ADC_DCCTL1_CTC_M   0x00000C00

§ ADC_DCCTL1_CTC_LOW

#define ADC_DCCTL1_CTC_LOW   0x00000000

§ ADC_DCCTL1_CTC_MID

#define ADC_DCCTL1_CTC_MID   0x00000400

§ ADC_DCCTL1_CTC_HIGH

#define ADC_DCCTL1_CTC_HIGH   0x00000C00

§ ADC_DCCTL1_CTM_M

#define ADC_DCCTL1_CTM_M   0x00000300

§ ADC_DCCTL1_CTM_ALWAYS

#define ADC_DCCTL1_CTM_ALWAYS   0x00000000

§ ADC_DCCTL1_CTM_ONCE

#define ADC_DCCTL1_CTM_ONCE   0x00000100

§ ADC_DCCTL1_CTM_HALWAYS

#define ADC_DCCTL1_CTM_HALWAYS   0x00000200

§ ADC_DCCTL1_CTM_HONCE

#define ADC_DCCTL1_CTM_HONCE   0x00000300

§ ADC_DCCTL1_CIE

#define ADC_DCCTL1_CIE   0x00000010

§ ADC_DCCTL1_CIC_M

#define ADC_DCCTL1_CIC_M   0x0000000C

§ ADC_DCCTL1_CIC_LOW

#define ADC_DCCTL1_CIC_LOW   0x00000000

§ ADC_DCCTL1_CIC_MID

#define ADC_DCCTL1_CIC_MID   0x00000004

§ ADC_DCCTL1_CIC_HIGH

#define ADC_DCCTL1_CIC_HIGH   0x0000000C

§ ADC_DCCTL1_CIM_M

#define ADC_DCCTL1_CIM_M   0x00000003

§ ADC_DCCTL1_CIM_ALWAYS

#define ADC_DCCTL1_CIM_ALWAYS   0x00000000

§ ADC_DCCTL1_CIM_ONCE

#define ADC_DCCTL1_CIM_ONCE   0x00000001

§ ADC_DCCTL1_CIM_HALWAYS

#define ADC_DCCTL1_CIM_HALWAYS   0x00000002

§ ADC_DCCTL1_CIM_HONCE

#define ADC_DCCTL1_CIM_HONCE   0x00000003

§ ADC_DCCTL2_CTE

#define ADC_DCCTL2_CTE   0x00001000

§ ADC_DCCTL2_CTC_M

#define ADC_DCCTL2_CTC_M   0x00000C00

§ ADC_DCCTL2_CTC_LOW

#define ADC_DCCTL2_CTC_LOW   0x00000000

§ ADC_DCCTL2_CTC_MID

#define ADC_DCCTL2_CTC_MID   0x00000400

§ ADC_DCCTL2_CTC_HIGH

#define ADC_DCCTL2_CTC_HIGH   0x00000C00

§ ADC_DCCTL2_CTM_M

#define ADC_DCCTL2_CTM_M   0x00000300

§ ADC_DCCTL2_CTM_ALWAYS

#define ADC_DCCTL2_CTM_ALWAYS   0x00000000

§ ADC_DCCTL2_CTM_ONCE

#define ADC_DCCTL2_CTM_ONCE   0x00000100

§ ADC_DCCTL2_CTM_HALWAYS

#define ADC_DCCTL2_CTM_HALWAYS   0x00000200

§ ADC_DCCTL2_CTM_HONCE

#define ADC_DCCTL2_CTM_HONCE   0x00000300

§ ADC_DCCTL2_CIE

#define ADC_DCCTL2_CIE   0x00000010

§ ADC_DCCTL2_CIC_M

#define ADC_DCCTL2_CIC_M   0x0000000C

§ ADC_DCCTL2_CIC_LOW

#define ADC_DCCTL2_CIC_LOW   0x00000000

§ ADC_DCCTL2_CIC_MID

#define ADC_DCCTL2_CIC_MID   0x00000004

§ ADC_DCCTL2_CIC_HIGH

#define ADC_DCCTL2_CIC_HIGH   0x0000000C

§ ADC_DCCTL2_CIM_M

#define ADC_DCCTL2_CIM_M   0x00000003

§ ADC_DCCTL2_CIM_ALWAYS

#define ADC_DCCTL2_CIM_ALWAYS   0x00000000

§ ADC_DCCTL2_CIM_ONCE

#define ADC_DCCTL2_CIM_ONCE   0x00000001

§ ADC_DCCTL2_CIM_HALWAYS

#define ADC_DCCTL2_CIM_HALWAYS   0x00000002

§ ADC_DCCTL2_CIM_HONCE

#define ADC_DCCTL2_CIM_HONCE   0x00000003

§ ADC_DCCTL3_CTE

#define ADC_DCCTL3_CTE   0x00001000

§ ADC_DCCTL3_CTC_M

#define ADC_DCCTL3_CTC_M   0x00000C00

§ ADC_DCCTL3_CTC_LOW

#define ADC_DCCTL3_CTC_LOW   0x00000000

§ ADC_DCCTL3_CTC_MID

#define ADC_DCCTL3_CTC_MID   0x00000400

§ ADC_DCCTL3_CTC_HIGH

#define ADC_DCCTL3_CTC_HIGH   0x00000C00

§ ADC_DCCTL3_CTM_M

#define ADC_DCCTL3_CTM_M   0x00000300

§ ADC_DCCTL3_CTM_ALWAYS

#define ADC_DCCTL3_CTM_ALWAYS   0x00000000

§ ADC_DCCTL3_CTM_ONCE

#define ADC_DCCTL3_CTM_ONCE   0x00000100

§ ADC_DCCTL3_CTM_HALWAYS

#define ADC_DCCTL3_CTM_HALWAYS   0x00000200

§ ADC_DCCTL3_CTM_HONCE

#define ADC_DCCTL3_CTM_HONCE   0x00000300

§ ADC_DCCTL3_CIE

#define ADC_DCCTL3_CIE   0x00000010

§ ADC_DCCTL3_CIC_M

#define ADC_DCCTL3_CIC_M   0x0000000C

§ ADC_DCCTL3_CIC_LOW

#define ADC_DCCTL3_CIC_LOW   0x00000000

§ ADC_DCCTL3_CIC_MID

#define ADC_DCCTL3_CIC_MID   0x00000004

§ ADC_DCCTL3_CIC_HIGH

#define ADC_DCCTL3_CIC_HIGH   0x0000000C

§ ADC_DCCTL3_CIM_M

#define ADC_DCCTL3_CIM_M   0x00000003

§ ADC_DCCTL3_CIM_ALWAYS

#define ADC_DCCTL3_CIM_ALWAYS   0x00000000

§ ADC_DCCTL3_CIM_ONCE

#define ADC_DCCTL3_CIM_ONCE   0x00000001

§ ADC_DCCTL3_CIM_HALWAYS

#define ADC_DCCTL3_CIM_HALWAYS   0x00000002

§ ADC_DCCTL3_CIM_HONCE

#define ADC_DCCTL3_CIM_HONCE   0x00000003

§ ADC_DCCTL4_CTE

#define ADC_DCCTL4_CTE   0x00001000

§ ADC_DCCTL4_CTC_M

#define ADC_DCCTL4_CTC_M   0x00000C00

§ ADC_DCCTL4_CTC_LOW

#define ADC_DCCTL4_CTC_LOW   0x00000000

§ ADC_DCCTL4_CTC_MID

#define ADC_DCCTL4_CTC_MID   0x00000400

§ ADC_DCCTL4_CTC_HIGH

#define ADC_DCCTL4_CTC_HIGH   0x00000C00

§ ADC_DCCTL4_CTM_M

#define ADC_DCCTL4_CTM_M   0x00000300

§ ADC_DCCTL4_CTM_ALWAYS

#define ADC_DCCTL4_CTM_ALWAYS   0x00000000

§ ADC_DCCTL4_CTM_ONCE

#define ADC_DCCTL4_CTM_ONCE   0x00000100

§ ADC_DCCTL4_CTM_HALWAYS

#define ADC_DCCTL4_CTM_HALWAYS   0x00000200

§ ADC_DCCTL4_CTM_HONCE

#define ADC_DCCTL4_CTM_HONCE   0x00000300

§ ADC_DCCTL4_CIE

#define ADC_DCCTL4_CIE   0x00000010

§ ADC_DCCTL4_CIC_M

#define ADC_DCCTL4_CIC_M   0x0000000C

§ ADC_DCCTL4_CIC_LOW

#define ADC_DCCTL4_CIC_LOW   0x00000000

§ ADC_DCCTL4_CIC_MID

#define ADC_DCCTL4_CIC_MID   0x00000004

§ ADC_DCCTL4_CIC_HIGH

#define ADC_DCCTL4_CIC_HIGH   0x0000000C

§ ADC_DCCTL4_CIM_M

#define ADC_DCCTL4_CIM_M   0x00000003

§ ADC_DCCTL4_CIM_ALWAYS

#define ADC_DCCTL4_CIM_ALWAYS   0x00000000

§ ADC_DCCTL4_CIM_ONCE

#define ADC_DCCTL4_CIM_ONCE   0x00000001

§ ADC_DCCTL4_CIM_HALWAYS

#define ADC_DCCTL4_CIM_HALWAYS   0x00000002

§ ADC_DCCTL4_CIM_HONCE

#define ADC_DCCTL4_CIM_HONCE   0x00000003

§ ADC_DCCTL5_CTE

#define ADC_DCCTL5_CTE   0x00001000

§ ADC_DCCTL5_CTC_M

#define ADC_DCCTL5_CTC_M   0x00000C00

§ ADC_DCCTL5_CTC_LOW

#define ADC_DCCTL5_CTC_LOW   0x00000000

§ ADC_DCCTL5_CTC_MID

#define ADC_DCCTL5_CTC_MID   0x00000400

§ ADC_DCCTL5_CTC_HIGH

#define ADC_DCCTL5_CTC_HIGH   0x00000C00

§ ADC_DCCTL5_CTM_M

#define ADC_DCCTL5_CTM_M   0x00000300

§ ADC_DCCTL5_CTM_ALWAYS

#define ADC_DCCTL5_CTM_ALWAYS   0x00000000

§ ADC_DCCTL5_CTM_ONCE

#define ADC_DCCTL5_CTM_ONCE   0x00000100

§ ADC_DCCTL5_CTM_HALWAYS

#define ADC_DCCTL5_CTM_HALWAYS   0x00000200

§ ADC_DCCTL5_CTM_HONCE

#define ADC_DCCTL5_CTM_HONCE   0x00000300

§ ADC_DCCTL5_CIE

#define ADC_DCCTL5_CIE   0x00000010

§ ADC_DCCTL5_CIC_M

#define ADC_DCCTL5_CIC_M   0x0000000C

§ ADC_DCCTL5_CIC_LOW

#define ADC_DCCTL5_CIC_LOW   0x00000000

§ ADC_DCCTL5_CIC_MID

#define ADC_DCCTL5_CIC_MID   0x00000004

§ ADC_DCCTL5_CIC_HIGH

#define ADC_DCCTL5_CIC_HIGH   0x0000000C

§ ADC_DCCTL5_CIM_M

#define ADC_DCCTL5_CIM_M   0x00000003

§ ADC_DCCTL5_CIM_ALWAYS

#define ADC_DCCTL5_CIM_ALWAYS   0x00000000

§ ADC_DCCTL5_CIM_ONCE

#define ADC_DCCTL5_CIM_ONCE   0x00000001

§ ADC_DCCTL5_CIM_HALWAYS

#define ADC_DCCTL5_CIM_HALWAYS   0x00000002

§ ADC_DCCTL5_CIM_HONCE

#define ADC_DCCTL5_CIM_HONCE   0x00000003

§ ADC_DCCTL6_CTE

#define ADC_DCCTL6_CTE   0x00001000

§ ADC_DCCTL6_CTC_M

#define ADC_DCCTL6_CTC_M   0x00000C00

§ ADC_DCCTL6_CTC_LOW

#define ADC_DCCTL6_CTC_LOW   0x00000000

§ ADC_DCCTL6_CTC_MID

#define ADC_DCCTL6_CTC_MID   0x00000400

§ ADC_DCCTL6_CTC_HIGH

#define ADC_DCCTL6_CTC_HIGH   0x00000C00

§ ADC_DCCTL6_CTM_M

#define ADC_DCCTL6_CTM_M   0x00000300

§ ADC_DCCTL6_CTM_ALWAYS

#define ADC_DCCTL6_CTM_ALWAYS   0x00000000

§ ADC_DCCTL6_CTM_ONCE

#define ADC_DCCTL6_CTM_ONCE   0x00000100

§ ADC_DCCTL6_CTM_HALWAYS

#define ADC_DCCTL6_CTM_HALWAYS   0x00000200

§ ADC_DCCTL6_CTM_HONCE

#define ADC_DCCTL6_CTM_HONCE   0x00000300

§ ADC_DCCTL6_CIE

#define ADC_DCCTL6_CIE   0x00000010

§ ADC_DCCTL6_CIC_M

#define ADC_DCCTL6_CIC_M   0x0000000C

§ ADC_DCCTL6_CIC_LOW

#define ADC_DCCTL6_CIC_LOW   0x00000000

§ ADC_DCCTL6_CIC_MID

#define ADC_DCCTL6_CIC_MID   0x00000004

§ ADC_DCCTL6_CIC_HIGH

#define ADC_DCCTL6_CIC_HIGH   0x0000000C

§ ADC_DCCTL6_CIM_M

#define ADC_DCCTL6_CIM_M   0x00000003

§ ADC_DCCTL6_CIM_ALWAYS

#define ADC_DCCTL6_CIM_ALWAYS   0x00000000

§ ADC_DCCTL6_CIM_ONCE

#define ADC_DCCTL6_CIM_ONCE   0x00000001

§ ADC_DCCTL6_CIM_HALWAYS

#define ADC_DCCTL6_CIM_HALWAYS   0x00000002

§ ADC_DCCTL6_CIM_HONCE

#define ADC_DCCTL6_CIM_HONCE   0x00000003

§ ADC_DCCTL7_CTE

#define ADC_DCCTL7_CTE   0x00001000

§ ADC_DCCTL7_CTC_M

#define ADC_DCCTL7_CTC_M   0x00000C00

§ ADC_DCCTL7_CTC_LOW

#define ADC_DCCTL7_CTC_LOW   0x00000000

§ ADC_DCCTL7_CTC_MID

#define ADC_DCCTL7_CTC_MID   0x00000400

§ ADC_DCCTL7_CTC_HIGH

#define ADC_DCCTL7_CTC_HIGH   0x00000C00

§ ADC_DCCTL7_CTM_M

#define ADC_DCCTL7_CTM_M   0x00000300

§ ADC_DCCTL7_CTM_ALWAYS

#define ADC_DCCTL7_CTM_ALWAYS   0x00000000

§ ADC_DCCTL7_CTM_ONCE

#define ADC_DCCTL7_CTM_ONCE   0x00000100

§ ADC_DCCTL7_CTM_HALWAYS

#define ADC_DCCTL7_CTM_HALWAYS   0x00000200

§ ADC_DCCTL7_CTM_HONCE

#define ADC_DCCTL7_CTM_HONCE   0x00000300

§ ADC_DCCTL7_CIE

#define ADC_DCCTL7_CIE   0x00000010

§ ADC_DCCTL7_CIC_M

#define ADC_DCCTL7_CIC_M   0x0000000C

§ ADC_DCCTL7_CIC_LOW

#define ADC_DCCTL7_CIC_LOW   0x00000000

§ ADC_DCCTL7_CIC_MID

#define ADC_DCCTL7_CIC_MID   0x00000004

§ ADC_DCCTL7_CIC_HIGH

#define ADC_DCCTL7_CIC_HIGH   0x0000000C

§ ADC_DCCTL7_CIM_M

#define ADC_DCCTL7_CIM_M   0x00000003

§ ADC_DCCTL7_CIM_ALWAYS

#define ADC_DCCTL7_CIM_ALWAYS   0x00000000

§ ADC_DCCTL7_CIM_ONCE

#define ADC_DCCTL7_CIM_ONCE   0x00000001

§ ADC_DCCTL7_CIM_HALWAYS

#define ADC_DCCTL7_CIM_HALWAYS   0x00000002

§ ADC_DCCTL7_CIM_HONCE

#define ADC_DCCTL7_CIM_HONCE   0x00000003

§ ADC_DCCMP0_COMP1_M

#define ADC_DCCMP0_COMP1_M   0x0FFF0000

§ ADC_DCCMP0_COMP0_M

#define ADC_DCCMP0_COMP0_M   0x00000FFF

§ ADC_DCCMP0_COMP1_S

#define ADC_DCCMP0_COMP1_S   16

§ ADC_DCCMP0_COMP0_S

#define ADC_DCCMP0_COMP0_S   0

§ ADC_DCCMP1_COMP1_M

#define ADC_DCCMP1_COMP1_M   0x0FFF0000

§ ADC_DCCMP1_COMP0_M

#define ADC_DCCMP1_COMP0_M   0x00000FFF

§ ADC_DCCMP1_COMP1_S

#define ADC_DCCMP1_COMP1_S   16

§ ADC_DCCMP1_COMP0_S

#define ADC_DCCMP1_COMP0_S   0

§ ADC_DCCMP2_COMP1_M

#define ADC_DCCMP2_COMP1_M   0x0FFF0000

§ ADC_DCCMP2_COMP0_M

#define ADC_DCCMP2_COMP0_M   0x00000FFF

§ ADC_DCCMP2_COMP1_S

#define ADC_DCCMP2_COMP1_S   16

§ ADC_DCCMP2_COMP0_S

#define ADC_DCCMP2_COMP0_S   0

§ ADC_DCCMP3_COMP1_M

#define ADC_DCCMP3_COMP1_M   0x0FFF0000

§ ADC_DCCMP3_COMP0_M

#define ADC_DCCMP3_COMP0_M   0x00000FFF

§ ADC_DCCMP3_COMP1_S

#define ADC_DCCMP3_COMP1_S   16

§ ADC_DCCMP3_COMP0_S

#define ADC_DCCMP3_COMP0_S   0

§ ADC_DCCMP4_COMP1_M

#define ADC_DCCMP4_COMP1_M   0x0FFF0000

§ ADC_DCCMP4_COMP0_M

#define ADC_DCCMP4_COMP0_M   0x00000FFF

§ ADC_DCCMP4_COMP1_S

#define ADC_DCCMP4_COMP1_S   16

§ ADC_DCCMP4_COMP0_S

#define ADC_DCCMP4_COMP0_S   0

§ ADC_DCCMP5_COMP1_M

#define ADC_DCCMP5_COMP1_M   0x0FFF0000

§ ADC_DCCMP5_COMP0_M

#define ADC_DCCMP5_COMP0_M   0x00000FFF

§ ADC_DCCMP5_COMP1_S

#define ADC_DCCMP5_COMP1_S   16

§ ADC_DCCMP5_COMP0_S

#define ADC_DCCMP5_COMP0_S   0

§ ADC_DCCMP6_COMP1_M

#define ADC_DCCMP6_COMP1_M   0x0FFF0000

§ ADC_DCCMP6_COMP0_M

#define ADC_DCCMP6_COMP0_M   0x00000FFF

§ ADC_DCCMP6_COMP1_S

#define ADC_DCCMP6_COMP1_S   16

§ ADC_DCCMP6_COMP0_S

#define ADC_DCCMP6_COMP0_S   0

§ ADC_DCCMP7_COMP1_M

#define ADC_DCCMP7_COMP1_M   0x0FFF0000

§ ADC_DCCMP7_COMP0_M

#define ADC_DCCMP7_COMP0_M   0x00000FFF

§ ADC_DCCMP7_COMP1_S

#define ADC_DCCMP7_COMP1_S   16

§ ADC_DCCMP7_COMP0_S

#define ADC_DCCMP7_COMP0_S   0

§ ADC_PP_APSHT

#define ADC_PP_APSHT   0x01000000

§ ADC_PP_TS

#define ADC_PP_TS   0x00800000

§ ADC_PP_RSL_M

#define ADC_PP_RSL_M   0x007C0000

§ ADC_PP_TYPE_M

#define ADC_PP_TYPE_M   0x00030000

§ ADC_PP_TYPE_SAR

#define ADC_PP_TYPE_SAR   0x00000000

§ ADC_PP_DC_M

#define ADC_PP_DC_M   0x0000FC00

§ ADC_PP_CH_M

#define ADC_PP_CH_M   0x000003F0

§ ADC_PP_MCR_M

#define ADC_PP_MCR_M   0x0000000F

§ ADC_PP_MCR_FULL

#define ADC_PP_MCR_FULL   0x00000007

§ ADC_PP_MSR_M

#define ADC_PP_MSR_M   0x0000000F

§ ADC_PP_MSR_125K

#define ADC_PP_MSR_125K   0x00000001

§ ADC_PP_MSR_250K

#define ADC_PP_MSR_250K   0x00000003

§ ADC_PP_MSR_500K

#define ADC_PP_MSR_500K   0x00000005

§ ADC_PP_MSR_1M

#define ADC_PP_MSR_1M   0x00000007

§ ADC_PP_RSL_S

#define ADC_PP_RSL_S   18

§ ADC_PP_DC_S

#define ADC_PP_DC_S   10

§ ADC_PP_CH_S

#define ADC_PP_CH_S   4

§ ADC_PC_SR_M

#define ADC_PC_SR_M   0x0000000F

Referenced by ADCClockConfigGet(), and ADCClockConfigSet().

§ ADC_PC_SR_125K

#define ADC_PC_SR_125K   0x00000001

§ ADC_PC_SR_250K

#define ADC_PC_SR_250K   0x00000003

§ ADC_PC_SR_500K

#define ADC_PC_SR_500K   0x00000005

§ ADC_PC_SR_1M

#define ADC_PC_SR_1M   0x00000007

§ ADC_PC_MCR_M

#define ADC_PC_MCR_M   0x0000000F

§ ADC_PC_MCR_1_8

#define ADC_PC_MCR_1_8   0x00000001

§ ADC_PC_MCR_1_4

#define ADC_PC_MCR_1_4   0x00000003

§ ADC_PC_MCR_1_2

#define ADC_PC_MCR_1_2   0x00000005

§ ADC_PC_MCR_FULL

#define ADC_PC_MCR_FULL   0x00000007

§ ADC_CC_CLKDIV_M

#define ADC_CC_CLKDIV_M   0x000003F0

Referenced by ADCClockConfigGet(), and ADCClockConfigSet().

§ ADC_CC_CS_M

#define ADC_CC_CS_M   0x0000000F

Referenced by ADCClockConfigSet().

§ ADC_CC_CS_SYSPLL

#define ADC_CC_CS_SYSPLL   0x00000000

§ ADC_CC_CS_PIOSC

#define ADC_CC_CS_PIOSC   0x00000001

§ ADC_CC_CS_MOSC

#define ADC_CC_CS_MOSC   0x00000002

§ ADC_CC_CLKDIV_S

#define ADC_CC_CLKDIV_S   4

Referenced by ADCClockConfigGet(), and ADCClockConfigSet().

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