Macros
#define	FLASH_PP_MAINSS_S 16

#define	SysCtlXtalCfgToIndex(a) ((a & 0x7c0) >> 6)

#define	MAX_VCO_ENTRIES 2

#define	MAX_XTAL_ENTRIES 18

#define	PLL_M_TO_REG(mi, mf) ((uint32_t)mi \| (uint32_t)(mf << SYSCTL_PLLFREQ0_MFRAC_S))

#define	PLL_N_TO_REG(n) ((uint32_t)(n - 1) << SYSCTL_PLLFREQ1_N_S)

#define	PLL_Q_TO_REG(q) ((uint32_t)(q - 1) << SYSCTL_PLLFREQ1_Q_S)

#define	SYSCTL_PPBASE 0x400fe300

#define	SYSCTL_SRBASE 0x400fe500

#define	SYSCTL_RCGCBASE 0x400fe600

#define	SYSCTL_SCGCBASE 0x400fe700

#define	SYSCTL_DCGCBASE 0x400fe800

#define	SYSCTL_PCBASE 0x400fe900

#define	SYSCTL_PRBASE 0x400fea00

Functions
uint32_t	SysCtlSRAMSizeGet (void)

uint32_t	SysCtlFlashSizeGet (void)

uint32_t	SysCtlFlashSectorSizeGet (void)

bool	SysCtlPeripheralPresent (uint32_t ui32Peripheral)

bool	SysCtlPeripheralReady (uint32_t ui32Peripheral)

void	SysCtlPeripheralPowerOn (uint32_t ui32Peripheral)

void	SysCtlPeripheralPowerOff (uint32_t ui32Peripheral)

void	SysCtlPeripheralReset (uint32_t ui32Peripheral)

void	SysCtlPeripheralEnable (uint32_t ui32Peripheral)

void	SysCtlPeripheralDisable (uint32_t ui32Peripheral)

void	SysCtlPeripheralSleepEnable (uint32_t ui32Peripheral)

void	SysCtlPeripheralSleepDisable (uint32_t ui32Peripheral)

void	SysCtlPeripheralDeepSleepEnable (uint32_t ui32Peripheral)

void	SysCtlPeripheralDeepSleepDisable (uint32_t ui32Peripheral)

void	SysCtlPeripheralClockGating (bool bEnable)

void	SysCtlIntRegister (void(*pfnHandler)(void))

void	SysCtlIntUnregister (void)

void	SysCtlIntEnable (uint32_t ui32Ints)

void	SysCtlIntDisable (uint32_t ui32Ints)

void	SysCtlIntClear (uint32_t ui32Ints)

uint32_t	SysCtlIntStatus (bool bMasked)

void	SysCtlLDODeepSleepSet (uint32_t ui32Voltage)

uint32_t	SysCtlLDODeepSleepGet (void)

void	SysCtlSleepPowerSet (uint32_t ui32Config)

void	SysCtlDeepSleepPowerSet (uint32_t ui32Config)

void	SysCtlReset (void)

void	SysCtlSleep (void)

void	SysCtlDeepSleep (void)

uint32_t	SysCtlResetCauseGet (void)

void	SysCtlResetCauseClear (uint32_t ui32Causes)

void	SysCtlMOSCConfigSet (uint32_t ui32Config)

uint32_t	SysCtlPIOSCCalibrate (uint32_t ui32Type)

void	SysCtlResetBehaviorSet (uint32_t ui32Behavior)

uint32_t	SysCtlResetBehaviorGet (void)

uint32_t	SysCtlClockFreqSet (uint32_t ui32Config, uint32_t ui32SysClock)

void	SysCtlDeepSleepClockConfigSet (uint32_t ui32Div, uint32_t ui32Config)

void	SysCtlVoltageEventConfig (uint32_t ui32Config)

uint32_t	SysCtlVoltageEventStatus (void)

void	SysCtlVoltageEventClear (uint32_t ui32Status)

bool	SysCtlVCOGet (uint32_t ui32Crystal, uint32_t *pui32VCOFrequency)

uint32_t	SysCtlNMIStatus (void)

void	SysCtlNMIClear (uint32_t ui32Ints)

void	SysCtlClockOutConfig (uint32_t ui32Config, uint32_t ui32Div)

void	SysCtlAltClkConfig (uint32_t ui32Config)

Detailed Description

Introduction

System control determines the overall operation of the device. It controls the clocking of the device, the set of peripherals that are enabled, configuration of the device and its resets, and provides information about the device.

The members of the MSP432E4 family have a varying peripheral set and memory sizes. The device has a set of read-only registers that indicate the size of the memories, the peripherals that are present, and the pins that are present for peripherals that have a varying number of pins. This information can be used to write adaptive software that can run on more than one member of the MSP432E4 family.

The device can be clocked from several sources: an external oscillator, the main oscillator, the internal oscillator, the precision internal oscillator (PIOSC) or the PLL. The PLL can use any of the oscillators as its input. Because the internal oscillator has a very wide error range (+/- 50%), it cannot be used for applications that require specific timing; its real use is for detecting failures of the main oscillator and the PLL, and for applications that strictly respond to external events and do not use time-based peripherals (such as a UART). When using the PLL, the input clock frequency is constrained to specific frequencies that are specified in the device data sheet. When direct clocking with an external oscillator or the main oscillator, the frequency is constrained to between 0 Hz and 50 MHz (depending on the part). The frequency of the internal oscillator varies by device, with voltage, and with temperature. The internal oscillator provides no tuning or frequency measurement mechanism; its frequency is not adjustable.

Almost the entire device operates from a single clock. See the device data sheet for more information on how clocking for the various periphersals is configured.

Three modes of operation are supported by the MSP432E4 family: run mode, sleep mode, and deep-sleep mode. In run mode, the processor is actively executing code. In sleep mode, the clocking of the device is unchanged but the processor no longer executes code (and is no longer clocked). In deep-sleep mode, the clocking of the device may change (depending upon the run mode clock configuration) and the processor no longer executes code (and is no longer clocked). An interrupt returns the device to run mode from one of the sleep modes; the sleep modes are entered upon request from the code.

The device has an internal LDO for generating the core power supply. On some devices, the output voltage of the LDO can be adjusted between 2.25 V and 2.75 V. Depending upon the application, lower voltage may be advantageous for its power savings, or higher voltage may be advantageous for its improved performance. The default setting of 2.5 V is a good compromise between the two, and should not be changed without careful consideration and evaluation.

There are several system events that, when detected, cause system control to reset the device. These events are a power-on, the input voltage dropping too low, an external reset, a software reset request, waking from hibernation, a watchdog timeout, a hardware system service request, and a main oscillator failure. The properties of some of these events can be configured, and the reason for a reset can be determined from system control. Not all of these reset causes are on all devices, see the device data sheet for more details.

Each peripheral in the device can be individually enabled, disabled, or reset. Additionally, the set of peripherals that remain enabled during sleep mode and deep-sleep mode can be configured, allowing custom sleep and deep-sleep modes to be defined. Care must be taken with deep-sleep mode, though, because in this mode, the PLL is no longer used and the system is clocked by the input crystal. Peripherals that depend on a particular input clock rate (such as a UART) require special consideration in deep-sleep mode due to a clock rate change; these peripherals must either be reconfigured upon entry to and exit from deep-sleep mode, or simply not enabled in deep-sleep mode. Some devices provide the option to clock some peripherals with the PIOSC, even while in deep-sleep mode so the peripheral clocking does not have to be reconfigured upon entry and exit.

There are various system events that, when detected, cause system control to generate a processor interrupt. These events are the PLL achieving lock, the internal LDO current limit being exceeded, the internal oscillator failing, the main oscillator failing, the input voltage dropping too low, the internal LDO voltage dropping too low, and the PLL failing. Not all of these interrupts are available on all MSP432E4 devices, see the device data sheet for more details. Each of these interrupts can be individually enabled or disabled, and the sources must be cleared by the interrupt handler when they occur.

API Functions

The SysCtl API is broken up into eight groups of functions: those that provide device information, those that deal with device clocking, those that provide peripheral control, those that deal with the SysCtl interrupt, those that deal with the LDO, those that deal with sleep modes, those that deal with reset reasons, those that deal with the brown-out reset, and those that deal with clock verification timers.

Information about the device is provided by SysCtlSRAMSizeGet(), SysCtlFlashSizeGet(), and SysCtlPeripheralPresent().

Clocking of the device is configured with SysCtlClockSet() and SysCtlPWMClockSet(). Information about device clocking is provided by SysCtlClockGet() and SysCtlPWMClockGet().

The clocking of the main processor is configured by calling the SysCtlClockSet() or the SysCtlClockFreqSet() functions depending on part class. The SysCtlClockSet() is called for Blizzard-class devices and the SysCtlClockFreqSet() is called on all other devices. The SysCtlClockGet() function can only be called on Blizzard-class devices and all other devices must use the value returned from the SysCtlClockFreqSet() to determine the operating frequency of the device.

Peripheral enabling and reset are controlled with SysCtlPeripheralReset(), SysCtlPeripheralEnable(), SysCtlPeripheralDisable(), SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), SysCtlPeripheralDeepSleepDisable(), and SysCtlPeripheralClockGating().

The system control interrupt is managed with SysCtlIntRegister(), SysCtlIntUnregister(), SysCtlIntEnable(), SysCtlIntDisable(), SysCtlIntClear(), SysCtlIntStatus().

The LDO is controlled with SysCtlLDOSet() and SysCtlLDOConfigSet(). Its status is provided by SysCtlLDOGet().

The device is put into sleep modes with SysCtlSleep() and SysCtlDeepSleep().

The reset reason is managed with SysCtlResetCauseGet() and SysCtlResetCauseClear(). A software reset is performed with SysCtlReset().

The brown-out reset is configured with SysCtlBrownOutConfigSet().

The clock verification timers are managed with SysCtlIOSCVerificationSet(), SysCtlMOSCVerificationSet(), SysCtlPLLVerificationSet(), and SysCtlClkVerificationClear().

Programming Example

The following example shows how to use the SysCtl API to configure the device for normal operation on a TM4C123x device.

//
// Configure the device to run at 20 MHz from the PLL using a 4 MHz crystal
// as the input.
//
SysCtlClockSet(SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_XTAL_4MHZ |
               SYSCTL_OSC_MAIN);
//
// Enable the GPIO blocks and the SSI.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);
//
// Enable the GPIO blocks and the SSI in sleep mode.
//
SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_SSI);
//
// Enable peripheral clock gating.
//
SysCtlPeripheralClockGating(true);

Macro Definition Documentation

§ FLASH_PP_MAINSS_S

#define FLASH_PP_MAINSS_S 16

Referenced by SysCtlFlashSectorSizeGet().

§ SysCtlXtalCfgToIndex

#define SysCtlXtalCfgToIndex ( a ) ((a & 0x7c0) >> 6)

Referenced by SysCtlClockFreqSet(), and SysCtlVCOGet().

§ MAX_VCO_ENTRIES

#define MAX_VCO_ENTRIES 2

§ MAX_XTAL_ENTRIES

#define MAX_XTAL_ENTRIES 18

§ PLL_M_TO_REG

#define PLL_M_TO_REG	(	mi,
		mf
	)	((uint32_t)mi \| (uint32_t)(mf << SYSCTL_PLLFREQ0_MFRAC_S))

§ PLL_N_TO_REG

#define PLL_N_TO_REG ( n ) ((uint32_t)(n - 1) << SYSCTL_PLLFREQ1_N_S)

§ PLL_Q_TO_REG

#define PLL_Q_TO_REG ( q ) ((uint32_t)(q - 1) << SYSCTL_PLLFREQ1_Q_S)

§ SYSCTL_PPBASE

#define SYSCTL_PPBASE 0x400fe300

Referenced by SysCtlPeripheralPresent().

§ SYSCTL_SRBASE

#define SYSCTL_SRBASE 0x400fe500

Referenced by SysCtlPeripheralReset().

§ SYSCTL_RCGCBASE

#define SYSCTL_RCGCBASE 0x400fe600

Referenced by SysCtlPeripheralDisable(), and SysCtlPeripheralEnable().

§ SYSCTL_SCGCBASE

#define SYSCTL_SCGCBASE 0x400fe700

Referenced by SysCtlPeripheralSleepDisable(), and SysCtlPeripheralSleepEnable().

§ SYSCTL_DCGCBASE

#define SYSCTL_DCGCBASE 0x400fe800

Referenced by SysCtlPeripheralDeepSleepDisable(), and SysCtlPeripheralDeepSleepEnable().

§ SYSCTL_PCBASE

#define SYSCTL_PCBASE 0x400fe900

Referenced by SysCtlPeripheralPowerOff(), and SysCtlPeripheralPowerOn().

§ SYSCTL_PRBASE

#define SYSCTL_PRBASE 0x400fea00

Referenced by SysCtlPeripheralReady().

Function Documentation

§ SysCtlSRAMSizeGet()

uint32_t SysCtlSRAMSizeGet ( void )

Gets the size of the SRAM.

This function determines the size of the SRAM on the device.

Returns: The total number of bytes of SRAM.

References FLASH_SSIZE, and HWREG.

§ SysCtlFlashSizeGet()

uint32_t SysCtlFlashSizeGet ( void )

Gets the size of the flash.

This function determines the size of the flash on the device.

Returns: The total number of bytes of flash.

References FLASH_PP, FLASH_PP_SIZE_M, and HWREG.

§ SysCtlFlashSectorSizeGet()

uint32_t SysCtlFlashSectorSizeGet ( void )

Gets the size of a single eraseable sector of flash.

This function determines the flash sector size on the device. This size determines the erase granularity of the device flash.

Returns: The number of bytes in a single flash sector.

References FLASH_PP, FLASH_PP_MAINSS_M, FLASH_PP_MAINSS_S, and HWREG.

§ SysCtlPeripheralPresent()

bool SysCtlPeripheralPresent ( uint32_t ui32Peripheral )

Determines if a peripheral is present.

Parameters

ui32Peripheral is the peripheral in question.

This function determines if a particular peripheral is present in the device.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CCM0,SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_EEPROM0, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_EPI0, SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH_GPIOK, SYSCTL_PERIPH_GPIOL, SYSCTL_PERIPH_GPIOM, SYSCTL_PERIPH_GPION, SYSCTL_PERIPH_GPIOP, SYSCTL_PERIPH_GPIOQ, SYSCTL_PERIPH_GPIOR, SYSCTL_PERIPH_GPIOS, SYSCTL_PERIPH_GPIOT, SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH_I2C2, SYSCTL_PERIPH_I2C3, SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_I2C6, SYSCTL_PERIPH_I2C7, SYSCTL_PERIPH_I2C8, SYSCTL_PERIPH_I2C9, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_ONEWIRE0, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4, SYSCTL_PERIPH_TIMER5, SYSCTL_PERIPH_TIMER6, SYSCTL_PERIPH_TIMER7, SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART5, SYSCTL_PERIPH_UART6, SYSCTL_PERIPH_UART7, SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH_USB0, SYSCTL_PERIPH_WDOG0, or SYSCTL_PERIPH_WDOG1

Returns: Returns true if the specified peripheral is present and false if it is not.

References ASSERT, HWREGBITW, and SYSCTL_PPBASE.

§ SysCtlPeripheralReady()

bool SysCtlPeripheralReady ( uint32_t ui32Peripheral )

Determines if a peripheral is ready.

Parameters

ui32Peripheral is the peripheral in question.

This function determines if a particular peripheral is ready to be accessed. The peripheral may be in a non-ready state if it is not enabled, is being held in reset, or is in the process of becoming ready after being enabled or taken out of reset.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CCM0,SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_EEPROM0, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_EPI0, SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH_GPIOK, SYSCTL_PERIPH_GPIOL, SYSCTL_PERIPH_GPIOM, SYSCTL_PERIPH_GPION, SYSCTL_PERIPH_GPIOP, SYSCTL_PERIPH_GPIOQ, SYSCTL_PERIPH_GPIOR, SYSCTL_PERIPH_GPIOS, SYSCTL_PERIPH_GPIOT, SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH_I2C2, SYSCTL_PERIPH_I2C3, SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_I2C6, SYSCTL_PERIPH_I2C7, SYSCTL_PERIPH_I2C8, SYSCTL_PERIPH_I2C9, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_ONEWIRE0, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4, SYSCTL_PERIPH_TIMER5, SYSCTL_PERIPH_TIMER6, SYSCTL_PERIPH_TIMER7, SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART5, SYSCTL_PERIPH_UART6, SYSCTL_PERIPH_UART7, SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH_USB0, SYSCTL_PERIPH_WDOG0, or SYSCTL_PERIPH_WDOG1

Returns: Returns true if the specified peripheral is ready and false if it is not.

References ASSERT, HWREGBITW, and SYSCTL_PRBASE.

Referenced by EMACPHYConfigSet().

§ SysCtlPeripheralPowerOn()

void SysCtlPeripheralPowerOn ( uint32_t ui32Peripheral )

Powers on a peripheral.

Parameters

ui32Peripheral is the peripheral to be powered on.

This function turns on the power to a peripheral. The peripheral continues to receive power even when its clock is not enabled.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_CAN0,SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_USB0

Returns: None.

References ASSERT, HWREGBITW, and SYSCTL_PCBASE.

§ SysCtlPeripheralPowerOff()

void SysCtlPeripheralPowerOff ( uint32_t ui32Peripheral )

Powers off a peripheral.

Parameters

ui32Peripheral is the peripheral to be powered off.

This function allows the power to a peripheral to be turned off. The peripheral continues to receive power when its clock is enabled, but the power is removed when its clock is disabled.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_CAN0,SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_USB0

Returns: None.

References ASSERT, HWREGBITW, and SYSCTL_PCBASE.

§ SysCtlPeripheralReset()

void SysCtlPeripheralReset ( uint32_t ui32Peripheral )

Performs a software reset of a peripheral.

Parameters

ui32Peripheral is the peripheral to reset.

This function performs a software reset of the specified peripheral. An individual peripheral reset signal is asserted for a brief period and then de-asserted, returning the internal state of the peripheral to its reset condition.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CCM0,SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_EEPROM0, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_EPI0, SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH_GPIOK, SYSCTL_PERIPH_GPIOL, SYSCTL_PERIPH_GPIOM, SYSCTL_PERIPH_GPION, SYSCTL_PERIPH_GPIOP, SYSCTL_PERIPH_GPIOQ, SYSCTL_PERIPH_GPIOR, SYSCTL_PERIPH_GPIOS, SYSCTL_PERIPH_GPIOT, SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH_I2C2, SYSCTL_PERIPH_I2C3, SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_I2C6, SYSCTL_PERIPH_I2C7, SYSCTL_PERIPH_I2C8, SYSCTL_PERIPH_I2C9, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_ONEWIRE0, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4, SYSCTL_PERIPH_TIMER5, SYSCTL_PERIPH_TIMER6, SYSCTL_PERIPH_TIMER7, SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART5, SYSCTL_PERIPH_UART6, SYSCTL_PERIPH_UART7, SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH_USB0, SYSCTL_PERIPH_WDOG0, or SYSCTL_PERIPH_WDOG1

Returns: None.

References ASSERT, HWREGBITW, and SYSCTL_SRBASE.

Referenced by EMACPHYConfigSet().

§ SysCtlPeripheralEnable()

void SysCtlPeripheralEnable ( uint32_t ui32Peripheral )

Enables a peripheral.

Parameters

ui32Peripheral is the peripheral to enable.

This function enables a peripheral. At power-up, all peripherals are disabled; they must be enabled in order to operate or respond to register reads/writes.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CCM0,SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_EEPROM0, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_EPI0, SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH_GPIOK, SYSCTL_PERIPH_GPIOL, SYSCTL_PERIPH_GPIOM, SYSCTL_PERIPH_GPION, SYSCTL_PERIPH_GPIOP, SYSCTL_PERIPH_GPIOQ, SYSCTL_PERIPH_GPIOR, SYSCTL_PERIPH_GPIOS, SYSCTL_PERIPH_GPIOT, SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH_I2C2, SYSCTL_PERIPH_I2C3, SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_I2C6, SYSCTL_PERIPH_I2C7, SYSCTL_PERIPH_I2C8, SYSCTL_PERIPH_I2C9, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_ONEWIRE0, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4, SYSCTL_PERIPH_TIMER5, SYSCTL_PERIPH_TIMER6, SYSCTL_PERIPH_TIMER7, SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART5, SYSCTL_PERIPH_UART6, SYSCTL_PERIPH_UART7, SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH_USB0, SYSCTL_PERIPH_WDOG0, or SYSCTL_PERIPH_WDOG1

Note: It takes five clock cycles after the write to enable a peripheral before the the peripheral is actually enabled. During this time, attempts to access the peripheral result in a bus fault. Care should be taken to ensure that the peripheral is not accessed during this brief time period.

Returns: None.

References ASSERT, HWREGBITW, and SYSCTL_RCGCBASE.

§ SysCtlPeripheralDisable()

void SysCtlPeripheralDisable ( uint32_t ui32Peripheral )

Disables a peripheral.

Parameters

ui32Peripheral is the peripheral to disable.

This function disables a peripheral. Once disabled, they do not operate or respond to register reads/writes.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CCM0,SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_EEPROM0, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_EPI0, SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH_GPIOK, SYSCTL_PERIPH_GPIOL, SYSCTL_PERIPH_GPIOM, SYSCTL_PERIPH_GPION, SYSCTL_PERIPH_GPIOP, SYSCTL_PERIPH_GPIOQ, SYSCTL_PERIPH_GPIOR, SYSCTL_PERIPH_GPIOS, SYSCTL_PERIPH_GPIOT, SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH_I2C2, SYSCTL_PERIPH_I2C3, SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_I2C6, SYSCTL_PERIPH_I2C7, SYSCTL_PERIPH_I2C8, SYSCTL_PERIPH_I2C9, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_ONEWIRE0, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4, SYSCTL_PERIPH_TIMER5, SYSCTL_PERIPH_TIMER6, SYSCTL_PERIPH_TIMER7, SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART5, SYSCTL_PERIPH_UART6, SYSCTL_PERIPH_UART7, SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH_USB0, SYSCTL_PERIPH_WDOG0, or SYSCTL_PERIPH_WDOG1

Returns: None.

References ASSERT, HWREGBITW, and SYSCTL_RCGCBASE.

§ SysCtlPeripheralSleepEnable()

void SysCtlPeripheralSleepEnable ( uint32_t ui32Peripheral )

Enables a peripheral in sleep mode.

Parameters

ui32Peripheral is the peripheral to enable in sleep mode.

This function allows a peripheral to continue operating when the processor goes into sleep mode. Because the clocking configuration of the device does not change, any peripheral can safely continue operating while the processor is in sleep mode and can therefore wake the processor from sleep mode.

Sleep mode clocking of peripherals must be enabled via SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode configuration is maintained but has no effect when sleep mode is entered.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CCM0,SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_EEPROM0, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_EPI0, SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH_GPIOK, SYSCTL_PERIPH_GPIOL, SYSCTL_PERIPH_GPIOM, SYSCTL_PERIPH_GPION, SYSCTL_PERIPH_GPIOP, SYSCTL_PERIPH_GPIOQ, SYSCTL_PERIPH_GPIOR, SYSCTL_PERIPH_GPIOS, SYSCTL_PERIPH_GPIOT, SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH_I2C2, SYSCTL_PERIPH_I2C3, SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_I2C6, SYSCTL_PERIPH_I2C7, SYSCTL_PERIPH_I2C8, SYSCTL_PERIPH_I2C9, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_ONEWIRE0, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4, SYSCTL_PERIPH_TIMER5, SYSCTL_PERIPH_TIMER6, SYSCTL_PERIPH_TIMER7, SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART5, SYSCTL_PERIPH_UART6, SYSCTL_PERIPH_UART7, SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH_USB0, SYSCTL_PERIPH_WDOG0, or SYSCTL_PERIPH_WDOG1

Returns: None.

References ASSERT, HWREGBITW, and SYSCTL_SCGCBASE.

§ SysCtlPeripheralSleepDisable()

void SysCtlPeripheralSleepDisable ( uint32_t ui32Peripheral )

Disables a peripheral in sleep mode.

Parameters

ui32Peripheral is the peripheral to disable in sleep mode.

This function causes a peripheral to stop operating when the processor goes into sleep mode. Disabling peripherals while in sleep mode helps to lower the current draw of the device. If enabled (via SysCtlPeripheralEnable()), the peripheral automatically resumes operation when the processor leaves sleep mode, maintaining its entire state from before sleep mode was entered.

Sleep mode clocking of peripherals must be enabled via SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode configuration is maintained but has no effect when sleep mode is entered.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CCM0,SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_EEPROM0, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_EPI0, SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH_GPIOK, SYSCTL_PERIPH_GPIOL, SYSCTL_PERIPH_GPIOM, SYSCTL_PERIPH_GPION, SYSCTL_PERIPH_GPIOP, SYSCTL_PERIPH_GPIOQ, SYSCTL_PERIPH_GPIOR, SYSCTL_PERIPH_GPIOS, SYSCTL_PERIPH_GPIOT, SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH_I2C2, SYSCTL_PERIPH_I2C3, SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_I2C6, SYSCTL_PERIPH_I2C7, SYSCTL_PERIPH_I2C8, SYSCTL_PERIPH_I2C9, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_ONEWIRE0, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4, SYSCTL_PERIPH_TIMER5, SYSCTL_PERIPH_TIMER6, SYSCTL_PERIPH_TIMER7, SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART5, SYSCTL_PERIPH_UART6, SYSCTL_PERIPH_UART7, SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH_USB0, SYSCTL_PERIPH_WDOG0, or SYSCTL_PERIPH_WDOG1

Returns: None.

References ASSERT, HWREGBITW, and SYSCTL_SCGCBASE.

§ SysCtlPeripheralDeepSleepEnable()

void SysCtlPeripheralDeepSleepEnable ( uint32_t ui32Peripheral )

Enables a peripheral in deep-sleep mode.

Parameters

ui32Peripheral is the peripheral to enable in deep-sleep mode.

This function allows a peripheral to continue operating when the processor goes into deep-sleep mode. Because the clocking configuration of the device may change, not all peripherals can safely continue operating while the processor is in deep-sleep mode. Those that must run at a particular frequency (such as a UART) do not work as expected if the clock changes. It is the responsibility of the caller to make sensible choices.

Deep-sleep mode clocking of peripherals must be enabled via SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode configuration is maintained but has no effect when deep-sleep mode is entered.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CCM0,SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_EEPROM0, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_EPI0, SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH_GPIOK, SYSCTL_PERIPH_GPIOL, SYSCTL_PERIPH_GPIOM, SYSCTL_PERIPH_GPION, SYSCTL_PERIPH_GPIOP, SYSCTL_PERIPH_GPIOQ, SYSCTL_PERIPH_GPIOR, SYSCTL_PERIPH_GPIOS, SYSCTL_PERIPH_GPIOT, SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH_I2C2, SYSCTL_PERIPH_I2C3, SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_I2C6, SYSCTL_PERIPH_I2C7, SYSCTL_PERIPH_I2C8, SYSCTL_PERIPH_I2C9, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_ONEWIRE0, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4, SYSCTL_PERIPH_TIMER5, SYSCTL_PERIPH_TIMER6, SYSCTL_PERIPH_TIMER7, SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART5, SYSCTL_PERIPH_UART6, SYSCTL_PERIPH_UART7, SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH_USB0, SYSCTL_PERIPH_WDOG0, or SYSCTL_PERIPH_WDOG1

Returns: None.

References ASSERT, HWREGBITW, and SYSCTL_DCGCBASE.

§ SysCtlPeripheralDeepSleepDisable()

void SysCtlPeripheralDeepSleepDisable ( uint32_t ui32Peripheral )

Disables a peripheral in deep-sleep mode.

Parameters

ui32Peripheral is the peripheral to disable in deep-sleep mode.

This function causes a peripheral to stop operating when the processor goes into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps to lower the current draw of the device, and can keep peripherals that require a particular clock frequency from operating when the clock changes as a result of entering deep-sleep mode. If enabled (via SysCtlPeripheralEnable()), the peripheral automatically resumes operation when the processor leaves deep-sleep mode, maintaining its entire state from before deep-sleep mode was entered.

Deep-sleep mode clocking of peripherals must be enabled via SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode configuration is maintained but has no effect when deep-sleep mode is entered.

The ui32Peripheral parameter must be only one of the following values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CCM0,SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_EEPROM0, SYSCTL_PERIPH_EMAC, SYSCTL_PERIPH_EPHY, SYSCTL_PERIPH_EPI0, SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH_GPIOK, SYSCTL_PERIPH_GPIOL, SYSCTL_PERIPH_GPIOM, SYSCTL_PERIPH_GPION, SYSCTL_PERIPH_GPIOP, SYSCTL_PERIPH_GPIOQ, SYSCTL_PERIPH_GPIOR, SYSCTL_PERIPH_GPIOS, SYSCTL_PERIPH_GPIOT, SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH_I2C2, SYSCTL_PERIPH_I2C3, SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_I2C6, SYSCTL_PERIPH_I2C7, SYSCTL_PERIPH_I2C8, SYSCTL_PERIPH_I2C9, SYSCTL_PERIPH_LCD0, SYSCTL_PERIPH_ONEWIRE0, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4, SYSCTL_PERIPH_TIMER5, SYSCTL_PERIPH_TIMER6, SYSCTL_PERIPH_TIMER7, SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART5, SYSCTL_PERIPH_UART6, SYSCTL_PERIPH_UART7, SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH_USB0, SYSCTL_PERIPH_WDOG0, or SYSCTL_PERIPH_WDOG1

Returns: None.

References ASSERT, HWREGBITW, and SYSCTL_DCGCBASE.

§ SysCtlPeripheralClockGating()

void SysCtlPeripheralClockGating ( bool bEnable )

Controls peripheral clock gating in sleep and deep-sleep mode.

Parameters

bEnable is a boolean that is true if the sleep and deep-sleep peripheral configuration should be used and false if not.

This function controls how peripherals are clocked when the processor goes into sleep or deep-sleep mode. By default, the peripherals are clocked the same as in run mode; if peripheral clock gating is enabled, they are clocked according to the configuration set by SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and SysCtlPeripheralDeepSleepDisable().

Returns: None.

References HWREG, SYSCTL_RSCLKCFG, and SYSCTL_RSCLKCFG_ACG.

§ SysCtlIntRegister()

void SysCtlIntRegister ( void(*)(void) pfnHandler )

Registers an interrupt handler for the system control interrupt.

Parameters

pfnHandler is a pointer to the function to be called when the system control interrupt occurs.

This function registers the handler to be called when a system control interrupt occurs. This function enables the global interrupt in the interrupt controller; specific system control interrupts must be enabled via SysCtlIntEnable(). It is the interrupt handler's responsibility to clear the interrupt source via SysCtlIntClear().

System control can generate interrupts when the PLL achieves lock, if the internal LDO current limit is exceeded, if the internal oscillator fails, if the main oscillator fails, if the internal LDO output voltage droops too much, if the external voltage droops too much, or if the PLL fails.

See also: IntRegister() for important information about registering interrupt handlers.

Returns: None.

References INT_SYSCTL, IntEnable(), and IntRegister().

§ SysCtlIntUnregister()

void SysCtlIntUnregister ( void )

Unregisters the interrupt handler for the system control interrupt.

This function unregisters the handler to be called when a system control interrupt occurs. This function also masks off the interrupt in the interrupt controller so that the interrupt handler no longer is called.

See also: IntRegister() for important information about registering interrupt handlers.

Returns: None.

References INT_SYSCTL, IntDisable(), and IntUnregister().

§ SysCtlIntEnable()

void SysCtlIntEnable ( uint32_t ui32Ints )

Enables individual system control interrupt sources.

Parameters

ui32Ints is a bit mask of the interrupt sources to be enabled. Must be a logical OR of SYSCTL_INT_BOR0, SYSCTL_INT_VDDA_OK, SYSCTL_INT_MOSC_PUP, SYSCTL_INT_USBPLL_LOCK, SYSCTL_INT_PLL_LOCK, SYSCTL_INT_MOSC_FAIL, SYSCTL_INT_BOR, and/or SYSCTL_INT_BOR1.

This function enables the indicated system control interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

Returns: None.

References HWREG, and SYSCTL_IMC.

§ SysCtlIntDisable()

void SysCtlIntDisable ( uint32_t ui32Ints )

Disables individual system control interrupt sources.

Parameters

ui32Ints is a bit mask of the interrupt sources to be disabled. Must be a logical OR of SYSCTL_INT_BOR0, SYSCTL_INT_VDDA_OK, SYSCTL_INT_MOSC_PUP, SYSCTL_INT_USBPLL_LOCK, SYSCTL_INT_PLL_LOCK, SYSCTL_INT_MOSC_FAIL, SYSCTL_INT_BOR, and/or SYSCTL_INT_BOR1.

This function disables the indicated system control interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

Returns: None.

References HWREG, and SYSCTL_IMC.

§ SysCtlIntClear()

void SysCtlIntClear ( uint32_t ui32Ints )

Clears system control interrupt sources.

Parameters

ui32Ints is a bit mask of the interrupt sources to be cleared. Must be a logical OR of SYSCTL_INT_BOR0, SYSCTL_INT_VDDA_OK, SYSCTL_INT_MOSC_PUP, SYSCTL_INT_USBPLL_LOCK, SYSCTL_INT_PLL_LOCK, SYSCTL_INT_MOSC_FAIL, SYSCTL_INT_BOR, and/or SYSCTL_INT_BOR1.

The specified system control interrupt sources are cleared, so that they no longer assert. This function must be called in the interrupt handler to keep it from being called again immediately on exit.

Note: Because there is a write buffer in the Cortex-M processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared. Failure to do so may result in the interrupt handler being immediately reentered (because the interrupt controller still sees the interrupt source asserted).

Returns: None.

References HWREG, and SYSCTL_MISC.

§ SysCtlIntStatus()

uint32_t SysCtlIntStatus ( bool bMasked )

Gets the current interrupt status.

Parameters

bMasked is false if the raw interrupt status is required and true if the masked interrupt status is required.

This function returns the interrupt status for the system controller. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Returns: The current interrupt status, enumerated as a bit field of SYSCTL_INT_BOR0, SYSCTL_INT_VDDA_OK, SYSCTL_INT_MOSC_PUP, SYSCTL_INT_USBPLL_LOCK, SYSCTL_INT_PLL_LOCK, SYSCTL_INT_MOSC_FAIL, SYSCTL_INT_BOR, and/or SYSCTL_INT_BOR1.

References HWREG, SYSCTL_MISC, and SYSCTL_RIS.

§ SysCtlLDODeepSleepSet()

void SysCtlLDODeepSleepSet ( uint32_t ui32Voltage )

Sets the output voltage of the LDO when the device enters deep-sleep mode.

Parameters

ui32Voltage is the required output voltage from the LDO while in deep-sleep mode.

This function sets the output voltage of the LDO while in deep-sleep mode. The ui32Voltage parameter specifies the output voltage of the LDO and must be one of the following values: SYSCTL_LDO_0_90V, SYSCTL_LDO_0_95V, SYSCTL_LDO_1_00V, SYSCTL_LDO_1_05V, SYSCTL_LDO_1_10V, SYSCTL_LDO_1_15V, or SYSCTL_LDO_1_20V.

Returns: None.

References ASSERT, HWREG, SYSCTL_LDO_0_90V, SYSCTL_LDO_0_95V, SYSCTL_LDO_1_00V, SYSCTL_LDO_1_05V, SYSCTL_LDO_1_10V, SYSCTL_LDO_1_15V, SYSCTL_LDO_1_20V, and SYSCTL_LDODPCTL.

§ SysCtlLDODeepSleepGet()

uint32_t SysCtlLDODeepSleepGet ( void )

Returns the output voltage of the LDO when the device enters deep-sleep mode.

This function returns the output voltage of the LDO when the device is in deep-sleep mode, as specified by the control register.

Returns: Returns the deep-sleep-mode voltage of the LDO; is one of SYSCTL_LDO_0_90V, SYSCTL_LDO_0_95V, SYSCTL_LDO_1_00V, SYSCTL_LDO_1_05V, SYSCTL_LDO_1_10V, SYSCTL_LDO_1_15V, or SYSCTL_LDO_1_20V.

References HWREG, and SYSCTL_LDODPCTL.

§ SysCtlSleepPowerSet()

void SysCtlSleepPowerSet ( uint32_t ui32Config )

Configures the power to the flash and SRAM while in sleep mode.

Parameters

ui32Config is the required flash and SRAM power configuration.

This function allows the power configuration of the flash and SRAM while in sleep mode to be set. The ui32Config parameter is the logical OR of the flash power configuration and the SRAM power configuration.

The flash power configuration is specified as either:

SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode, providing fast wake-up time but higher power consumption.
SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing reduced power consumption but longer wake-up time.

The SRAM power configuration is specified as one of:

SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing fast wake-up time but higher power consumption.
SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode, providing reduced power consumption but longer wake-up time.
SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode, providing further reduced power consumption but longer wake-up time.

Returns: None.

References HWREG, and SYSCTL_SLPPWRCFG.

§ SysCtlDeepSleepPowerSet()

void SysCtlDeepSleepPowerSet ( uint32_t ui32Config )

Configures the power to the flash and SRAM while in deep-sleep mode.

Parameters

ui32Config is the required flash and SRAM power configuration.

This function allows the power configuration of the flash and SRAM while in deep-sleep mode to be set. The ui32Config parameter is the logical OR of the flash power configuration and the SRAM power configuration.

The flash power configuration is specified as either:

SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode, providing fast wake-up time but higher power consumption.
SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing reduced power consumption but longer wake-up time.

The SRAM power configuration is specified as one of:

SYSCTL_LDO_SLEEP - The LDO is in sleep mode.
SYSCTL_TEMP_LOW_POWER - The temperature sensor in low power mode.
SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing fast wake-up time but higher power consumption.
SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode, providing reduced power consumption but longer wake-up time.
SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode, providing further reduced power consumption but longer wake-up time.

Returns: None.

References HWREG, and SYSCTL_DSLPPWRCFG.

§ SysCtlReset()

void SysCtlReset ( void )

Resets the device.

This function performs a software reset of the entire device. The processor and all peripherals are reset and all device registers are returned to their default values (with the exception of the reset cause register, which maintains its current value but has the software reset bit set as well).

Returns: This function does not return.

References HWREG, NVIC_APINT, NVIC_APINT_SYSRESETREQ, and NVIC_APINT_VECTKEY.

§ SysCtlSleep()

void SysCtlSleep ( void )

Puts the processor into sleep mode.

This function places the processor into sleep mode; it does not return until the processor returns to run mode. The peripherals that are enabled via SysCtlPeripheralSleepEnable() continue to operate and can wake up the processor (if automatic clock gating is enabled with SysCtlPeripheralClockGating(), otherwise all peripherals continue to operate).

Returns: None.

References CPUwfi().

§ SysCtlDeepSleep()

void SysCtlDeepSleep ( void )

Puts the processor into deep-sleep mode.

This function places the processor into deep-sleep mode; it does not return until the processor returns to run mode. The peripherals that are enabled via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up the processor (if automatic clock gating is enabled with SysCtlPeripheralClockGating(), otherwise all peripherals continue to operate).

Returns: None.

References CPUwfi(), HWREG, NVIC_SYS_CTRL, and NVIC_SYS_CTRL_SLEEPDEEP.

§ SysCtlResetCauseGet()

uint32_t SysCtlResetCauseGet ( void )

Gets the reason for a reset.

This function returns the reason(s) for a reset. Because the reset reasons are sticky until either cleared by software or a power-on reset, multiple reset reasons may be returned if multiple resets have occurred. The reset reason is a logical OR of SYSCTL_CAUSE_HSRVREQ, SYSCTL_CAUSE_HIB, SYSCTL_CAUSE_WDOG1, SYSCTL_CAUSE_SW, SYSCTL_CAUSE_WDOG0, SYSCTL_CAUSE_BOR, SYSCTL_CAUSE_POR, and/or SYSCTL_CAUSE_EXT.

Returns: Returns the reason(s) for a reset.

References HWREG, and SYSCTL_RESC.

§ SysCtlResetCauseClear()

void SysCtlResetCauseClear ( uint32_t ui32Causes )

Clears reset reasons.

Parameters

ui32Causes are the reset causes to be cleared; must be a logical OR of SYSCTL_CAUSE_HSRVREQ, SYSCTL_CAUSE_HIB, SYSCTL_CAUSE_WDOG1, SYSCTL_CAUSE_SW, SYSCTL_CAUSE_WDOG0, SYSCTL_CAUSE_BOR, SYSCTL_CAUSE_POR, and/or SYSCTL_CAUSE_EXT.

This function clears the specified sticky reset reasons. Once cleared, another reset for the same reason can be detected, and a reset for a different reason can be distinguished (instead of having two reset causes set). If the reset reason is used by an application, all reset causes should be cleared after they are retrieved with SysCtlResetCauseGet().

Returns: None.

References HWREG, SYSCTL_RESC, and SysCtlDelay().

§ SysCtlMOSCConfigSet()

void SysCtlMOSCConfigSet ( uint32_t ui32Config )

Provides a small delay.

Parameters

ui32Count is the number of delay loop iterations to perform.

This function provides a means of generating a delay by executing a simple 3 instruction cycle loop a given number of times. It is written in assembly to keep the loop instruction count consistent across tool chains.

It is important to note that this function does NOT provide an accurate timing mechanism. Although the delay loop is 3 instruction cycles long, the execution time of the loop will vary dramatically depending upon the application's interrupt environment (the loop will be interrupted unless run with interrupts disabled and this is generally an unwise thing to do) and also the current system clock rate and flash timings (wait states and the operation of the prefetch buffer affect the timing).

For better accuracy, the ROM version of this function may be used. This version will not suffer from flash- and prefect buffer-related timing variability but will still be delayed by interrupt service routines.

For best accuracy, a system timer should be used with code either polling for a particular timer value being exceeded or processing the timer interrupt to determine when a particular time period has elapsed.

Returns: None. Sets the configuration of the main oscillator (MOSC) control.

Parameters

ui32Config is the required configuration of the MOSC control.

This function configures the control of the main oscillator. The ui32Config is specified as the logical OR of the following values:

SYSCTL_MOSC_VALIDATE enables the MOSC verification circuit that detects a failure of the main oscillator (such as a loss of the clock).
SYSCTL_MOSC_INTERRUPT indicates that a MOSC failure should generate an interrupt instead of resetting the processor.
SYSCTL_MOSC_NO_XTAL indicates that there is no crystal or oscillator connected to the OSC0/OSC1 pins, allowing power consumption to be reduced.
SYSCTL_MOSC_PWR_DIS disable power to the main oscillator. If this parameter is not specified, the MOSC input remains powered.
SYSCTL_MOSC_LOWFREQ MOSC is less than 10 MHz.
SYSCTL_MOSC_HIGHFREQ MOSC is greater than 10 MHz.
SYSCTL_MOSC_SESRC specifies that the MOSC is a single-ended oscillator connected to OSC0. If this parameter is not specified, the input is assumed to be a crystal.

Returns: None.

References HWREG, and SYSCTL_MOSCCTL.

§ SysCtlPIOSCCalibrate()

uint32_t SysCtlPIOSCCalibrate ( uint32_t ui32Type )

Calibrates the precision internal oscillator.

Parameters

ui32Type is the type of calibration to perform.

This function performs a calibration of the PIOSC. There are three types of calibration available; the desired calibration type as specified in ui32Type is one of:

SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the 32-kHz clock from the hibernate module as a reference. This type is only possible if the hibernate module is enabled, a 32.768-kHz clock source is attached to the XOSC0/1 pins and the hibernate module's RTC is also enabled.
SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory provided calibration.
SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied value. The value to be used is ORed into the lower 7-bits of this value, with 0x40 being the ``nominal'' value (in other words, if everything were perfect, 0x40 provides exactly 16 MHz). Values larger than 0x40 slow down PIOSC, and values smaller than 0x40 speed up PIOSC.

Returns: Returns 1 if the calibration was successful and 0 if it failed.

References HWREG, SYSCTL_PIOSCCAL, SYSCTL_PIOSCCAL_CAL, SYSCTL_PIOSCCAL_UPDATE, SYSCTL_PIOSCCAL_UT_M, SYSCTL_PIOSCCAL_UTEN, SYSCTL_PIOSCSTAT, SYSCTL_PIOSCSTAT_CR_M, and SYSCTL_PIOSCSTAT_CRPASS.

§ SysCtlResetBehaviorSet()

void SysCtlResetBehaviorSet ( uint32_t ui32Behavior )

Sets the type of reset issued due to certain reset events.

Parameters

ui32Behavior specifies the types of resets for each of the configurable reset events.

This function sets the types of reset issued when a configurable reset event occurs. The reset events that are configurable are: Watchdog 0 or 1, a brown out and the external RSTn pin. The valid actions are either a system reset or a full POR sequence. See the technical reference manual for more information on the differences between a full POR and a system reset. All reset behaviors can be configured with a single call using the logical OR of the values defined below. Any reset option that is not specifically set remains configured for its default behavior. Either POR or system reset can be selected for each reset cause.

Valid values are logical combinations of the following:

SYSCTL_ONRST_WDOG0_POR configures a Watchdog 0 reset to perform a full POR.
SYSCTL_ONRST_WDOG0_SYS configures a Watchdog 0 reset to perform a system reset.
SYSCTL_ONRST_WDOG1_POR configures a Watchdog 1 reset to perform a full POR.
SYSCTL_ONRST_WDOG1_SYS configures a Watchdog 1 reset to perform a system reset.
SYSCTL_ONRST_BOR_POR configures a brown-out reset to perform a full POR.
SYSCTL_ONRST_BOR_SYS configures a brown-out reset to perform a system reset.
SYSCTL_ONRST_EXT_POR configures an external pin reset to perform a full POR.
SYSCTL_ONRST_EXT_SYS configures an external pin reset to perform a system reset.

Example: Set Watchdog 0 reset to trigger a POR and a brown-out reset to trigger a system reset while leaving the remaining resets with their default behaviors.

//! SysCtlResetBehaviorSet(SYSCTL_ONRST_WDOG0_POR | SYSCTL_ONRST_BOR_SYS);
//!

\return None.

References HWREG, and SYSCTL_RESBEHAVCTL.

§ SysCtlResetBehaviorGet()

uint32_t SysCtlResetBehaviorGet ( void )

Returns the current types of reset issued due to reset events.

This function returns the types of resets issued when a configurable reset occurs. The value returned is a logical OR combination of the valid values that are described in the documentation for the ui32Behavior parameter of the SysCtlResetBehaviorSet() function.

Returns: The reset behaviors for all configurable resets.

References HWREG, and SYSCTL_RESBEHAVCTL.

§ SysCtlClockFreqSet()

uint32_t SysCtlClockFreqSet	(	uint32_t	ui32Config,
		uint32_t	ui32SysClock
	)

Configures the system clock.

Parameters

ui32Config	is the required configuration of the device clocking.
ui32SysClock	is the requested processor frequency.

This function configures the main system clocking for the device. The input frequency, oscillator source, whether or not to enable the PLL, and the system clock divider are all configured with this function. This function configures the system frequency to the closest available divisor of one of the fixed PLL VCO settings provided in the ui32Config parameter. The caller sets the ui32SysClock parameter to request the system clock frequency, and this function then attempts to match this using the values provided in the ui32Config parameter. If this function cannot exactly match the requested frequency, it picks the closest frequency that is lower than the requested frequency. The ui32Config parameter provides the remaining configuration options using a set of defines that are a logical OR of several different values, many of which are grouped into sets where only one of the set can be chosen. This function returns the current system frequency which may not match the requested frequency.

If the application is using an external crystal then the frequency is set by using one of the following values: SYSCTL_XTAL_5MHZ, SYSCTL_XTAL_6MHZ, SYSCTL_XTAL_8MHZ, SYSCTL_XTAL_10MHZ, SYSCTL_XTAL_12MHZ, SYSCTL_XTAL_16MHZ, SYSCTL_XTAL_18MHZ, SYSCTL_XTAL_20MHZ, SYSCTL_XTAL_24MHZ, or SYSCTL_XTAL_25MHz.

The oscillator source is chosen with one of the following values:

SYSCTL_OSC_MAIN to use an external crystal or oscillator.
SYSCTL_OSC_INT to use the 16-MHz precision internal oscillator.
SYSCTL_OSC_INT30 to use the internal low frequency oscillator.
SYSCTL_OSC_EXT32 to use the hibernate modules 32.786-kHz oscillator.

The system clock source is chosen with one of the following values:

SYSCTL_USE_PLL is used to select the PLL output as the system clock.
SYSCTL_USE_OSC is used to choose one of the oscillators as the system clock.

The PLL VCO frequency is chosen with one of the the following values:

SYSCTL_CFG_VCO_480 to set the PLL VCO output to 480-MHz
SYSCTL_CFG_VCO_320 to set the PLL VCO output to 320-MHz

Example: Configure the system clocking to be 40 MHz with a 320-MHz PLL setting using the 16-MHz internal oscillator.

//! SysCtlClockFreqSet(SYSCTL_OSC_INT | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_320,
//!                    40000000);
//!

\return The actual configured system clock frequency in Hz or zero if the
value could not be changed due to a parameter error or PLL lock failure.

References SYSCTL_OSC_EXT32, SYSCTL_OSC_INT, SYSCTL_OSC_INT30, SYSCTL_OSC_MAIN, SYSCTL_RSCLKCFG_OSCSRC_LFIOSC, SYSCTL_RSCLKCFG_OSCSRC_PIOSC, SYSCTL_RSCLKCFG_OSCSRC_RTC, SYSCTL_RSCLKCFG_PLLSRC_PIOSC, SYSCTL_XTAL_16MHZ, SYSCTL_XTAL_25MHZ, SYSCTL_XTAL_5MHZ, and SysCtlXtalCfgToIndex.

§ SysCtlDeepSleepClockConfigSet()

void SysCtlDeepSleepClockConfigSet	(	uint32_t	ui32Div,
		uint32_t	ui32Config
	)

Sets the clock configuration of the device while in deep-sleep mode.

Parameters

ui32Div	is the clock divider when in deep-sleep mode.
ui32Config	is the configuration of the device clocking while in deep-sleep mode.

This function configures the clocking of the device while in deep-sleep mode. The ui32Config parameter selects the oscillator and the ui32Div parameter sets the clock divider used in deep-sleep mode. The valid values for the ui32Div parameter range from 1 to 1024.

The oscillator source is chosen from one of the following values: SYSCTL_DSLP_OSC_MAIN, SYSCTL_DSLP_OSC_INT, SYSCTL_DSLP_OSC_INT30, or SYSCTL_DSLP_OSC_EXT32. The SYSCTL_DSLP_OSC_EXT32 option is only available when the hibernation module is enabled.

The precision internal oscillator can be powered down in deep-sleep mode by specifying SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is not powered down if it is required for operation while in deep-sleep (based on other configuration settings).

The main oscillator can be powered down in deep-sleep mode by specifying SYSCTL_DSLP_MOSC_PD. The main oscillator is not powered down if it is required for operation while in deep-sleep (based on other configuration settings).

Returns: None.

References ASSERT, HWREG, SYSCTL_DSCLKCFG, SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC, SYSCTL_DSCLKCFG_DSOSCSRC_M, SYSCTL_DSCLKCFG_DSOSCSRC_MOSC, SYSCTL_DSCLKCFG_DSOSCSRC_RTC, SYSCTL_DSCLKCFG_MOSCDPD, SYSCTL_DSCLKCFG_PIOSCPD, SYSCTL_DSLP_MOSC_DPD, SYSCTL_DSLP_OSC_EXT32, SYSCTL_DSLP_OSC_INT, SYSCTL_DSLP_OSC_INT30, SYSCTL_DSLP_OSC_MAIN, and SYSCTL_DSLP_PIOSC_PD.

§ SysCtlVoltageEventConfig()

void SysCtlVoltageEventConfig ( uint32_t ui32Config )

Configures the response to system voltage events.

Parameters

ui32Config holds the configuration options for the voltage events.

This function configures the response to voltage-related events. These events are triggered when the voltage rails drop below certain levels. The ui32Config parameter provides the configuration for the voltage events and is a combination of the SYSCTL_VEVENT_* values.

The response to a brown out on the VDDA rail is set by using one of the following values:

SYSCTL_VEVENT_VDDABO_NONE - There is no action taken on a VDDA brown out.
SYSCTL_VEVENT_VDDABO_INT - A system interrupt is generated when a VDDA brown out occurs.
SYSCTL_VEVENT_VDDABO_NMI - An NMI is generated when a VDDA brown out occurs.
SYSCTL_VEVENT_VDDABO_RST - A reset is generated when a VDDA brown out occurs. The type of reset that is generated is controller by the SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet() function.

The response to a brown out on the VDD rail is set by using one of the following values:

SYSCTL_VEVENT_VDDBO_NONE - There is no action taken on a VDD brown out.
SYSCTL_VEVENT_VDDBO_INT - A system interrupt is generated when a VDD brown out occurs.
SYSCTL_VEVENT_VDDBO_NMI - An NMI is generated when a VDD brown out occurs.
SYSCTL_VEVENT_VDDBO_RST - A reset is generated when a VDD brown out occurs. The type of reset that is generated is controller by the SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet() function.

Example: Configure the voltage events to trigger an interrupt on a VDDA brown out, an NMI on a VDDC brown out and a reset on a VDD brown out.

//!
//! //
//! // Configure the BOR rest to trigger a full POR.  This is needed because
//! // the SysCtlVoltageEventConfig() call is triggering a reset so the type
//! // of reset is specified by this call.
//! //
//! SysCtlResetBehaviorSet(SYSCTL_ONRST_BOR_POR);
//!
//! //
//! // Trigger an interrupt on a VDDA brown out and a reset on a VDD brown out.
//! //
//! SysCtlVoltageEventConfig(SYSCTL_VEVENT_VDDABO_INT |
//!                          SYSCTL_VEVENT_VDDBO_RST);
//!

\return None.

References HWREG, and SYSCTL_PTBOCTL.

§ SysCtlVoltageEventStatus()

uint32_t SysCtlVoltageEventStatus ( void )

Returns the voltage event status.

This function returns the voltage event status for the system controller. The value returned is a logical OR of the following values:

SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail.
SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail.

The values returned from this function can be passed to the SysCtlVoltageEventClear() to clear the current voltage event status. Because voltage events are not cleared due to a reset, the voltage event status must be cleared by calling SysCtlVoltageEventClear().

Example: Clear the current voltage event status.

//! uint32_t ui32VoltageEvents;
//!
//! //
//! // Read the current voltage event status.
//! //
//! ui32VoltageEvents = SysCtlVoltageEventStatus();
//!
//! //
//! // Clear all the current voltage events.
//! //
//! SysCtlVoltageEventClear(ui32VoltageEvents);
//!

\return The current voltage event status.

References HWREG, and SYSCTL_PWRTC.

§ SysCtlVoltageEventClear()

void SysCtlVoltageEventClear ( uint32_t ui32Status )

Clears the voltage event status.

Parameters

ui32Status is a bit mask of the voltage events to clear.

This function clears the current voltage events status for the values specified in the ui32Status parameter. The ui32Status value must be a logical OR of the following values:

SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail.
SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail.

Example: Clear the current voltage event status.

//! //
//! // Clear all the current voltage events.
//! //
//! SysCtlVoltageEventClear(SysCtlVoltageEventStatus());
//!

\return None.

References HWREG, and SYSCTL_PWRTC.

§ SysCtlVCOGet()

bool SysCtlVCOGet	(	uint32_t	ui32Crystal,
		uint32_t *	pui32VCOFrequency
	)

Gets the effective VCO frequency.

Parameters

ui32Crystal	holds the crystal value used for the PLL.
pui32VCOFrequency	is a pointer to the storage location which holds value of the VCO computed.

This function calculates the VCO of the PLL before the system divider is applied

Returns: true if the PLL is configured correctly and a VCO is valid or false if the PLL is not used

References HWREG, SYSCTL_RSCLKCFG, SYSCTL_RSCLKCFG_USEPLL, and SysCtlXtalCfgToIndex.

§ SysCtlNMIStatus()

uint32_t SysCtlNMIStatus ( void )

Returns the current NMI status.

This function returns the NMI status for the system controller. The valid values for the ui32Ints parameter are a logical OR of the following values:

SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not start.
SYSCTL_NMI_TAMPER a tamper event has been detected.
SYSCTL_NMI_WDT0 watchdog 0 generated a timeout.
SYSCTL_NMI_WDT1 watchdog 1 generated a timeout.
SYSCTL_NMI_POWER a power event occurred.
SYSCTL_NMI_EXTERNAL an external NMI pin asserted.

Example: Clear all current NMI status flags.

//!
//! //
//! // Clear all the current NMI sources.
//! //
//! SysCtlNMIClear(SysCtlNMIStatus());
//!

\return The current NMI status.

References HWREG, and SYSCTL_NMIC.

§ SysCtlNMIClear()

void SysCtlNMIClear ( uint32_t ui32Ints )

Clears NMI sources.

Parameters

ui32Ints is a bit mask of the non-maskable interrupt sources.

This function clears the current NMI status specified in the ui32Ints parameter. The valid values for the ui32Ints parameter are a logical OR of the following values:

SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not start.
SYSCTL_NMI_TAMPER a tamper event has been detected.
SYSCTL_NMI_WDT0 watchdog 0 generated a timeout.
SYSCTL_NMI_WDT1 watchdog 1 generated a timeout.
SYSCTL_NMI_POWER a power event occurred.
SYSCTL_NMI_EXTERNAL an external NMI pin asserted.

Example: Clear all current NMI status flags.

//!
//! //
//! // Clear all the current NMI sources.
//! //
//! SysCtlNMIClear(SysCtlNMIStatus());
//!

\return None.

References HWREG, and SYSCTL_NMIC.

§ SysCtlClockOutConfig()

void SysCtlClockOutConfig	(	uint32_t	ui32Config,
		uint32_t	ui32Div
	)

Configures and enables or disables the clock output on the DIVSCLK pin.

Parameters

ui32Config	holds the configuration options including enabling or disabling the clock output on the DIVSCLK pin.
ui32Div	is the divisor for the clock selected in the ui32Config parameter.

This function selects the source for the DIVSCLK, enables or disables the clock output and provides an output divider value. The ui32Div parameter specifies the divider for the selected clock source and has a valid range of 1-256. The ui32Config parameter configures the DIVSCLK output based on the following settings:

The first setting allows the output to be enabled or disabled.

SYSCTL_CLKOUT_EN - enable the DIVSCLK output.
SYSCTL_CLKOUT_DIS - disable the DIVSCLK output (default).

The next group of settings selects the source for the DIVSCLK.

SYSCTL_CLKOUT_SYSCLK - use the current system clock as the source (default).
SYSCTL_CLKOUT_PIOSC - use the PIOSC as the source.
SYSCTL_CLKOUT_MOSC - use the MOSC as the source.

Example: Enable the PIOSC divided by 4 as the DIVSCLK output.

//!
//! //
//! // Enable the PIOSC divided by 4 as the DIVSCLK output.
//! //
//! SysCtlClockOutConfig(SYSCTL_DIVSCLK_EN | SYSCTL_DIVSCLK_SRC_PIOSC, 4);
//!

\return None.

References ASSERT, HWREG, SYSCTL_CLKOUT_DIS, SYSCTL_CLKOUT_EN, SYSCTL_CLKOUT_MOSC, SYSCTL_CLKOUT_PIOSC, SYSCTL_CLKOUT_SYSCLK, SYSCTL_DIVSCLK, and SYSCTL_DIVSCLK_DIV_M.

§ SysCtlAltClkConfig()

void SysCtlAltClkConfig ( uint32_t ui32Config )

Configures the alternate peripheral clock source.

Parameters

ui32Config holds the configuration options for the alternate peripheral clock.

This function configures the alternate peripheral clock. The alternate peripheral clock is used to provide a known clock in all operating modes to peripherals that support using the alternate peripheral clock as an input clock. The ui32Config parameter value provides the clock input source using one of the following values:

SYSCTL_ALTCLK_PIOSC - use the PIOSC as the alternate clock source (default).
SYSCTL_ALTCLK_RTCOSC - use the Hibernate module RTC clock as the alternate clock source.
SYSCTL_ALTCLK_LFIOSC - use the low-frequency internal oscillator as the alternate clock source.

Example: Select the Hibernate module RTC clock as the alternate clock source.

//!
//! //
//! // Select the Hibernate module RTC clock as the alternate clock source.
//! //
//! SysCtlAltClkConfig(SYSCTL_ALTCLK_RTCOSC);
//!

\return None.

References HWREG, and SYSCTL_ALTCLKCFG.

Variable Documentation

§ ui32Frequency

uint32_t { ... } ui32Frequency

§ ui32MemTiming

uint32_t { ... } ui32MemTiming

Macros

Functions

Detailed Description

Introduction

API Functions

Programming Example

Macro Definition Documentation

§ FLASH_PP_MAINSS_S

§ SysCtlXtalCfgToIndex

§ MAX_VCO_ENTRIES

§ MAX_XTAL_ENTRIES

§ PLL_M_TO_REG

§ PLL_N_TO_REG

§ PLL_Q_TO_REG

§ SYSCTL_PPBASE

§ SYSCTL_SRBASE

§ SYSCTL_RCGCBASE

§ SYSCTL_SCGCBASE

§ SYSCTL_DCGCBASE

§ SYSCTL_PCBASE

§ SYSCTL_PRBASE

Function Documentation

§ SysCtlSRAMSizeGet()

§ SysCtlFlashSizeGet()

§ SysCtlFlashSectorSizeGet()

§ SysCtlPeripheralPresent()

§ SysCtlPeripheralReady()

§ SysCtlPeripheralPowerOn()

§ SysCtlPeripheralPowerOff()

§ SysCtlPeripheralReset()

§ SysCtlPeripheralEnable()

§ SysCtlPeripheralDisable()

§ SysCtlPeripheralSleepEnable()

§ SysCtlPeripheralSleepDisable()

§ SysCtlPeripheralDeepSleepEnable()

§ SysCtlPeripheralDeepSleepDisable()

§ SysCtlPeripheralClockGating()

§ SysCtlIntRegister()

§ SysCtlIntUnregister()

§ SysCtlIntEnable()

§ SysCtlIntDisable()

§ SysCtlIntClear()

§ SysCtlIntStatus()

§ SysCtlLDODeepSleepSet()

§ SysCtlLDODeepSleepGet()

§ SysCtlSleepPowerSet()

§ SysCtlDeepSleepPowerSet()

§ SysCtlReset()

§ SysCtlSleep()

§ SysCtlDeepSleep()

§ SysCtlResetCauseGet()

§ SysCtlResetCauseClear()

§ SysCtlMOSCConfigSet()

§ SysCtlPIOSCCalibrate()

§ SysCtlResetBehaviorSet()

§ SysCtlResetBehaviorGet()

§ SysCtlClockFreqSet()

§ SysCtlDeepSleepClockConfigSet()

§ SysCtlVoltageEventConfig()

§ SysCtlVoltageEventStatus()

§ SysCtlVoltageEventClear()

§ SysCtlVCOGet()

§ SysCtlNMIStatus()

§ SysCtlNMIClear()

§ SysCtlClockOutConfig()

§ SysCtlAltClkConfig()

Variable Documentation

§ ui32Frequency

§ ui32MemTiming