Data Structures
union	tEMACDES3

struct	tEMACDMADescriptor
	A structure defining a single Ethernet DMA buffer descriptor. More...

struct	tEMACWakeUpFrameFilter

Macros
#define	VALID_CONFIG_FLAGS

#define	VALID_FRMFILTER_FLAGS

#define	EMAC_MASKABLE_INTS

#define	EMAC_NORMAL_INTS

#define	EMAC_ABNORMAL_INTS

#define	EMAC_NON_MASKED_INTS

#define	NUM_MAC_ADDR 4

#define	MAC_ADDR_OFFSET (EMAC_O_ADDR1L - EMAC_O_ADDR0L)

#define	EMAC_O_ADDRL(n) (EMAC_O_ADDR0L + (MAC_ADDR_OFFSET * (n)))

#define	EMAC_O_ADDRH(n) (EMAC_O_ADDR0H + (MAC_ADDR_OFFSET * (n)))

#define	NUM_CLOCK_DIVISORS

#define	DEV_ADDR(x) ((x & 0xF000) >> 12)

#define	REG_ADDR(x) ((x & 0x0FFF))

#define	EMAC_PHY_ADDR 0

#define	htonl(a)

#define	ntohl(a) htonl((a))

#define	htons(a)

#define	ntohs(a) htons((a))

#define	DES0_TX_CTRL_OWN 0x80000000

#define	DES0_TX_CTRL_INTERRUPT 0x40000000

#define	DES0_TX_CTRL_LAST_SEG 0x20000000

#define	DES0_TX_CTRL_FIRST_SEG 0x10000000

#define	DES0_TX_CTRL_DISABLE_CRC 0x08000000

#define	DES0_TX_CTRL_DISABLE_PADDING 0x04000000

#define	DES0_TX_CTRL_ENABLE_TS 0x02000000

#define	DES0_TX_CTRL_REPLACE_CRC 0x01000000

#define	DES0_TX_CTRL_CHKSUM_M 0x00C00000

#define	DES0_TX_CTRL_NO_CHKSUM 0x00000000

#define	DES0_TX_CTRL_IP_HDR_CHKSUM 0x00400000

#define	DES0_TX_CTRL_IP_HDR_PAY_CHKSUM 0x00800000

#define	DES0_TX_CTRL_IP_ALL_CKHSUMS 0x00C00000

#define	DES0_TX_CTRL_END_OF_RING 0x00200000

#define	DES0_TX_CTRL_CHAINED 0x00100000

#define	DES0_TX_CTRL_VLAN_M 0x000C0000

#define	DES0_TX_CTRL_VLAN_NONE 0x00000000

#define	DES0_TX_CTRL_VLAN_REMOVE 0x00040000

#define	DES0_TX_CTRL_VLAN_INSERT 0x00080000

#define	DES0_TX_CTRL_VLAN_REPLACE 0x000C0000

#define	DES0_TX_STAT_TS_CAPTURED 0x00020000

#define	DES0_TX_STAT_IPH_ERR 0x00010000

#define	DES0_TX_STAT_ERR 0x00008000

#define	DES0_TX_STAT_JABBER_TO 0x00004000

#define	DES0_TX_STAT_FLUSHED 0x00002000

#define	DES0_TX_STAT_PAYLOAD_ERR 0x00001000

#define	DES0_TX_STAT_CARRIER_LOST 0x00000800

#define	DES0_TX_STAT_NO_CARRIER 0x00000400

#define	DES0_TX_STAT_TX_L_COLLISION 0x00000200

#define	DES0_TX_STAT_E_COLLISION 0x00000100

#define	DES0_TX_STAT_VLAN_FRAME 0x00000080

#define	DES0_TX_STAT_COL_COUNT_M 0x00000078

#define	DES0_TX_STAT_COL_COUNT_S 3

#define	DES0_TX_STAT_E_DEFERRAL 0x00000004

#define	DES0_TX_STAT_UNDERFLOW 0x00000002

#define	DES0_TX_STAT_DEFERRED 0x00000001

#define	DES1_TX_CTRL_SADDR_MAC1 0x80000000

#define	DES1_TX_CTRL_SADDR_M 0x60000000

#define	DES1_TX_CTRL_SADDR_NONE 0x00000000

#define	DES1_TX_CTRL_SADDR_INSERT 0x20000000

#define	DES1_TX_CTRL_SADDR_REPLACE 0x40000000

#define	DES1_TX_CTRL_BUFF2_SIZE_M 0x1FFF0000

#define	DES1_TX_CTRL_BUFF1_SIZE_M 0x00001FFF

#define	DES1_TX_CTRL_BUFF2_SIZE_S 16

#define	DES1_TX_CTRL_BUFF1_SIZE_S 0

#define	DES0_RX_CTRL_OWN 0x80000000

#define	DES0_RX_STAT_DEST_ADDR_FAIL 0x40000000

#define	DES0_RX_STAT_FRAME_LENGTH_M 0x3FFF0000

#define	DES0_RX_STAT_FRAME_LENGTH_S 16

#define	DES0_RX_STAT_ERR 0x00008000

#define	DES0_RX_STAT_DESCRIPTOR_ERR 0x00004000

#define	DES0_RX_STAT_SRC_ADDR_FAIL 0x00002000

#define	DES0_RX_STAT_LENGTH_ERR 0x00001000

#define	DES0_RX_STAT_OVERFLOW 0x00000800

#define	DES0_RX_STAT_VLAN_TAG 0x00000400

#define	DES0_RX_STAT_FIRST_DESC 0x00000200

#define	DES0_RX_STAT_LAST_DESC 0x00000100

#define	DES0_RX_STAT_TS_AVAILABLE 0x00000080

#define	DES0_RX_STAT_RX_L_COLLISION 0x00000040

#define	DES0_RX_STAT_FRAME_TYPE 0x00000020

#define	DES0_RX_STAT_WDOG_TIMEOUT 0x00000010

#define	DES0_RX_STAT_RX_ERR 0x00000008

#define	DES0_RX_STAT_DRIBBLE_ERR 0x00000004

#define	DES0_RX_STAT_CRC_ERR 0x00000002

#define	DES0_RX_STAT_MAC_ADDR 0x00000001

#define	DES0_RX_STAT_EXT_AVAILABLE 0x00000001

#define	DES1_RX_CTRL_DISABLE_INT 0x80000000

#define	DES1_RX_CTRL_BUFF2_SIZE_M 0x1FFF0000

#define	DES1_RX_CTRL_BUFF2_SIZE_S 16

#define	DES1_RX_CTRL_END_OF_RING 0x00008000

#define	DES1_RX_CTRL_CHAINED 0x00004000

#define	DES1_RX_CTRL_BUFF1_SIZE_M 0x00001FFF

#define	DES1_RX_CTRL_BUFF1_SIZE_S 0

#define	DES4_RX_STAT_TS_DROPPED 0x00004000

#define	DES4_RX_STAT_PTP_VERSION2 0x00002000

#define	DES4_RX_STAT_PTP_TYPE_ETH 0x00001000

#define	DES4_RX_STAT_PTP_TYPE_UDP 0x00000000

#define	DES4_RX_STAT_PTP_MT_M 0x00000F00

#define	DES4_RX_STAT_PTP_MT_NONE 0x00000000

#define	DES4_RX_STAT_PTP_MT_SYNC 0x00000100

#define	DES4_RX_STAT_PTP_MT_FOLLOW_UP 0x00000200

#define	DES4_RX_STAT_PTP_MT_DELAY_REQ 0x00000300

#define	DES4_RX_STAT_PTP_MT_DELAY_RESP 0x00000400

#define	DES4_RX_STAT_PTP_MT_PDELAY_REQ 0x00000500

#define	DES4_RX_STAT_PTP_MT_PDELAY_RESP 0x00000600

#define	DES4_RX_STAT_PTP_MT_PDELAY_RFU 0x00000700

#define	DES4_RX_STAT_PTP_MT_ANNOUNCE 0x00000800

#define	DES4_RX_STAT_PTP_MT_SIGNALLING 0x00000A00

#define	DES4_RX_STAT_PTP_MT_RESERVED 0x00000F00

#define	DES4_RX_STAT_IPV6 0x00000080

#define	DES4_RX_STAT_IPV4 0x00000040

#define	DES4_RX_STAT_IP_CHK_BYPASSED 0x00000020

#define	DES4_RX_STAT_IP_PAYLOAD_ERR 0x00000010

#define	DES4_RX_STAT_IP_HEADER_ERR 0x00000008

#define	DES4_RX_STAT_PAYLOAD_M 0x00000007

#define	DES4_RX_STAT_PAYLOAD_UNKNOWN 0x00000000

#define	DES4_RX_STAT_PAYLOAD_UDP 0x00000001

#define	DES4_RX_STAT_PAYLOAD_TCP 0x00000002

#define	DES4_RX_STAT_PAYLOAD_ICMP 0x00000003

#define	EMAC_BCONFIG_DMA_PRIO_WEIGHT_M 0x30000000

#define	EMAC_BCONFIG_DMA_PRIO_WEIGHT_1 0x00000000

#define	EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 0x10000000

#define	EMAC_BCONFIG_DMA_PRIO_WEIGHT_3 0x20000000

#define	EMAC_BCONFIG_DMA_PRIO_WEIGHT_4 0x30000000

#define	EMAC_BCONFIG_TX_PRIORITY 0x08000000

#define	EMAC_BCONFIG_ADDR_ALIGNED 0x02000000

#define	EMAC_BCONFIG_PRIORITY_M 0x0000C000

#define	EMAC_BCONFIG_PRIORITY_1_1 (0 << 14)

#define	EMAC_BCONFIG_PRIORITY_2_1 (1 << 14)

#define	EMAC_BCONFIG_PRIORITY_3_1 (2 << 14)

#define	EMAC_BCONFIG_PRIORITY_4_1 (3 << 14)

#define	EMAC_BCONFIG_PRIORITY_FIXED 0x00000002

#define	EMAC_BCONFIG_FIXED_BURST 0x00010000

#define	EMAC_BCONFIG_MIXED_BURST 0x04000000

#define	EMAC_PHY_TYPE_INTERNAL 0x00000000

#define	EMAC_PHY_TYPE_EXTERNAL_MII 0x80000000

#define	EMAC_PHY_TYPE_EXTERNAL_RMII 0xC0000000

#define	EMAC_PHY_INT_NIB_TXERR_DET_DIS 0x01000000

#define	EMAC_PHY_INT_RX_ER_DURING_IDLE 0x00800000

#define	EMAC_PHY_INT_ISOLATE_MII_LLOSS 0x00400000

#define	EMAC_PHY_INT_LINK_LOSS_RECOVERY 0x00200000

#define	EMAC_PHY_INT_TDRRUN 0x00100000

#define	EMAC_PHY_INT_LD_ON_RX_ERR_COUNT 0x00040000

#define	EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT 0x00020000

#define	EMAC_PHY_INT_LD_ON_LOW_SNR 0x00010000

#define	EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY 0x00008000

#define	EMAC_PHY_INT_POLARITY_SWAP 0x00004000

#define	EMAC_PHY_INT_MDI_SWAP 0x00002000

#define	EMAC_PHY_INT_ROBUST_MDIX 0x00001000

#define	EMAC_PHY_INT_FAST_MDIX 0x00000800

#define	EMAC_PHY_INT_MDIX_EN 0x00000400

#define	EMAC_PHY_INT_FAST_RXDV_DETECT 0x00000200

#define	EMAC_PHY_INT_FAST_L_UP_DETECT 0x00000100

#define	EMAC_PHY_INT_EXT_FULL_DUPLEX 0x00000080

#define	EMAC_PHY_INT_FAST_AN_80_50_35 0x00000040

#define	EMAC_PHY_INT_FAST_AN_120_75_50 0x00000050

#define	EMAC_PHY_INT_FAST_AN_140_150_100 0x00000060

#define	EMAC_PHY_FORCE_10B_T_HALF_DUPLEX 0x00000000

#define	EMAC_PHY_FORCE_10B_T_FULL_DUPLEX 0x00000002

#define	EMAC_PHY_FORCE_100B_T_HALF_DUPLEX 0x00000004

#define	EMAC_PHY_FORCE_100B_T_FULL_DUPLEX 0x00000006

#define	EMAC_PHY_AN_10B_T_HALF_DUPLEX 0x00000008

#define	EMAC_PHY_AN_10B_T_FULL_DUPLEX 0x0000000A

#define	EMAC_PHY_AN_100B_T_HALF_DUPLEX 0x0000000C

#define	EMAC_PHY_AN_100B_T_FULL_DUPLEX 0x0000000E

#define	EMAC_PHY_INT_HOLD 0x00000001

#define	EMAC_PHY_TYPE_MASK 0xC0000000

#define	EMAC_CONFIG_USE_MACADDR1 0x40000000

#define	EMAC_CONFIG_USE_MACADDR0 0x00000000

#define	EMAC_CONFIG_SA_FROM_DESCRIPTOR 0x00000000

#define	EMAC_CONFIG_SA_INSERT 0x20000000

#define	EMAC_CONFIG_SA_REPLACE 0x30000000

#define	EMAC_CONFIG_2K_PACKETS 0x08000000

#define	EMAC_CONFIG_STRIP_CRC 0x02000000

#define	EMAC_CONFIG_JABBER_DISABLE 0x00400000

#define	EMAC_CONFIG_JUMBO_ENABLE 0x00100000

#define	EMAC_CONFIG_IF_GAP_MASK 0x000E0000

#define	EMAC_CONFIG_IF_GAP_96BITS (0x0 << 17)

#define	EMAC_CONFIG_IF_GAP_88BITS (0x1 << 17)

#define	EMAC_CONFIG_IF_GAP_80BITS (0x2 << 17)

#define	EMAC_CONFIG_IF_GAP_72BITS (0x3 << 17)

#define	EMAC_CONFIG_IF_GAP_64BITS (0x4 << 17)

#define	EMAC_CONFIG_IF_GAP_56BITS (0x5 << 17)

#define	EMAC_CONFIG_IF_GAP_48BITS (0x6 << 17)

#define	EMAC_CONFIG_IF_GAP_40BITS (0x7 << 17)

#define	EMAC_CONFIG_CS_DISABLE 0x00010000

#define	EMAC_CONFIG_100MBPS 0x00004000

#define	EMAC_CONFIG_10MBPS 0x00000000

#define	EMAC_CONFIG_RX_OWN_DISABLE 0x00002000

#define	EMAC_CONFIG_LOOPBACK 0x00001000

#define	EMAC_CONFIG_FULL_DUPLEX 0x00000800

#define	EMAC_CONFIG_HALF_DUPLEX 0x00000000

#define	EMAC_CONFIG_CHECKSUM_OFFLOAD 0x00000400

#define	EMAC_CONFIG_RETRY_DISABLE 0x00000200

#define	EMAC_CONFIG_AUTO_CRC_STRIPPING 0x00000080

#define	EMAC_CONFIG_BO_MASK 0x00000060

#define	EMAC_CONFIG_BO_LIMIT_1024 (0x0 << 5)

#define	EMAC_CONFIG_BO_LIMIT_256 (0x1 << 5)

#define	EMAC_CONFIG_BO_LIMIT_16 (0x2 << 5)

#define	EMAC_CONFIG_BO_LIMIT_2 (0x3 << 5)

#define	EMAC_CONFIG_DEFERRAL_CHK_ENABLE 0x00000010

#define	EMAC_CONFIG_PREAMBLE_MASK 0x00000003

#define	EMAC_CONFIG_7BYTE_PREAMBLE 0x00000000

#define	EMAC_CONFIG_5BYTE_PREAMBLE 0x00000001

#define	EMAC_CONFIG_3BYTE_PREAMBLE 0x00000002

#define	EMAC_MODE_KEEP_BAD_CRC 0x04000000

#define	EMAC_MODE_RX_STORE_FORWARD 0x02000000

#define	EMAC_MODE_RX_FLUSH_DISABLE 0x01000000

#define	EMAC_MODE_TX_STORE_FORWARD 0x00200000

#define	EMAC_MODE_TX_THRESHOLD_16_BYTES (7 << 14)

#define	EMAC_MODE_TX_THRESHOLD_24_BYTES (6 << 14)

#define	EMAC_MODE_TX_THRESHOLD_32_BYTES (5 << 14)

#define	EMAC_MODE_TX_THRESHOLD_40_BYTES (4 << 14)

#define	EMAC_MODE_TX_THRESHOLD_64_BYTES (0 << 14)

#define	EMAC_MODE_TX_THRESHOLD_128_BYTES (1 << 14)

#define	EMAC_MODE_TX_THRESHOLD_192_BYTES (2 << 14)

#define	EMAC_MODE_TX_THRESHOLD_256_BYTES (3 << 14)

#define	EMAC_MODE_RX_ERROR_FRAMES 0x00000080

#define	EMAC_MODE_RX_UNDERSIZED_FRAMES 0x00000040

#define	EMAC_MODE_RX_THRESHOLD_64_BYTES (0 << 3)

#define	EMAC_MODE_RX_THRESHOLD_32_BYTES (1 << 3)

#define	EMAC_MODE_RX_THRESHOLD_96_BYTES (2 << 3)

#define	EMAC_MODE_RX_THRESHOLD_128_BYTES (3 << 3)

#define	EMAC_MODE_OPERATE_2ND_FRAME 0x00000002

#define	EMAC_CONFIG_TX_ENABLED 0x00000008

#define	EMAC_CONFIG_RX_ENABLED 0x00000004

#define	EMAC_MODE_TX_DMA_ENABLED 0x00002000

#define	EMAC_MODE_RX_DMA_ENABLED 0x00000002

#define	EMAC_FRMFILTER_RX_ALL 0x80000000

#define	EMAC_FRMFILTER_VLAN 0x00010000

#define	EMAC_FRMFILTER_HASH_AND_PERFECT 0x00000400

#define	EMAC_FRMFILTER_SADDR 0x00000200

#define	EMAC_FRMFILTER_INV_SADDR 0x00000100

#define	EMAC_FRMFILTER_PASS_MASK (0x03 << 6)

#define	EMAC_FRMFILTER_PASS_NO_CTRL (0x00 << 6)

#define	EMAC_FRMFILTER_PASS_NO_PAUSE (0x01 << 6)

#define	EMAC_FRMFILTER_PASS_ALL_CTRL (0x02 << 6)

#define	EMAC_FRMFILTER_PASS_ADDR_CTRL (0x03 << 6)

#define	EMAC_FRMFILTER_BROADCAST 0x00000020

#define	EMAC_FRMFILTER_PASS_MULTICAST 0x00000010

#define	EMAC_FRMFILTER_INV_DADDR 0x00000008

#define	EMAC_FRMFILTER_HASH_MULTICAST 0x00000004

#define	EMAC_FRMFILTER_HASH_UNICAST 0x00000002

#define	EMAC_FRMFILTER_PROMISCUOUS 0x00000001

#define	EMAC_STATUS_TX_NOT_EMPTY 0x01000000

#define	EMAC_STATUS_TX_WRITING_FIFO 0x00400000

#define	EMAC_STATUS_TRC_STATE_MASK 0x00300000

#define	EMAC_STATUS_TRC_STATE_IDLE (0x00 << 20)

#define	EMAC_STATUS_TRC_STATE_READING (0x01 << 20)

#define	EMAC_STATUS_TRC_STATE_WAITING (0x02 << 20)

#define	EMAC_STATUS_TRC_STATE_STATUS (0x03 << 20)

#define	EMAC_STATUS_TX_PAUSED 0x00080000

#define	EMAC_STATUS_TFC_STATE_MASK 0x00060000

#define	EMAC_STATUS_TFC_STATE_IDLE (0x00 << 17)

#define	EMAC_STATUS_TFC_STATE_WAITING (0x01 << 17)

#define	EMAC_STATUS_TFC_STATE_PAUSING (0x02 << 17)

#define	EMAC_STATUS_TFC_STATE_WRITING (0x03 << 17)

#define	EMAC_STATUS_MAC_NOT_IDLE 0x00010000

#define	EMAC_STATUS_RX_FIFO_LEVEL_MASK 0x00000300

#define	EMAC_STATUS_RX_FIFO_EMPTY (0x00 << 8)

#define	EMAC_STATUS_RX_FIFO_BELOW (0x01 << 8)

#define	EMAC_STATUS_RX_FIFO_ABOVE (0x02 << 8)

#define	EMAC_STATUS_RX_FIFO_FULL (0x03 << 8)

#define	EMAC_STATUS_RX_FIFO_STATE_MASK 0x00000060

#define	EMAC_STATUS_RX_FIFO_IDLE (0x00 << 5)

#define	EMAC_STATUS_RX_FIFO_READING (0x01 << 5)

#define	EMAC_STATUS_RX_FIFO_STATUS (0x02 << 5)

#define	EMAC_STATUS_RX_FIFO_FLUSHING (0x03 << 5)

#define	EMAC_STATUS_RWC_ACTIVE 0x00000010

#define	EMAC_STATUS_RPE_ACTIVE 0x00000001

#define	EMAC_DMA_TXSTAT_MASK (0x07 << 20)

#define	EMAC_DMA_TXSTAT_STOPPED (0x00 << 20)

#define	EMAC_DMA_TXSTAT_RUN_FETCH_DESC (0x01 << 20)

#define	EMAC_DMA_TXSTAT_RUN_WAIT_STATUS (0x02 << 20)

#define	EMAC_DMA_TXSTAT_RUN_READING (0x03 << 20)

#define	EMAC_DMA_TXSTAT_RUN_CLOSE_DESC (0x07 << 20)

#define	EMAC_DMA_TXSTAT_TS_WRITE (0x04 << 20)

#define	EMAC_DMA_TXSTAT_SUSPENDED (0x06 << 20)

#define	EMAC_DMA_RXSTAT_MASK (0x07 << 17)

#define	EMAC_DMA_RXSTAT_STOPPED (0x00 << 17)

#define	EMAC_DMA_RXSTAT_RUN_FETCH_DESC (0x01 << 17)

#define	EMAC_DMA_RXSTAT_RUN_WAIT_PACKET (0x03 << 17)

#define	EMAC_DMA_RXSTAT_SUSPENDED (0x04 << 17)

#define	EMAC_DMA_RXSTAT_RUN_CLOSE_DESC (0x05 << 17)

#define	EMAC_DMA_RXSTAT_TS_WRITE (0x06 << 17)

#define	EMAC_DMA_RXSTAT_RUN_RECEIVING (0x07 << 17)

#define	EMAC_TX_DMA_STATE(x) ((x) & EMAC_DMA_TXSTAT_MASK)

#define	EMAC_RX_DMA_STATE(x) ((x) & EMAC_DMA_RXSTAT_MASK)

#define	EMAC_DMA_ERROR 0x00002000

#define	EMAC_DMA_ERR_MASK 0x03800000

#define	EMAC_DMA_ERR_RX_DATA_WRITE 0x00000000

#define	EMAC_DMA_ERR_TX_DATA_READ 0x01800000

#define	EMAC_DMA_ERR_RX_DESC_WRITE 0x02000000

#define	EMAC_DMA_ERR_TX_DESC_WRITE 0x02800000

#define	EMAC_DMA_ERR_RX_DESC_READ 0x03000000

#define	EMAC_DMA_ERR_TX_DESC_READ 0x03800000

#define	EMAC_FILTER_ADDR_ENABLE 0x80000000

#define	EMAC_FILTER_SOURCE_ADDR 0x40000000

#define	EMAC_FILTER_MASK_BYTE_6 0x20000000

#define	EMAC_FILTER_MASK_BYTE_5 0x10000000

#define	EMAC_FILTER_MASK_BYTE_4 0x08000000

#define	EMAC_FILTER_MASK_BYTE_3 0x04000000

#define	EMAC_FILTER_MASK_BYTE_2 0x03000000

#define	EMAC_FILTER_MASK_BYTE_1 0x01000000

#define	EMAC_FILTER_BYTE_MASK_M 0x3F000000

#define	EMAC_FILTER_BYTE_MASK_S 24

#define	EMAC_TS_MAC_FILTER_ENABLE 0x00040000

#define	EMAC_TS_MAC_FILTER_DISABLE 0x00000000

#define	EMAC_TS_SYNC_FOLLOW_DREQ_DRESP 0x00000000

#define	EMAC_TS_SYNC_ONLY 0x00004000

#define	EMAC_TS_DELAYREQ_ONLY 0x0000C000

#define	EMAC_TS_ALL 0x00010000

#define	EMAC_TS_SYNC_PDREQ_PDRESP 0x00014000

#define	EMAC_TS_DREQ_PDREQ_PDRESP 0x0001C000

#define	EMAC_TS_SYNC_DELAYREQ 0x00020000

#define	EMAC_TS_PDREQ_PDRESP 0x00030000

#define	EMAC_TS_PROCESS_IPV4_UDP 0x00002000

#define	EMAC_TS_PROCESS_IPV6_UDP 0x00001000

#define	EMAC_TS_PROCESS_ETHERNET 0x00000800

#define	EMAC_TS_PTP_VERSION_2 0x00000400

#define	EMAC_TS_PTP_VERSION_1 0x00000000

#define	EMAC_TS_DIGITAL_ROLLOVER 0x00000200

#define	EMAC_TS_BINARY_ROLLOVER 0x00000000

#define	EMAC_TS_ALL_RX_FRAMES 0x00000100

#define	EMAC_TS_UPDATE_FINE 0x00000002

#define	EMAC_TS_UPDATE_COARSE 0x00000000

#define	EPHY_SCR_INPOL_EXT 0x00000008

#define	EPHY_SCR_TINT_EXT 0x00000004

#define	EPHY_SCR_INTEN_EXT 0x00000002

#define	EPHY_SCR_INTOE_EXT 0x00000001

#define	EMAC_INT_PHY 0x80000000

#define	EMAC_INT_EARLY_RECEIVE 0x00004000

#define	EMAC_INT_BUS_ERROR 0x00002000

#define	EMAC_INT_EARLY_TRANSMIT 0x00000400

#define	EMAC_INT_RX_WATCHDOG 0x00000200

#define	EMAC_INT_RX_STOPPED 0x00000100

#define	EMAC_INT_RX_NO_BUFFER 0x00000080

#define	EMAC_INT_RECEIVE 0x00000040

#define	EMAC_INT_TX_UNDERFLOW 0x00000020

#define	EMAC_INT_RX_OVERFLOW 0x00000010

#define	EMAC_INT_TX_JABBER 0x00000008

#define	EMAC_INT_TX_NO_BUFFER 0x00000004

#define	EMAC_INT_TX_STOPPED 0x00000002

#define	EMAC_INT_TRANSMIT 0x00000001

#define	EMAC_INT_NORMAL_INT 0x00010000

#define	EMAC_INT_ABNORMAL_INT 0x00008000

#define	EMAC_INT_LPI 0x40000000

#define	EMAC_INT_TIMESTAMP 0x20000000

#define	EMAC_TS_INT_TARGET_REACHED 0x00000002

#define	EMAC_TS_INT_TS_SEC_OVERFLOW 0x00000001

#define	EMAC_INT_POWER_MGMNT 0x10000000

#define	EMAC_PPS_SINGLE_PULSE 0x00000000

#define	EMAC_PPS_1HZ 0x00000001

#define	EMAC_PPS_2HZ 0x00000002

#define	EMAC_PPS_4HZ 0x00000003

#define	EMAC_PPS_8HZ 0x00000004

#define	EMAC_PPS_16HZ 0x00000005

#define	EMAC_PPS_32HZ 0x00000006

#define	EMAC_PPS_64HZ 0x00000007

#define	EMAC_PPS_128HZ 0x00000008

#define	EMAC_PPS_256HZ 0x00000009

#define	EMAC_PPS_512HZ 0x0000000A

#define	EMAC_PPS_1024HZ 0x0000000B

#define	EMAC_PPS_2048HZ 0x0000000C

#define	EMAC_PPS_4096HZ 0x0000000D

#define	EMAC_PPS_8192HZ 0x0000000E

#define	EMAC_PPS_16384HZ 0x0000000F

#define	EMAC_PPS_32768HZ 0x00000010

#define	EMAC_PPS_TARGET_INT 0x00000000

#define	EMAC_PPS_TARGET_PPS 0x00000060

#define	EMAC_PPS_TARGET_BOTH 0x00000040

#define	EMAC_PPS_COMMAND_NONE 0x00

#define	EMAC_PPS_COMMAND_START_SINGLE 0x01

#define	EMAC_PPS_COMMAND_START_TRAIN 0x02

#define	EMAC_PPS_COMMAND_CANCEL_START 0x03

#define	EMAC_PPS_COMMAND_STOP_AT_TIME 0x04

#define	EMAC_PPS_COMMAND_STOP_NOW 0x05

#define	EMAC_PPS_COMMAND_CANCEL_STOP 0x06

#define	EMAC_VLAN_RX_HASH_ENABLE 0x00080000

#define	EMAC_VLAN_RX_HASH_DISABLE 0x00000000

#define	EMAC_VLAN_RX_SVLAN_ENABLE 0x00040000

#define	EMAC_VLAN_RX_SVLAN_DISABLE 0x00000000

#define	EMAC_VLAN_RX_NORMAL_MATCH 0x00000000

#define	EMAC_VLAN_RX_INVERSE_MATCH 0x00020000

#define	EMAC_VLAN_RX_12BIT_TAG 0x00010000

#define	EMAC_VLAN_RX_16BIT_TAG 0x00000000

#define	EMAC_VLAN_TX_CVLAN 0x00000000

#define	EMAC_VLAN_TX_SVLAN 0x00080000

#define	EMAC_VLAN_TX_USE_VLC 0x00040000

#define	EMAC_VLAN_TX_VLC_NONE 0x00000000

#define	EMAC_VLAN_TX_VLC_DELETE 0x00010000

#define	EMAC_VLAN_TX_VLC_INSERT 0x00020000

#define	EMAC_VLAN_TX_VLC_REPLACE 0x00030000

#define	EMAC_VLAN_TX_VLC_MASK 0x00030000

#define	EMAC_RWU_FILTER_ENABLE 1

#define	EMAC_RWU_FILTER_DISABLE 0

#define	EMAC_RWU_FILTER_MULTICAST 8

#define	EMAC_RWU_FILTER_UNICAST 0

#define	EMAC_PMT_GLOBAL_UNICAST_ENABLE 0x00000200

#define	EMAC_PMT_WAKEUP_PACKET_ENABLE 0x00000004

#define	EMAC_PMT_MAGIC_PACKET_ENABLE 0x00000002

#define	EMAC_PMT_POWER_DOWN 0x00000001

#define	EMAC_PMT_WAKEUP_PACKET_RECEIVED 0x00000040

#define	EMAC_PMT_MAGIC_PACKET_RECEIVED 0x00000020

Typedefs
typedef struct tEMACDMADescriptor	tEMACDMADescriptor

Functions
void	EMACInit (uint32_t ui32Base, uint32_t ui32SysClk, uint32_t ui32BusConfig, uint32_t ui32RxBurst, uint32_t ui32TxBurst, uint32_t ui32DescSkipSize)

void	EMACReset (uint32_t ui32Base)

void	EMACPHYConfigSet (uint32_t ui32Base, uint32_t ui32Config)

void	EMACConfigSet (uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32ModeFlags, uint32_t ui32RxMaxFrameSize)

void	EMACConfigGet (uint32_t ui32Base, uint32_t pui32Config, uint32_t pui32Mode, uint32_t *pui32RxMaxFrameSize)

void	EMACAddrSet (uint32_t ui32Base, uint32_t ui32Index, const uint8_t *pui8MACAddr)

void	EMACAddrGet (uint32_t ui32Base, uint32_t ui32Index, uint8_t *pui8MACAddr)

uint32_t	EMACNumAddrGet (uint32_t ui32Base)

void	EMACAddrFilterSet (uint32_t ui32Base, uint32_t ui32Index, uint32_t ui32Config)

uint32_t	EMACAddrFilterGet (uint32_t ui32Base, uint32_t ui32Index)

void	EMACFrameFilterSet (uint32_t ui32Base, uint32_t ui32FilterOpts)

uint32_t	EMACFrameFilterGet (uint32_t ui32Base)

void	EMACHashFilterSet (uint32_t ui32Base, uint32_t ui32HashHi, uint32_t ui32HashLo)

void	EMACHashFilterGet (uint32_t ui32Base, uint32_t pui32HashHi, uint32_t pui32HashLo)

uint32_t	EMACHashFilterBitCalculate (uint8_t *pui8MACAddr)

void	EMACRxWatchdogTimerSet (uint32_t ui32Base, uint8_t ui8Timeout)

uint32_t	EMACStatusGet (uint32_t ui32Base)

void	EMACTxDMAPollDemand (uint32_t ui32Base)

void	EMACRxDMAPollDemand (uint32_t ui32Base)

void	EMACRxDMADescriptorListSet (uint32_t ui32Base, tEMACDMADescriptor *pDescriptor)

tEMACDMADescriptor *	EMACRxDMADescriptorListGet (uint32_t ui32Base)

tEMACDMADescriptor *	EMACRxDMACurrentDescriptorGet (uint32_t ui32Base)

uint8_t *	EMACRxDMACurrentBufferGet (uint32_t ui32Base)

void	EMACTxDMADescriptorListSet (uint32_t ui32Base, tEMACDMADescriptor *pDescriptor)

tEMACDMADescriptor *	EMACTxDMADescriptorListGet (uint32_t ui32Base)

tEMACDMADescriptor *	EMACTxDMACurrentDescriptorGet (uint32_t ui32Base)

uint8_t *	EMACTxDMACurrentBufferGet (uint32_t ui32Base)

uint32_t	EMACDMAStateGet (uint32_t ui32Base)

void	EMACTxFlush (uint32_t ui32Base)

void	EMACTxEnable (uint32_t ui32Base)

void	EMACTxDisable (uint32_t ui32Base)

void	EMACRxEnable (uint32_t ui32Base)

void	EMACRxDisable (uint32_t ui32Base)

void	EMACIntRegister (uint32_t ui32Base, void(*pfnHandler)(void))

void	EMACIntUnregister (uint32_t ui32Base)

void	EMACIntEnable (uint32_t ui32Base, uint32_t ui32IntFlags)

void	EMACIntDisable (uint32_t ui32Base, uint32_t ui32IntFlags)

uint32_t	EMACIntStatus (uint32_t ui32Base, bool bMasked)

void	EMACIntClear (uint32_t ui32Base, uint32_t ui32IntFlags)

void	EMACPHYWrite (uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr, uint16_t ui16Data)

uint16_t	EMACPHYRead (uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr)

uint16_t	EMACPHYExtendedRead (uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr)

void	EMACPHYExtendedWrite (uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr, uint16_t ui16Value)

void	EMACPHYPowerOff (uint32_t ui32Base, uint8_t ui8PhyAddr)

void	EMACPHYPowerOn (uint32_t ui32Base, uint8_t ui8PhyAddr)

void	EMACTimestampConfigSet (uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32SubSecondInc)

uint32_t	EMACTimestampConfigGet (uint32_t ui32Base, uint32_t *pui32SubSecondInc)

void	EMACTimestampEnable (uint32_t ui32Base)

void	EMACTimestampDisable (uint32_t ui32Base)

void	EMACTimestampSysTimeSet (uint32_t ui32Base, uint32_t ui32Seconds, uint32_t ui32SubSeconds)

void	EMACTimestampSysTimeGet (uint32_t ui32Base, uint32_t pui32Seconds, uint32_t pui32SubSeconds)

void	EMACTimestampSysTimeUpdate (uint32_t ui32Base, uint32_t ui32Seconds, uint32_t ui32SubSeconds, bool bInc)

void	EMACTimestampAddendSet (uint32_t ui32Base, uint32_t ui32Increment)

void	EMACTimestampTargetSet (uint32_t ui32Base, uint32_t ui32Seconds, uint32_t ui32SubSeconds)

void	EMACTimestampTargetIntEnable (uint32_t ui32Base)

void	EMACTimestampTargetIntDisable (uint32_t ui32Base)

uint32_t	EMACTimestampIntStatus (uint32_t ui32Base)

void	EMACTimestampPPSSimpleModeSet (uint32_t ui32Base, uint32_t ui32FreqConfig)

void	EMACTimestampPPSCommandModeSet (uint32_t ui32Base, uint32_t ui32Config)
	Configures the Ethernet MAC PPS output in command mode. More...

void	EMACTimestampPPSCommand (uint32_t ui32Base, uint8_t ui8Cmd)

void	EMACTimestampPPSPeriodSet (uint32_t ui32Base, uint32_t ui32Period, uint32_t ui32Width)

void	EMACVLANRxConfigSet (uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config)

uint32_t	EMACVLANRxConfigGet (uint32_t ui32Base, uint16_t *pui16Tag)

void	EMACVLANTxConfigSet (uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config)

uint32_t	EMACVLANTxConfigGet (uint32_t ui32Base, uint16_t *pui16Tag)

uint32_t	EMACVLANHashFilterBitCalculate (uint16_t ui16Tag)

void	EMACVLANHashFilterSet (uint32_t ui32Base, uint32_t ui32Hash)

uint32_t	EMACVLANHashFilterGet (uint32_t ui32Base)

void	EMACRemoteWakeUpFrameFilterSet (uint32_t ui32Base, const tEMACWakeUpFrameFilter *pFilter)

void	EMACRemoteWakeUpFrameFilterGet (uint32_t ui32Base, tEMACWakeUpFrameFilter *pFilter)

void	EMACPowerManagementControlSet (uint32_t ui32Base, uint32_t ui32Flags)

uint32_t	EMACPowerManagementControlGet (uint32_t ui32Base)

uint32_t	EMACPowerManagementStatusGet (uint32_t ui32Base)

void	EMACWoLEnter (uint32_t ui32Base)

void	EMACLPIConfig (uint32_t ui32Base, bool bLPIConfig, uint16_t ui16LPILSTimer, uint16_t ui16LPITWTimer)

void	EMACLPIEnter (uint32_t ui32Base)

uint16_t	EMACLPIStatus (uint32_t ui32Base)

void	EMACLPILinkSet (uint32_t ui32Base)

void	EMACLPILinkClear (uint32_t ui32Base)

void	EMACPHYMMDWrite (uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr, uint16_t ui16Data)

uint16_t	EMACPHYMMDRead (uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr)

Detailed Description

Introduction

The MSP432E4 Ethernet controller consists of a fully integrated media access controller (MAC) and a network physical (PHY) interface device. The Ethernet controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. Additionally, external PHYs may be connected via either MII or RMII interfaces. Note that this document describes the Ethernet MAC found in MSP432E4 devices which differs markedly from that found in older LM3S devices. The new MAC architecture provides very much improved data handling and throughput using a DMA-based engine in addition to many new hardware features including automatic checksum calculation and insertion, hardware perfect and hash packet filtering, low power operation with remote wakeup and wake-on-LAN capability, VLAN tagging and IEEE1588 types 1 and 2 support. As a result, the API provided has been completely redesigned and cannot be used with older parts.

The Ethernet MAC API provides the set of functions required to implement an interrupt-driven Ethernet driver for the MSP432E4 Ethernet MAC. Functions are provided to configure and control the MAC, to access the register set on the PHY, to transmit and receive Ethernet packets using the MAC's integrated DMA engine, to control timestamp handling for IEEE1588, to configure and control low power operation, to configure and control VLAN tagging, and to configure and control the peripheral interrupts.

API Functions

The Ethernet MAC driver API consists of 9 groups of functions:

Initialization and configuration of the MAC and PHY are controlled using EMACInit(), EMACReset(), EMACPHYConfigSet(), EMACConfigSet(), EMACConfigGet(), EMACAddrSet(), EMACAddrGet() and EMACNumAddrGet().

Packet filtering options are set and queried using EMACFrameFilterSet(), EMACFrameFilterGet(), EMACHashFilterSet(), EMACHashFilterGet(), EMACHashFilterBitCalculate(), EMACAddrFilterSet() and EMACAddrFilterGet().

Transmit and receive DMA descriptors are managed using EMACTxDMAPollDemand(), EMACRxDMAPollDemand(), EMACRxDMADescriptorListSet(), EMACRxDMADescriptorListGet(), EMACRxDMACurrentDescriptorGet(), EMACRxDMACurrentBufferGet(), EMACTxDMADescriptorListSet(), EMACTxDMADescriptorListGet(), EMACTxDMACurrentDescriptorGet() and EMACTxDMACurrentBufferGet().

Overall control of the transmitter and receiver are handled using EMACRxWatchdogTimerSet(), EMACStatusGet(), EMACDMAStateGet(), EMACTxFlush(), EMACTxEnable(), EMACTxDisable(), EMACRxEnable() and EMACRxDisable().

Interrupt management is controlled using EMACIntEnable(), EMACIntDisable(), EMACIntStatus(), EMACIntClear(), EMACIntRegister() and EMACIntUnregister().

The PHY, either internal or external, is controlled using EMACPHYWrite(), EMACPHYExtendedWrite(), EMACPHYRead(), EMACPHYExtendedRead(), EMACPHYPowerOff() and EMACPHYPowerOn().

IEEE1588, Precision Time Protocol timestamping, the integrated PTPD clock and the PPS output signal are controlled using EMACTimestampConfigSet(), EMACTimestampConfigGet(), EMACTimestampAddendSet(), EMACTimestampEnable(), EMACTimestampDisable(), EMACTimestampSysTimeSet(), EMACTimestampSysTimeGet(), EMACTimestampSysTimeUpdate(), EMACTimestampTargetSet(), EMACTimestampTargetIntEnable(), EMACTimestampTargetIntDisable(), EMACTimestampIntStatus(), EMACTimestampPPSSimpleModeSet(), EMACTimestampPPSCommandModeSet(), EMACTimestampPPSCommand() and EMACTimestampPPSPeriodSet().

Control of 802.1Q VLAN packet tagging is handled using EMACVLANRxConfigSet(), EMACVLANRxConfigGet(), EMACVLANTxConfigSet(), EMACVLANTxConfigGet(), EMACVLANHashFilterBitCalculate(), EMACVLANHashFilterSet() and EMACVLANHashFilterGet().

Handling of remote wakeup packets and power management options are controlled using EMACRemoteWakeUpFrameFilterSet(), EMACRemoteWakeUpFrameFilterGet(), EMACPowerManagementControlSet(), EMACPowerManagementControlGet() and EMACPowerManagementStatusGet().

Ethernet MAC Data Transfer

Data is transfered between system SRAM and the Ethernet MAC using independent transmit and receive DMA engines. Each engine is controlled using a list of descriptor structures stored in SRAM and containing frame data buffer pointers, control bits and status information. Two options exist for controlling the arrangement of the descriptor list. Descriptors may be arranged in a ring with a fixed spacing between the start of each descriptor and a control bit in the last descriptor to tell the hardware to return to the head of the list, or they may be configured as a linked list with a pointer in each descriptor directing the hardware to the next descriptor that is to be processed.

Although the hardware supports two distinct descriptor formats for both transmit and receive, a basic 4-word descriptor and an enhanced 8-word descriptor, the DriverLib EMAC driver includes type definitions and labels for only the enhanced descriptor format. Enhanced descriptors allow support for many commonly-used advanced features such as TCP/IP/UDP checksum insertion, VLAN tagging and frame timestamping so using this descriptor format throughout prevents complexity and confusion that could arise due to attempts to handle two somewhat-incompatible formats within the same code. Applications wishing to use the basic descriptor format may do so but must be careful not to use the various descriptor-related types and labels defined in emac.h because many of these will be incorrect for the shorter descriptor format.

The hardware moves through the descriptor lists sequentially until it discovers a descriptor marked as owned by software at which point it stops and waits for the descriptor to be made available to it. Ownership of a given descriptor for both the transmit and receive cases is controlled by the most significant bit of the first descriptor word. When this bit is set, the hardware owns the descriptor and will read its content and use it to control transmission or reception of a frame. When clear, the software owns the descriptor and it is safe for the software to read or write the descriptor content without fear of treading on an ongoing hardware operation.

Management of transmit and receive descriptor lists is the responsibility of software above the EMAC API. While the API provides function calls to set the list start pointers, query the current descriptor and tell the hardware to start and stop reading the list, the actual descriptor contents must be handled above the EMAC layer, typically in the Ethernet interrupt handler which must track the current descriptor position in each ring and ensure that the correct descriptors are written for frame transmission or read for frame reception.

To transmit a frame, software must determine the next descriptor in the transmit list which is not currently owned by the hardware (has the DES0_TX_CTRL_OWN bit in the first descriptor word clear). A pointer to the frame to be transmitted is then written to the third word of the descriptor (pvBuffer1) and its length to the second word (ui32Count). If the descriptor list uses the ring structure rather than the linked list structure, a second buffer may be linked to the same descriptor using the fourth descriptor word (DES3.pvBuffer2) and bits [28:16] of the second word to store its size. Various flags controlling checksum insertion or replacement options, source address insertion or replacement and VLAN tagging are written into the first and second words of the descriptor (ui32CtrlStatus and ui32Count) before the DES0_TX_CTRL_OWN bit in the first word is set to hand the descriptor over to the hardware. If the transmit DMA was stopped waiting for the next descriptor to become available, a call to EMACTxDMAPollDemand() will then ensure that the DMA restarts and transmits the new frame. Once transmission is completed, the hardware clears the DES0_TX_CTRL_OWN bit in the descriptor, returning it to the software and, optionally, raises an interrupt.

Similarly, to receive a frame, software must determine the next descriptor in the receive list which is not currently owned by the hardware (has the DES0_RX_CTRL_OWN bit in the first descriptor word clear). A pointer to an empty buffer into which data from the next received frame will be written must be written to the third word of the descriptor. The buffer size is written into the second word, taking care to preserve the DES1_RX_CTRL_CHAINED and DES1_RX_CTRL_END_OF_RING control bits also found there. Again, if the ring structure is used for the descriptor list, a second buffer may be attached to the descriptor using fields in words 3 and 2 to hold the pointer and size. The descriptor is then passed to the hardware by setting DES0_RX_CTRL_OWN in the first descriptor word. If the receiver had previously stopped due to a lack of available descriptors, a call to EMACRxDMAPollDemand() will cause it to restart.

When a frame is received, the hardware will write its content into the next available receive buffer. If the buffer is smaller than the frame, reception continues in the next available buffer (either the second buffer attached to the current descriptor if a descriptor ring is in use or the first buffer attached to the next descriptor). Once the frame is completed, additional status is written into the receive descriptors to indicate the packet type, the buffer containing the start of the frame and the end of the frame, any errors detected and, optionally, IEEE1588 timestamps, before the DES0_RX_CTRL_OWN bits in affected descriptors are cleared and those descriptors become available to the software again.

Programming Example

The following example shows how to use the this API to initialize the Ethernet controller to transmit and receive packets. Note that this is a very much simplified example which shows only the basic flow required. A full implementation would contain rather more error checking and recovery code.

//*****************************************************************************
//
// Ethernet DMA descriptors.
//
// The MAC hardware needs a minimum of 3 receive descriptors to operate.  The
// number used will be application-dependent and should be tuned for best
// performance.
//
//*****************************************************************************
#define NUM_TX_DESCRIPTORS 3
#define NUM_RX_DESCRIPTORS 3
tEMACDMADescriptor g_psRxDescriptor[NUM_TX_DESCRIPTORS];
tEMACDMADescriptor g_psTxDescriptor[NUM_RX_DESCRIPTORS];
uint32_t g_ui32RxDescIndex;
uint32_t g_ui32TxDescIndex;
//*****************************************************************************
//
// Transmit and receive buffers.  These will typically be allocated within your
// network stack somewhere.
//
//*****************************************************************************
#define RX_BUFFER_SIZE 1536
uint8_t g_ppui8RxBuffer[NUM_RX_DESCRIPTORS][RX_BUFFER_SIZE];
//*****************************************************************************
//
// Read a packet from the DMA receive buffer and return the number of bytes
// read.
//
//*****************************************************************************
int32_t
ProcessReceivedPacket(void)
{
    int_fast32_t i32FrameLen;
    //
    // By default, we assume we got a bad frame.
    //
    i32FrameLen = 0;
    //
    // Make sure that we own the receive descriptor.
    //
    if(!(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus & DES0_RX_CTRL_OWN))
    {
        //
        // We own the receive descriptor so check to see if it contains a valid
        // frame.
        //
        if(!(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus &
             DES0_RX_STAT_ERR))
        {
            //
            // We have a valid frame. First check that the "last descriptor"
            // flag is set.  We sized the receive buffer such that it can
            // always hold a valid frame so this flag should never be clear at
            // this point but...
            //
            if(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus &
               DES0_RX_STAT_LAST_DESC)
            {
                //
                // What size is the received frame?
                //
                i32FrameLen =
                    ((g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus &
                      DES0_RX_STAT_FRAME_LENGTH_M) >>
                     DES0_RX_STAT_FRAME_LENGTH_S);
                //
                // Pass the received buffer up to the application to handle.
                //
                ApplicationProcessFrame(i32FrameLen,
                               g_psRxDescriptor[g_ui32RxDescIndex].pvBuffer1);
            }
        }
        //
        // Now that we are finished dealing with this descriptor, hand
        // it back to the hardware.  Note that we assume
        // ApplicationProcessFrame() is finished with the buffer at this point
        // so it is safe to reuse.
        //
        g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus =
                                                     DES0_RX_CTRL_OWN;
        //
        // Move on to the next descriptor in the chain.
        //
        g_ui32RxDescIndex++;
        if(g_ui32RxDescIndex == NUM_RX_DESCRIPTORS)
        {
            g_ui32RxDescIndex = 0;
        }
    }
    //
    // Return the Frame Length
    //
    return(i32FrameLen);
}
//*****************************************************************************
//
// The interrupt handler for the Ethernet interrupt.
//
//*****************************************************************************
void
EthernetIntHandler(void)
{
    uint32_t ui32Temp;
    //
    // Read and Clear the interrupt.
    //
    ui32Temp = EMACIntStatus(EMAC0_BASE, true);
    EMACIntClear(EMAC0_BASE, ui32Temp);
    //
    // Check to see if an RX Interrupt has occurred.
    //
    if(ui32Temp & EMAC_INT_RECEIVE)
    {
        //
        // Indicate that a packet has been received.
        //
        ProcessReceivedPacket();
    }
}
//*****************************************************************************
//
// Transmit a packet from the supplied buffer.  This function would be called
// directly by the application.  pui8Buf points to the Ethernet frame to send
// and i32BufLen contains the number of bytes in the frame.
//
//*****************************************************************************
static int32_t
PacketTransmit(uint8_t *pui8Buf, int32_t i32BufLen)
{
    //
    // Wait for the transmit descriptor to free up.
    //
    while(g_psTxDescriptor[g_ui32TxDescIndex].ui32CtrlStatus &
          DES0_TX_CTRL_OWN)
    {
        //
        // Spin and waste time.
        //
    }
    //
    // Move to the next descriptor.
    //
    g_ui32TxDescIndex++;
    if(g_ui32TxDescIndex == NUM_TX_DESCRIPTORS)
    {
        g_ui32TxDescIndex = 0;
    }
    //
    // Fill in the packet size and pointer, and tell the transmitter to start
    // work.
    //
    g_psTxDescriptor[g_ui32TxDescIndex].ui32Count = (uint32_t)i32BufLen;
    g_psTxDescriptor[g_ui32TxDescIndex].pvBuffer1 = pui8Buf;
    g_psTxDescriptor[g_ui32TxDescIndex].ui32CtrlStatus =
        (DES0_TX_CTRL_LAST_SEG | DES0_TX_CTRL_FIRST_SEG |
         DES0_TX_CTRL_INTERRUPT | DES0_TX_CTRL_IP_ALL_CKHSUMS |
         DES0_TX_CTRL_CHAINED | DES0_TX_CTRL_OWN);
    //
    // Tell the DMA to reacquire the descriptor now that we've filled it in.
    // This call is benign if the transmitter hasn't stalled and checking
    // the state takes longer than just issuing a poll demand so we do this
    // for all packets.
    //
    EMACTxDMAPollDemand(EMAC0_BASE);
    //
    // Return the number of bytes sent.
    //
    return(i32BufLen);
}
//*****************************************************************************
//
// Initialize the transmit and receive DMA descriptors.
//
//*****************************************************************************
void
InitDescriptors(uint32_t ui32Base)
{
    uint32_t ui32Loop;
    //
    // Initialize each of the transmit descriptors.  Note that we leave the
    // buffer pointer and size empty and the OWN bit clear here since we have
    // not set up any transmissions yet.
    //
    for(ui32Loop = 0; ui32Loop < NUM_TX_DESCRIPTORS; ui32Loop++)
    {
        g_psTxDescriptor[ui32Loop].ui32Count = DES1_TX_CTRL_SADDR_INSERT;
        g_psTxDescriptor[ui32Loop].DES3.pLink =
            (ui32Loop == (NUM_TX_DESCRIPTORS - 1)) ?
            g_psTxDescriptor : &g_psTxDescriptor[ui32Loop + 1];
        g_psTxDescriptor[ui32Loop].ui32CtrlStatus =
            (DES0_TX_CTRL_LAST_SEG | DES0_TX_CTRL_FIRST_SEG |
             DES0_TX_CTRL_INTERRUPT | DES0_TX_CTRL_CHAINED |
             DES0_TX_CTRL_IP_ALL_CKHSUMS);
    }
    //
    // Initialize each of the receive descriptors.  We clear the OWN bit here
    // to make sure that the receiver doesn't start writing anything
    // immediately.
    //
    for(ui32Loop = 0; ui32Loop < NUM_RX_DESCRIPTORS; ui32Loop++)
    {
        g_psRxDescriptor[ui32Loop].ui32CtrlStatus = 0;
        g_psRxDescriptor[ui32Loop].ui32Count =
            (DES1_RX_CTRL_CHAINED |
             (RX_BUFFER_SIZE << DES1_RX_CTRL_BUFF1_SIZE_S));
        g_psRxDescriptor[ui32Loop].pvBuffer1 = g_ppui8RxBuffer[ui32Loop];
        g_psRxDescriptor[ui32Loop].DES3.pLink =
            (ui32Loop == (NUM_RX_DESCRIPTORS - 1)) ?
            g_psRxDescriptor : &g_psRxDescriptor[ui32Loop + 1];
    }
    //
    // Set the descriptor pointers in the hardware.
    //
    EMACRxDMADescriptorListSet(ui32Base, g_psRxDescriptor);
    EMACTxDMADescriptorListSet(ui32Base, g_psTxDescriptor);
    //
    // Start from the beginning of both descriptor chains.  We actually set
    // the transmit descriptor index to the last descriptor in the chain
    // since it will be incremented before use and this means the first
    // transmission we perform will use the correct descriptor.
    //
    g_ui32RxDescIndex = 0;
    g_ui32TxDescIndex = NUM_TX_DESCRIPTORS - 1;
}
//*****************************************************************************
//
// This example demonstrates the use of the Ethernet Controller.
//
//*****************************************************************************
int
main(void)
{
    uint32_t ui32User0, ui32User1, ui32Loop, ui32SysClock;
    uint8_t ui8PHYAddr;
    uint8_t pui8MACAddr[6];
    //
    // Run from the PLL at 120 MHz.
    //
    ui32SysClock = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
                                       SYSCTL_OSC_MAIN |
                                       SYSCTL_USE_PLL |
                                       SYSCTL_CFG_VCO_480), 120000000);
    //
    // Configure the device pins.
    //
    PinoutSet();
    //
    // Read the MAC address from the user registers.
    //
    FlashUserGet(&ui32User0, &ui32User1);
    if((ui32User0 == 0xffffffff) || (ui32User1 == 0xffffffff))
    {
        //
        // We should never get here.  This is an error if the MAC address has
        // not been programmed into the device.  Exit the program.
        //
        while(1)
        {
        }
    }
    //
    // Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC
    // address needed to program the hardware registers, then program the MAC
    // address into the Ethernet Controller registers.
    //
    pui8MACAddr[0] = ((ui32User0 >> 0) & 0xff);
    pui8MACAddr[1] = ((ui32User0 >> 8) & 0xff);
    pui8MACAddr[2] = ((ui32User0 >> 16) & 0xff);
    pui8MACAddr[3] = ((ui32User1 >> 0) & 0xff);
    pui8MACAddr[4] = ((ui32User1 >> 8) & 0xff);
    pui8MACAddr[5] = ((ui32User1 >> 16) & 0xff);
    //
    // Enable and reset the Ethernet modules.
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
    SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
    SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
    //
    // Wait for the MAC to be ready.
    //
    while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0))
    {
    }
    //
    // Configure for use with the internal PHY.
    //
    ui8PHYAddr = 0;
    EMACPHYConfigSet(EMAC0_BASE,
                     (EMAC_PHY_TYPE_INTERNAL |
                      EMAC_PHY_INT_MDIX_EN |
                      EMAC_PHY_AN_100B_T_FULL_DUPLEX));
    //
    // Reset the MAC to latch the PHY configuration.
    //
    EMACReset(EMAC0_BASE);
    //
    // Initialize the MAC and set the DMA mode.
    //
    EMACInit(EMAC0_BASE, ui32SysClock,
             EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED, 4, 4,
             0);
    //
    // Set MAC configuration options.
    //
    EMACConfigSet(EMAC0_BASE,
                  (EMAC_CONFIG_FULL_DUPLEX |
                   EMAC_CONFIG_CHECKSUM_OFFLOAD |
                   EMAC_CONFIG_7BYTE_PREAMBLE |
                   EMAC_CONFIG_IF_GAP_96BITS |
                   EMAC_CONFIG_USE_MACADDR0 |
                   EMAC_CONFIG_SA_FROM_DESCRIPTOR |
                   EMAC_CONFIG_BO_LIMIT_1024),
                  (EMAC_MODE_RX_STORE_FORWARD |
                   EMAC_MODE_TX_STORE_FORWARD |
                   EMAC_MODE_TX_THRESHOLD_64_BYTES |
                   EMAC_MODE_RX_THRESHOLD_64_BYTES), 0);
    //
    // Initialize the Ethernet DMA descriptors.
    //
    InitDescriptors(EMAC0_BASE);
    //
    // Program the hardware with its MAC address (for filtering).
    //
    EMACAddrSet(EMAC0_BASE, 0, pui8MACAddr);
    //
    // Wait for the link to become active.
    //
    while((EMACPHYRead(EMAC0_BASE, ui8PHYAddr, EPHY_BMSR) &
                       EPHY_BMSR_LINKSTAT) == 0)
    {
    }
    //
    // Set MAC filtering options.  We receive all broadcast and multicast
    // packets along with those addressed specifically for us.
    //
    EMACFrameFilterSet(EMAC0_BASE, (EMAC_FRMFILTER_SADDR |
                                    EMAC_FRMFILTER_PASS_MULTICAST |
                                    EMAC_FRMFILTER_PASS_NO_CTRL));
    //
    // Clear any pending interrupts.
    //
    EMACIntClear(EMAC0_BASE, EMACIntStatus(EMAC0_BASE, false));
    //
    // Mark the receive descriptors as available to the DMA to start
    // the receive processing.
    //
    for(ui32Loop = 0; ui32Loop < NUM_RX_DESCRIPTORS; ui32Loop++)
    {
        g_psRxDescriptor[ui32Loop].ui32CtrlStatus |= DES0_RX_CTRL_OWN;
    }
    //
    // Enable the Ethernet MAC transmitter and receiver.
    //
    EMACTxEnable(EMAC0_BASE);
    EMACRxEnable(EMAC0_BASE);
    //
    // Enable the Ethernet interrupt.
    //
    IntEnable(INT_EMAC0);
    //
    // Enable the Ethernet RX Packet interrupt source.
    //
    EMACIntEnable(EMAC0_BASE, EMAC_INT_RECEIVE);
    //
    // Application main loop continues....
    //
    while(1)
    {
        //
        // Do main loop things...
        //
    }
}

Macro Definition Documentation

§ VALID_CONFIG_FLAGS

#define VALID_CONFIG_FLAGS

Value:

(EMAC_CONFIG_USE_MACADDR1 |                   \
                                 EMAC_CONFIG_SA_INSERT |                      \
                                 EMAC_CONFIG_SA_REPLACE |                     \
                                 EMAC_CONFIG_2K_PACKETS |                     \
                                 EMAC_CONFIG_STRIP_CRC |                      \
                                 EMAC_CONFIG_JABBER_DISABLE |                 \
                                 EMAC_CONFIG_JUMBO_ENABLE |                   \
                                 EMAC_CONFIG_IF_GAP_MASK |                    \
                                 EMAC_CONFIG_CS_DISABLE |                     \
                                 EMAC_CONFIG_100MBPS |                        \
                                 EMAC_CONFIG_RX_OWN_DISABLE |                 \
                                 EMAC_CONFIG_LOOPBACK |                       \
                                 EMAC_CONFIG_FULL_DUPLEX |                    \
                                 EMAC_CONFIG_CHECKSUM_OFFLOAD |               \
                                 EMAC_CONFIG_RETRY_DISABLE |                  \
                                 EMAC_CONFIG_AUTO_CRC_STRIPPING |             \
                                 EMAC_CONFIG_BO_MASK |                        \
                                 EMAC_CONFIG_DEFERRAL_CHK_ENABLE |            \
                                 EMAC_CONFIG_PREAMBLE_MASK)

Referenced by EMACConfigGet(), and EMACConfigSet().

§ VALID_FRMFILTER_FLAGS

#define VALID_FRMFILTER_FLAGS

Value:

(EMAC_FRMFILTER_RX_ALL |                      \
                                 EMAC_FRMFILTER_VLAN |                        \
                                 EMAC_FRMFILTER_HASH_AND_PERFECT |            \
                                 EMAC_FRMFILTER_SADDR |                       \
                                 EMAC_FRMFILTER_INV_SADDR |                   \
                                 EMAC_FRMFILTER_PASS_NO_PAUSE |               \
                                 EMAC_FRMFILTER_PASS_ALL_CTRL |               \
                                 EMAC_FRMFILTER_PASS_ADDR_CTRL |              \
                                 EMAC_FRMFILTER_BROADCAST |                   \
                                 EMAC_FRMFILTER_PASS_MULTICAST |              \
                                 EMAC_FRMFILTER_INV_DADDR |                   \
                                 EMAC_FRMFILTER_HASH_MULTICAST |              \
                                 EMAC_FRMFILTER_HASH_UNICAST |                \
                                 EMAC_FRMFILTER_PROMISCUOUS)

Referenced by EMACFrameFilterGet(), and EMACFrameFilterSet().

§ EMAC_MASKABLE_INTS

#define EMAC_MASKABLE_INTS

Value:

(EMAC_INT_EARLY_RECEIVE |                     \
                                 EMAC_INT_BUS_ERROR |                         \
                                 EMAC_INT_EARLY_TRANSMIT |                    \
                                 EMAC_INT_RX_WATCHDOG |                       \
                                 EMAC_INT_RX_STOPPED |                        \
                                 EMAC_INT_RX_NO_BUFFER |                      \
                                 EMAC_INT_RECEIVE |                           \
                                 EMAC_INT_TX_UNDERFLOW |                      \
                                 EMAC_INT_RX_OVERFLOW |                       \
                                 EMAC_INT_TX_JABBER |                         \
                                 EMAC_INT_TX_NO_BUFFER |                      \
                                 EMAC_INT_TX_STOPPED |                        \
                                 EMAC_INT_TRANSMIT |                          \
                                 EMAC_INT_NORMAL_INT |                        \
                                 EMAC_INT_ABNORMAL_INT |                      \
                                 EMAC_INT_PHY)

Referenced by EMACIntDisable(), and EMACIntEnable().

§ EMAC_NORMAL_INTS

#define EMAC_NORMAL_INTS

Value:

(EMAC_INT_TRANSMIT |                          \
                                 EMAC_INT_RECEIVE |                           \
                                 EMAC_INT_EARLY_RECEIVE |                     \
                                 EMAC_INT_TX_NO_BUFFER)

Referenced by EMACIntClear(), EMACIntDisable(), and EMACIntEnable().

§ EMAC_ABNORMAL_INTS

#define EMAC_ABNORMAL_INTS

Value:

(EMAC_INT_TX_STOPPED |                        \
                                 EMAC_INT_TX_JABBER |                         \
                                 EMAC_INT_RX_OVERFLOW |                       \
                                 EMAC_INT_TX_UNDERFLOW |                      \
                                 EMAC_INT_RX_NO_BUFFER |                      \
                                 EMAC_INT_RX_STOPPED |                        \
                                 EMAC_INT_RX_WATCHDOG |                       \
                                 EMAC_INT_EARLY_TRANSMIT |                    \
                                 EMAC_INT_BUS_ERROR)

Referenced by EMACIntClear(), EMACIntDisable(), and EMACIntEnable().

§ EMAC_NON_MASKED_INTS

#define EMAC_NON_MASKED_INTS

Value:

(EMAC_DMARIS_LPI |                            \
                                 EMAC_DMARIS_TT |                             \
                                 EMAC_DMARIS_PMT |                            \
                                 EMAC_DMARIS_MMC)

Referenced by EMACIntStatus().

§ NUM_MAC_ADDR

#define NUM_MAC_ADDR 4

Referenced by EMACAddrFilterGet(), EMACAddrFilterSet(), EMACAddrGet(), EMACAddrSet(), and EMACNumAddrGet().

§ MAC_ADDR_OFFSET

#define MAC_ADDR_OFFSET (EMAC_O_ADDR1L - EMAC_O_ADDR0L)

§ EMAC_O_ADDRL

#define EMAC_O_ADDRL ( n ) (EMAC_O_ADDR0L + (MAC_ADDR_OFFSET * (n)))

Referenced by EMACAddrFilterSet(), EMACAddrGet(), and EMACAddrSet().

§ EMAC_O_ADDRH

#define EMAC_O_ADDRH ( n ) (EMAC_O_ADDR0H + (MAC_ADDR_OFFSET * (n)))

Referenced by EMACAddrFilterGet(), EMACAddrFilterSet(), EMACAddrGet(), and EMACAddrSet().

§ NUM_CLOCK_DIVISORS

#define NUM_CLOCK_DIVISORS

Value:

(sizeof(g_pi16MIIClockDiv) / \

sizeof(g_pi16MIIClockDiv[0]))

§ DEV_ADDR

#define DEV_ADDR ( x ) ((x & 0xF000) >> 12)

Referenced by EMACPHYMMDRead(), and EMACPHYMMDWrite().

§ REG_ADDR

#define REG_ADDR ( x ) ((x & 0x0FFF))

Referenced by EMACPHYMMDRead(), and EMACPHYMMDWrite().

§ EMAC_PHY_ADDR

#define EMAC_PHY_ADDR 0

§ htonl

#define htonl ( a )

Value:

((((a) >> 24) & 0x000000ff) |   \
         (((a) >>  8) & 0x0000ff00) |   \
         (((a) <<  8) & 0x00ff0000) |   \
         (((a) << 24) & 0xff000000))

§ ntohl

#define ntohl ( a ) htonl((a))

§ htons

#define htons ( a )

Value:

((((a) >> 8) & 0x00ff) | \

(((a) << 8) & 0xff00))

§ ntohs

#define ntohs ( a ) htons((a))

§ DES0_TX_CTRL_OWN

#define DES0_TX_CTRL_OWN 0x80000000

§ DES0_TX_CTRL_INTERRUPT

#define DES0_TX_CTRL_INTERRUPT 0x40000000

§ DES0_TX_CTRL_LAST_SEG

#define DES0_TX_CTRL_LAST_SEG 0x20000000

§ DES0_TX_CTRL_FIRST_SEG

#define DES0_TX_CTRL_FIRST_SEG 0x10000000

§ DES0_TX_CTRL_DISABLE_CRC

#define DES0_TX_CTRL_DISABLE_CRC 0x08000000

§ DES0_TX_CTRL_DISABLE_PADDING

#define DES0_TX_CTRL_DISABLE_PADDING 0x04000000

§ DES0_TX_CTRL_ENABLE_TS

#define DES0_TX_CTRL_ENABLE_TS 0x02000000

§ DES0_TX_CTRL_REPLACE_CRC

#define DES0_TX_CTRL_REPLACE_CRC 0x01000000

§ DES0_TX_CTRL_CHKSUM_M

#define DES0_TX_CTRL_CHKSUM_M 0x00C00000

§ DES0_TX_CTRL_NO_CHKSUM

#define DES0_TX_CTRL_NO_CHKSUM 0x00000000

§ DES0_TX_CTRL_IP_HDR_CHKSUM

#define DES0_TX_CTRL_IP_HDR_CHKSUM 0x00400000

§ DES0_TX_CTRL_IP_HDR_PAY_CHKSUM

#define DES0_TX_CTRL_IP_HDR_PAY_CHKSUM 0x00800000

§ DES0_TX_CTRL_IP_ALL_CKHSUMS

#define DES0_TX_CTRL_IP_ALL_CKHSUMS 0x00C00000

§ DES0_TX_CTRL_END_OF_RING

#define DES0_TX_CTRL_END_OF_RING 0x00200000

§ DES0_TX_CTRL_CHAINED

#define DES0_TX_CTRL_CHAINED 0x00100000

§ DES0_TX_CTRL_VLAN_M

#define DES0_TX_CTRL_VLAN_M 0x000C0000

§ DES0_TX_CTRL_VLAN_NONE

#define DES0_TX_CTRL_VLAN_NONE 0x00000000

§ DES0_TX_CTRL_VLAN_REMOVE

#define DES0_TX_CTRL_VLAN_REMOVE 0x00040000

§ DES0_TX_CTRL_VLAN_INSERT

#define DES0_TX_CTRL_VLAN_INSERT 0x00080000

§ DES0_TX_CTRL_VLAN_REPLACE

#define DES0_TX_CTRL_VLAN_REPLACE 0x000C0000

§ DES0_TX_STAT_TS_CAPTURED

#define DES0_TX_STAT_TS_CAPTURED 0x00020000

§ DES0_TX_STAT_IPH_ERR

#define DES0_TX_STAT_IPH_ERR 0x00010000

§ DES0_TX_STAT_ERR

#define DES0_TX_STAT_ERR 0x00008000

§ DES0_TX_STAT_JABBER_TO

#define DES0_TX_STAT_JABBER_TO 0x00004000

§ DES0_TX_STAT_FLUSHED

#define DES0_TX_STAT_FLUSHED 0x00002000

§ DES0_TX_STAT_PAYLOAD_ERR

#define DES0_TX_STAT_PAYLOAD_ERR 0x00001000

§ DES0_TX_STAT_CARRIER_LOST

#define DES0_TX_STAT_CARRIER_LOST 0x00000800

§ DES0_TX_STAT_NO_CARRIER

#define DES0_TX_STAT_NO_CARRIER 0x00000400

§ DES0_TX_STAT_TX_L_COLLISION

#define DES0_TX_STAT_TX_L_COLLISION 0x00000200

§ DES0_TX_STAT_E_COLLISION

#define DES0_TX_STAT_E_COLLISION 0x00000100

§ DES0_TX_STAT_VLAN_FRAME

#define DES0_TX_STAT_VLAN_FRAME 0x00000080

§ DES0_TX_STAT_COL_COUNT_M

#define DES0_TX_STAT_COL_COUNT_M 0x00000078

§ DES0_TX_STAT_COL_COUNT_S

#define DES0_TX_STAT_COL_COUNT_S 3

§ DES0_TX_STAT_E_DEFERRAL

#define DES0_TX_STAT_E_DEFERRAL 0x00000004

§ DES0_TX_STAT_UNDERFLOW

#define DES0_TX_STAT_UNDERFLOW 0x00000002

§ DES0_TX_STAT_DEFERRED

#define DES0_TX_STAT_DEFERRED 0x00000001

§ DES1_TX_CTRL_SADDR_MAC1

#define DES1_TX_CTRL_SADDR_MAC1 0x80000000

§ DES1_TX_CTRL_SADDR_M

#define DES1_TX_CTRL_SADDR_M 0x60000000

§ DES1_TX_CTRL_SADDR_NONE

#define DES1_TX_CTRL_SADDR_NONE 0x00000000

§ DES1_TX_CTRL_SADDR_INSERT

#define DES1_TX_CTRL_SADDR_INSERT 0x20000000

§ DES1_TX_CTRL_SADDR_REPLACE

#define DES1_TX_CTRL_SADDR_REPLACE 0x40000000

§ DES1_TX_CTRL_BUFF2_SIZE_M

#define DES1_TX_CTRL_BUFF2_SIZE_M 0x1FFF0000

§ DES1_TX_CTRL_BUFF1_SIZE_M

#define DES1_TX_CTRL_BUFF1_SIZE_M 0x00001FFF

§ DES1_TX_CTRL_BUFF2_SIZE_S

#define DES1_TX_CTRL_BUFF2_SIZE_S 16

§ DES1_TX_CTRL_BUFF1_SIZE_S

#define DES1_TX_CTRL_BUFF1_SIZE_S 0

§ DES0_RX_CTRL_OWN

#define DES0_RX_CTRL_OWN 0x80000000

§ DES0_RX_STAT_DEST_ADDR_FAIL

#define DES0_RX_STAT_DEST_ADDR_FAIL 0x40000000

§ DES0_RX_STAT_FRAME_LENGTH_M

#define DES0_RX_STAT_FRAME_LENGTH_M 0x3FFF0000

§ DES0_RX_STAT_FRAME_LENGTH_S

#define DES0_RX_STAT_FRAME_LENGTH_S 16

§ DES0_RX_STAT_ERR

#define DES0_RX_STAT_ERR 0x00008000

§ DES0_RX_STAT_DESCRIPTOR_ERR

#define DES0_RX_STAT_DESCRIPTOR_ERR 0x00004000

§ DES0_RX_STAT_SRC_ADDR_FAIL

#define DES0_RX_STAT_SRC_ADDR_FAIL 0x00002000

§ DES0_RX_STAT_LENGTH_ERR

#define DES0_RX_STAT_LENGTH_ERR 0x00001000

§ DES0_RX_STAT_OVERFLOW

#define DES0_RX_STAT_OVERFLOW 0x00000800

§ DES0_RX_STAT_VLAN_TAG

#define DES0_RX_STAT_VLAN_TAG 0x00000400

§ DES0_RX_STAT_FIRST_DESC

#define DES0_RX_STAT_FIRST_DESC 0x00000200

§ DES0_RX_STAT_LAST_DESC

#define DES0_RX_STAT_LAST_DESC 0x00000100

§ DES0_RX_STAT_TS_AVAILABLE

#define DES0_RX_STAT_TS_AVAILABLE 0x00000080

§ DES0_RX_STAT_RX_L_COLLISION

#define DES0_RX_STAT_RX_L_COLLISION 0x00000040

§ DES0_RX_STAT_FRAME_TYPE

#define DES0_RX_STAT_FRAME_TYPE 0x00000020

§ DES0_RX_STAT_WDOG_TIMEOUT

#define DES0_RX_STAT_WDOG_TIMEOUT 0x00000010

§ DES0_RX_STAT_RX_ERR

#define DES0_RX_STAT_RX_ERR 0x00000008

§ DES0_RX_STAT_DRIBBLE_ERR

#define DES0_RX_STAT_DRIBBLE_ERR 0x00000004

§ DES0_RX_STAT_CRC_ERR

#define DES0_RX_STAT_CRC_ERR 0x00000002

§ DES0_RX_STAT_MAC_ADDR

#define DES0_RX_STAT_MAC_ADDR 0x00000001

§ DES0_RX_STAT_EXT_AVAILABLE

#define DES0_RX_STAT_EXT_AVAILABLE 0x00000001

§ DES1_RX_CTRL_DISABLE_INT

#define DES1_RX_CTRL_DISABLE_INT 0x80000000

§ DES1_RX_CTRL_BUFF2_SIZE_M

#define DES1_RX_CTRL_BUFF2_SIZE_M 0x1FFF0000

§ DES1_RX_CTRL_BUFF2_SIZE_S

#define DES1_RX_CTRL_BUFF2_SIZE_S 16

§ DES1_RX_CTRL_END_OF_RING

#define DES1_RX_CTRL_END_OF_RING 0x00008000

§ DES1_RX_CTRL_CHAINED

#define DES1_RX_CTRL_CHAINED 0x00004000

§ DES1_RX_CTRL_BUFF1_SIZE_M

#define DES1_RX_CTRL_BUFF1_SIZE_M 0x00001FFF

§ DES1_RX_CTRL_BUFF1_SIZE_S

#define DES1_RX_CTRL_BUFF1_SIZE_S 0

§ DES4_RX_STAT_TS_DROPPED

#define DES4_RX_STAT_TS_DROPPED 0x00004000

§ DES4_RX_STAT_PTP_VERSION2

#define DES4_RX_STAT_PTP_VERSION2 0x00002000

§ DES4_RX_STAT_PTP_TYPE_ETH

#define DES4_RX_STAT_PTP_TYPE_ETH 0x00001000

§ DES4_RX_STAT_PTP_TYPE_UDP

#define DES4_RX_STAT_PTP_TYPE_UDP 0x00000000

§ DES4_RX_STAT_PTP_MT_M

#define DES4_RX_STAT_PTP_MT_M 0x00000F00

§ DES4_RX_STAT_PTP_MT_NONE

#define DES4_RX_STAT_PTP_MT_NONE 0x00000000

§ DES4_RX_STAT_PTP_MT_SYNC

#define DES4_RX_STAT_PTP_MT_SYNC 0x00000100

§ DES4_RX_STAT_PTP_MT_FOLLOW_UP

#define DES4_RX_STAT_PTP_MT_FOLLOW_UP 0x00000200

§ DES4_RX_STAT_PTP_MT_DELAY_REQ

#define DES4_RX_STAT_PTP_MT_DELAY_REQ 0x00000300

§ DES4_RX_STAT_PTP_MT_DELAY_RESP

#define DES4_RX_STAT_PTP_MT_DELAY_RESP 0x00000400

§ DES4_RX_STAT_PTP_MT_PDELAY_REQ

#define DES4_RX_STAT_PTP_MT_PDELAY_REQ 0x00000500

§ DES4_RX_STAT_PTP_MT_PDELAY_RESP

#define DES4_RX_STAT_PTP_MT_PDELAY_RESP 0x00000600

§ DES4_RX_STAT_PTP_MT_PDELAY_RFU

#define DES4_RX_STAT_PTP_MT_PDELAY_RFU 0x00000700

§ DES4_RX_STAT_PTP_MT_ANNOUNCE

#define DES4_RX_STAT_PTP_MT_ANNOUNCE 0x00000800

§ DES4_RX_STAT_PTP_MT_SIGNALLING

#define DES4_RX_STAT_PTP_MT_SIGNALLING 0x00000A00

§ DES4_RX_STAT_PTP_MT_RESERVED

#define DES4_RX_STAT_PTP_MT_RESERVED 0x00000F00

§ DES4_RX_STAT_IPV6

#define DES4_RX_STAT_IPV6 0x00000080

§ DES4_RX_STAT_IPV4

#define DES4_RX_STAT_IPV4 0x00000040

§ DES4_RX_STAT_IP_CHK_BYPASSED

#define DES4_RX_STAT_IP_CHK_BYPASSED 0x00000020

§ DES4_RX_STAT_IP_PAYLOAD_ERR

#define DES4_RX_STAT_IP_PAYLOAD_ERR 0x00000010

§ DES4_RX_STAT_IP_HEADER_ERR

#define DES4_RX_STAT_IP_HEADER_ERR 0x00000008

§ DES4_RX_STAT_PAYLOAD_M

#define DES4_RX_STAT_PAYLOAD_M 0x00000007

§ DES4_RX_STAT_PAYLOAD_UNKNOWN

#define DES4_RX_STAT_PAYLOAD_UNKNOWN 0x00000000

§ DES4_RX_STAT_PAYLOAD_UDP

#define DES4_RX_STAT_PAYLOAD_UDP 0x00000001

§ DES4_RX_STAT_PAYLOAD_TCP

#define DES4_RX_STAT_PAYLOAD_TCP 0x00000002

§ DES4_RX_STAT_PAYLOAD_ICMP

#define DES4_RX_STAT_PAYLOAD_ICMP 0x00000003

§ EMAC_BCONFIG_DMA_PRIO_WEIGHT_M

#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_M 0x30000000

§ EMAC_BCONFIG_DMA_PRIO_WEIGHT_1

#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_1 0x00000000

§ EMAC_BCONFIG_DMA_PRIO_WEIGHT_2

#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 0x10000000

§ EMAC_BCONFIG_DMA_PRIO_WEIGHT_3

#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_3 0x20000000

§ EMAC_BCONFIG_DMA_PRIO_WEIGHT_4

#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_4 0x30000000

§ EMAC_BCONFIG_TX_PRIORITY

#define EMAC_BCONFIG_TX_PRIORITY 0x08000000

§ EMAC_BCONFIG_ADDR_ALIGNED

#define EMAC_BCONFIG_ADDR_ALIGNED 0x02000000

§ EMAC_BCONFIG_PRIORITY_M

#define EMAC_BCONFIG_PRIORITY_M 0x0000C000

§ EMAC_BCONFIG_PRIORITY_1_1

#define EMAC_BCONFIG_PRIORITY_1_1 (0 << 14)

§ EMAC_BCONFIG_PRIORITY_2_1

#define EMAC_BCONFIG_PRIORITY_2_1 (1 << 14)

§ EMAC_BCONFIG_PRIORITY_3_1

#define EMAC_BCONFIG_PRIORITY_3_1 (2 << 14)

§ EMAC_BCONFIG_PRIORITY_4_1

#define EMAC_BCONFIG_PRIORITY_4_1 (3 << 14)

§ EMAC_BCONFIG_PRIORITY_FIXED

#define EMAC_BCONFIG_PRIORITY_FIXED 0x00000002

§ EMAC_BCONFIG_FIXED_BURST

#define EMAC_BCONFIG_FIXED_BURST 0x00010000

§ EMAC_BCONFIG_MIXED_BURST

#define EMAC_BCONFIG_MIXED_BURST 0x04000000

§ EMAC_PHY_TYPE_INTERNAL

#define EMAC_PHY_TYPE_INTERNAL 0x00000000

Referenced by EMACPHYConfigSet().

§ EMAC_PHY_TYPE_EXTERNAL_MII

#define EMAC_PHY_TYPE_EXTERNAL_MII 0x80000000

§ EMAC_PHY_TYPE_EXTERNAL_RMII

#define EMAC_PHY_TYPE_EXTERNAL_RMII 0xC0000000

Referenced by EMACPHYConfigSet().

§ EMAC_PHY_INT_NIB_TXERR_DET_DIS

#define EMAC_PHY_INT_NIB_TXERR_DET_DIS 0x01000000

§ EMAC_PHY_INT_RX_ER_DURING_IDLE

#define EMAC_PHY_INT_RX_ER_DURING_IDLE 0x00800000

§ EMAC_PHY_INT_ISOLATE_MII_LLOSS

#define EMAC_PHY_INT_ISOLATE_MII_LLOSS 0x00400000

§ EMAC_PHY_INT_LINK_LOSS_RECOVERY

#define EMAC_PHY_INT_LINK_LOSS_RECOVERY 0x00200000

§ EMAC_PHY_INT_TDRRUN

#define EMAC_PHY_INT_TDRRUN 0x00100000

§ EMAC_PHY_INT_LD_ON_RX_ERR_COUNT

#define EMAC_PHY_INT_LD_ON_RX_ERR_COUNT 0x00040000

§ EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT

#define EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT 0x00020000

§ EMAC_PHY_INT_LD_ON_LOW_SNR

#define EMAC_PHY_INT_LD_ON_LOW_SNR 0x00010000

§ EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY

#define EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY 0x00008000

§ EMAC_PHY_INT_POLARITY_SWAP

#define EMAC_PHY_INT_POLARITY_SWAP 0x00004000

§ EMAC_PHY_INT_MDI_SWAP

#define EMAC_PHY_INT_MDI_SWAP 0x00002000

§ EMAC_PHY_INT_ROBUST_MDIX

#define EMAC_PHY_INT_ROBUST_MDIX 0x00001000

§ EMAC_PHY_INT_FAST_MDIX

#define EMAC_PHY_INT_FAST_MDIX 0x00000800

§ EMAC_PHY_INT_MDIX_EN

#define EMAC_PHY_INT_MDIX_EN 0x00000400

§ EMAC_PHY_INT_FAST_RXDV_DETECT

#define EMAC_PHY_INT_FAST_RXDV_DETECT 0x00000200

§ EMAC_PHY_INT_FAST_L_UP_DETECT

#define EMAC_PHY_INT_FAST_L_UP_DETECT 0x00000100

§ EMAC_PHY_INT_EXT_FULL_DUPLEX

#define EMAC_PHY_INT_EXT_FULL_DUPLEX 0x00000080

§ EMAC_PHY_INT_FAST_AN_80_50_35

#define EMAC_PHY_INT_FAST_AN_80_50_35 0x00000040

§ EMAC_PHY_INT_FAST_AN_120_75_50

#define EMAC_PHY_INT_FAST_AN_120_75_50 0x00000050

§ EMAC_PHY_INT_FAST_AN_140_150_100

#define EMAC_PHY_INT_FAST_AN_140_150_100 0x00000060

§ EMAC_PHY_FORCE_10B_T_HALF_DUPLEX

#define EMAC_PHY_FORCE_10B_T_HALF_DUPLEX 0x00000000

§ EMAC_PHY_FORCE_10B_T_FULL_DUPLEX

#define EMAC_PHY_FORCE_10B_T_FULL_DUPLEX 0x00000002

§ EMAC_PHY_FORCE_100B_T_HALF_DUPLEX

#define EMAC_PHY_FORCE_100B_T_HALF_DUPLEX 0x00000004

§ EMAC_PHY_FORCE_100B_T_FULL_DUPLEX

#define EMAC_PHY_FORCE_100B_T_FULL_DUPLEX 0x00000006

§ EMAC_PHY_AN_10B_T_HALF_DUPLEX

#define EMAC_PHY_AN_10B_T_HALF_DUPLEX 0x00000008

§ EMAC_PHY_AN_10B_T_FULL_DUPLEX

#define EMAC_PHY_AN_10B_T_FULL_DUPLEX 0x0000000A

§ EMAC_PHY_AN_100B_T_HALF_DUPLEX

#define EMAC_PHY_AN_100B_T_HALF_DUPLEX 0x0000000C

§ EMAC_PHY_AN_100B_T_FULL_DUPLEX

#define EMAC_PHY_AN_100B_T_FULL_DUPLEX 0x0000000E

§ EMAC_PHY_INT_HOLD

#define EMAC_PHY_INT_HOLD 0x00000001

§ EMAC_PHY_TYPE_MASK

#define EMAC_PHY_TYPE_MASK 0xC0000000

Referenced by EMACPHYConfigSet().

§ EMAC_CONFIG_USE_MACADDR1

#define EMAC_CONFIG_USE_MACADDR1 0x40000000

§ EMAC_CONFIG_USE_MACADDR0

#define EMAC_CONFIG_USE_MACADDR0 0x00000000

§ EMAC_CONFIG_SA_FROM_DESCRIPTOR

#define EMAC_CONFIG_SA_FROM_DESCRIPTOR 0x00000000

§ EMAC_CONFIG_SA_INSERT

#define EMAC_CONFIG_SA_INSERT 0x20000000

§ EMAC_CONFIG_SA_REPLACE

#define EMAC_CONFIG_SA_REPLACE 0x30000000

§ EMAC_CONFIG_2K_PACKETS

#define EMAC_CONFIG_2K_PACKETS 0x08000000

§ EMAC_CONFIG_STRIP_CRC

#define EMAC_CONFIG_STRIP_CRC 0x02000000

§ EMAC_CONFIG_JABBER_DISABLE

#define EMAC_CONFIG_JABBER_DISABLE 0x00400000

§ EMAC_CONFIG_JUMBO_ENABLE

#define EMAC_CONFIG_JUMBO_ENABLE 0x00100000

§ EMAC_CONFIG_IF_GAP_MASK

#define EMAC_CONFIG_IF_GAP_MASK 0x000E0000

§ EMAC_CONFIG_IF_GAP_96BITS

#define EMAC_CONFIG_IF_GAP_96BITS (0x0 << 17)

§ EMAC_CONFIG_IF_GAP_88BITS

#define EMAC_CONFIG_IF_GAP_88BITS (0x1 << 17)

§ EMAC_CONFIG_IF_GAP_80BITS

#define EMAC_CONFIG_IF_GAP_80BITS (0x2 << 17)

§ EMAC_CONFIG_IF_GAP_72BITS

#define EMAC_CONFIG_IF_GAP_72BITS (0x3 << 17)

§ EMAC_CONFIG_IF_GAP_64BITS

#define EMAC_CONFIG_IF_GAP_64BITS (0x4 << 17)

§ EMAC_CONFIG_IF_GAP_56BITS

#define EMAC_CONFIG_IF_GAP_56BITS (0x5 << 17)

§ EMAC_CONFIG_IF_GAP_48BITS

#define EMAC_CONFIG_IF_GAP_48BITS (0x6 << 17)

§ EMAC_CONFIG_IF_GAP_40BITS

#define EMAC_CONFIG_IF_GAP_40BITS (0x7 << 17)

§ EMAC_CONFIG_CS_DISABLE

#define EMAC_CONFIG_CS_DISABLE 0x00010000

§ EMAC_CONFIG_100MBPS

#define EMAC_CONFIG_100MBPS 0x00004000

§ EMAC_CONFIG_10MBPS

#define EMAC_CONFIG_10MBPS 0x00000000

§ EMAC_CONFIG_RX_OWN_DISABLE

#define EMAC_CONFIG_RX_OWN_DISABLE 0x00002000

§ EMAC_CONFIG_LOOPBACK

#define EMAC_CONFIG_LOOPBACK 0x00001000

§ EMAC_CONFIG_FULL_DUPLEX

#define EMAC_CONFIG_FULL_DUPLEX 0x00000800

§ EMAC_CONFIG_HALF_DUPLEX

#define EMAC_CONFIG_HALF_DUPLEX 0x00000000

§ EMAC_CONFIG_CHECKSUM_OFFLOAD

#define EMAC_CONFIG_CHECKSUM_OFFLOAD 0x00000400

§ EMAC_CONFIG_RETRY_DISABLE

#define EMAC_CONFIG_RETRY_DISABLE 0x00000200

§ EMAC_CONFIG_AUTO_CRC_STRIPPING

#define EMAC_CONFIG_AUTO_CRC_STRIPPING 0x00000080

§ EMAC_CONFIG_BO_MASK

#define EMAC_CONFIG_BO_MASK 0x00000060

§ EMAC_CONFIG_BO_LIMIT_1024

#define EMAC_CONFIG_BO_LIMIT_1024 (0x0 << 5)

§ EMAC_CONFIG_BO_LIMIT_256

#define EMAC_CONFIG_BO_LIMIT_256 (0x1 << 5)

§ EMAC_CONFIG_BO_LIMIT_16

#define EMAC_CONFIG_BO_LIMIT_16 (0x2 << 5)

§ EMAC_CONFIG_BO_LIMIT_2

#define EMAC_CONFIG_BO_LIMIT_2 (0x3 << 5)

§ EMAC_CONFIG_DEFERRAL_CHK_ENABLE

#define EMAC_CONFIG_DEFERRAL_CHK_ENABLE 0x00000010

§ EMAC_CONFIG_PREAMBLE_MASK

#define EMAC_CONFIG_PREAMBLE_MASK 0x00000003

§ EMAC_CONFIG_7BYTE_PREAMBLE

#define EMAC_CONFIG_7BYTE_PREAMBLE 0x00000000

§ EMAC_CONFIG_5BYTE_PREAMBLE

#define EMAC_CONFIG_5BYTE_PREAMBLE 0x00000001

§ EMAC_CONFIG_3BYTE_PREAMBLE

#define EMAC_CONFIG_3BYTE_PREAMBLE 0x00000002

§ EMAC_MODE_KEEP_BAD_CRC

#define EMAC_MODE_KEEP_BAD_CRC 0x04000000

§ EMAC_MODE_RX_STORE_FORWARD

#define EMAC_MODE_RX_STORE_FORWARD 0x02000000

§ EMAC_MODE_RX_FLUSH_DISABLE

#define EMAC_MODE_RX_FLUSH_DISABLE 0x01000000

§ EMAC_MODE_TX_STORE_FORWARD

#define EMAC_MODE_TX_STORE_FORWARD 0x00200000

§ EMAC_MODE_TX_THRESHOLD_16_BYTES

#define EMAC_MODE_TX_THRESHOLD_16_BYTES (7 << 14)

§ EMAC_MODE_TX_THRESHOLD_24_BYTES

#define EMAC_MODE_TX_THRESHOLD_24_BYTES (6 << 14)

§ EMAC_MODE_TX_THRESHOLD_32_BYTES

#define EMAC_MODE_TX_THRESHOLD_32_BYTES (5 << 14)

§ EMAC_MODE_TX_THRESHOLD_40_BYTES

#define EMAC_MODE_TX_THRESHOLD_40_BYTES (4 << 14)

§ EMAC_MODE_TX_THRESHOLD_64_BYTES

#define EMAC_MODE_TX_THRESHOLD_64_BYTES (0 << 14)

§ EMAC_MODE_TX_THRESHOLD_128_BYTES

#define EMAC_MODE_TX_THRESHOLD_128_BYTES (1 << 14)

§ EMAC_MODE_TX_THRESHOLD_192_BYTES

#define EMAC_MODE_TX_THRESHOLD_192_BYTES (2 << 14)

§ EMAC_MODE_TX_THRESHOLD_256_BYTES

#define EMAC_MODE_TX_THRESHOLD_256_BYTES (3 << 14)

§ EMAC_MODE_RX_ERROR_FRAMES

#define EMAC_MODE_RX_ERROR_FRAMES 0x00000080

§ EMAC_MODE_RX_UNDERSIZED_FRAMES

#define EMAC_MODE_RX_UNDERSIZED_FRAMES 0x00000040

§ EMAC_MODE_RX_THRESHOLD_64_BYTES

#define EMAC_MODE_RX_THRESHOLD_64_BYTES (0 << 3)

§ EMAC_MODE_RX_THRESHOLD_32_BYTES

#define EMAC_MODE_RX_THRESHOLD_32_BYTES (1 << 3)

§ EMAC_MODE_RX_THRESHOLD_96_BYTES

#define EMAC_MODE_RX_THRESHOLD_96_BYTES (2 << 3)

§ EMAC_MODE_RX_THRESHOLD_128_BYTES

#define EMAC_MODE_RX_THRESHOLD_128_BYTES (3 << 3)

§ EMAC_MODE_OPERATE_2ND_FRAME

#define EMAC_MODE_OPERATE_2ND_FRAME 0x00000002

§ EMAC_CONFIG_TX_ENABLED

#define EMAC_CONFIG_TX_ENABLED 0x00000008

Referenced by EMACConfigGet(), and EMACConfigSet().

§ EMAC_CONFIG_RX_ENABLED

#define EMAC_CONFIG_RX_ENABLED 0x00000004

Referenced by EMACConfigGet(), and EMACConfigSet().

§ EMAC_MODE_TX_DMA_ENABLED

#define EMAC_MODE_TX_DMA_ENABLED 0x00002000

§ EMAC_MODE_RX_DMA_ENABLED

#define EMAC_MODE_RX_DMA_ENABLED 0x00000002

§ EMAC_FRMFILTER_RX_ALL

#define EMAC_FRMFILTER_RX_ALL 0x80000000

§ EMAC_FRMFILTER_VLAN

#define EMAC_FRMFILTER_VLAN 0x00010000

§ EMAC_FRMFILTER_HASH_AND_PERFECT

#define EMAC_FRMFILTER_HASH_AND_PERFECT 0x00000400

§ EMAC_FRMFILTER_SADDR

#define EMAC_FRMFILTER_SADDR 0x00000200

§ EMAC_FRMFILTER_INV_SADDR

#define EMAC_FRMFILTER_INV_SADDR 0x00000100

§ EMAC_FRMFILTER_PASS_MASK

#define EMAC_FRMFILTER_PASS_MASK (0x03 << 6)

§ EMAC_FRMFILTER_PASS_NO_CTRL

#define EMAC_FRMFILTER_PASS_NO_CTRL (0x00 << 6)

§ EMAC_FRMFILTER_PASS_NO_PAUSE

#define EMAC_FRMFILTER_PASS_NO_PAUSE (0x01 << 6)

§ EMAC_FRMFILTER_PASS_ALL_CTRL

#define EMAC_FRMFILTER_PASS_ALL_CTRL (0x02 << 6)

§ EMAC_FRMFILTER_PASS_ADDR_CTRL

#define EMAC_FRMFILTER_PASS_ADDR_CTRL (0x03 << 6)

§ EMAC_FRMFILTER_BROADCAST

#define EMAC_FRMFILTER_BROADCAST 0x00000020

§ EMAC_FRMFILTER_PASS_MULTICAST

#define EMAC_FRMFILTER_PASS_MULTICAST 0x00000010

§ EMAC_FRMFILTER_INV_DADDR

#define EMAC_FRMFILTER_INV_DADDR 0x00000008

§ EMAC_FRMFILTER_HASH_MULTICAST

#define EMAC_FRMFILTER_HASH_MULTICAST 0x00000004

§ EMAC_FRMFILTER_HASH_UNICAST

#define EMAC_FRMFILTER_HASH_UNICAST 0x00000002

§ EMAC_FRMFILTER_PROMISCUOUS

#define EMAC_FRMFILTER_PROMISCUOUS 0x00000001

§ EMAC_STATUS_TX_NOT_EMPTY

#define EMAC_STATUS_TX_NOT_EMPTY 0x01000000

§ EMAC_STATUS_TX_WRITING_FIFO

#define EMAC_STATUS_TX_WRITING_FIFO 0x00400000

§ EMAC_STATUS_TRC_STATE_MASK

#define EMAC_STATUS_TRC_STATE_MASK 0x00300000

§ EMAC_STATUS_TRC_STATE_IDLE

#define EMAC_STATUS_TRC_STATE_IDLE (0x00 << 20)

§ EMAC_STATUS_TRC_STATE_READING

#define EMAC_STATUS_TRC_STATE_READING (0x01 << 20)

§ EMAC_STATUS_TRC_STATE_WAITING

#define EMAC_STATUS_TRC_STATE_WAITING (0x02 << 20)

§ EMAC_STATUS_TRC_STATE_STATUS

#define EMAC_STATUS_TRC_STATE_STATUS (0x03 << 20)

§ EMAC_STATUS_TX_PAUSED

#define EMAC_STATUS_TX_PAUSED 0x00080000

§ EMAC_STATUS_TFC_STATE_MASK

#define EMAC_STATUS_TFC_STATE_MASK 0x00060000

§ EMAC_STATUS_TFC_STATE_IDLE

#define EMAC_STATUS_TFC_STATE_IDLE (0x00 << 17)

§ EMAC_STATUS_TFC_STATE_WAITING

#define EMAC_STATUS_TFC_STATE_WAITING (0x01 << 17)

§ EMAC_STATUS_TFC_STATE_PAUSING

#define EMAC_STATUS_TFC_STATE_PAUSING (0x02 << 17)

§ EMAC_STATUS_TFC_STATE_WRITING

#define EMAC_STATUS_TFC_STATE_WRITING (0x03 << 17)

§ EMAC_STATUS_MAC_NOT_IDLE

#define EMAC_STATUS_MAC_NOT_IDLE 0x00010000

§ EMAC_STATUS_RX_FIFO_LEVEL_MASK

#define EMAC_STATUS_RX_FIFO_LEVEL_MASK 0x00000300

Referenced by EMACWoLEnter().

§ EMAC_STATUS_RX_FIFO_EMPTY

#define EMAC_STATUS_RX_FIFO_EMPTY (0x00 << 8)

Referenced by EMACWoLEnter().

§ EMAC_STATUS_RX_FIFO_BELOW

#define EMAC_STATUS_RX_FIFO_BELOW (0x01 << 8)

§ EMAC_STATUS_RX_FIFO_ABOVE

#define EMAC_STATUS_RX_FIFO_ABOVE (0x02 << 8)

§ EMAC_STATUS_RX_FIFO_FULL

#define EMAC_STATUS_RX_FIFO_FULL (0x03 << 8)

§ EMAC_STATUS_RX_FIFO_STATE_MASK

#define EMAC_STATUS_RX_FIFO_STATE_MASK 0x00000060

§ EMAC_STATUS_RX_FIFO_IDLE

#define EMAC_STATUS_RX_FIFO_IDLE (0x00 << 5)

§ EMAC_STATUS_RX_FIFO_READING

#define EMAC_STATUS_RX_FIFO_READING (0x01 << 5)

§ EMAC_STATUS_RX_FIFO_STATUS

#define EMAC_STATUS_RX_FIFO_STATUS (0x02 << 5)

§ EMAC_STATUS_RX_FIFO_FLUSHING

#define EMAC_STATUS_RX_FIFO_FLUSHING (0x03 << 5)

§ EMAC_STATUS_RWC_ACTIVE

#define EMAC_STATUS_RWC_ACTIVE 0x00000010

§ EMAC_STATUS_RPE_ACTIVE

#define EMAC_STATUS_RPE_ACTIVE 0x00000001

§ EMAC_DMA_TXSTAT_MASK

#define EMAC_DMA_TXSTAT_MASK (0x07 << 20)

§ EMAC_DMA_TXSTAT_STOPPED

#define EMAC_DMA_TXSTAT_STOPPED (0x00 << 20)

§ EMAC_DMA_TXSTAT_RUN_FETCH_DESC

#define EMAC_DMA_TXSTAT_RUN_FETCH_DESC (0x01 << 20)

§ EMAC_DMA_TXSTAT_RUN_WAIT_STATUS

#define EMAC_DMA_TXSTAT_RUN_WAIT_STATUS (0x02 << 20)

§ EMAC_DMA_TXSTAT_RUN_READING

#define EMAC_DMA_TXSTAT_RUN_READING (0x03 << 20)

§ EMAC_DMA_TXSTAT_RUN_CLOSE_DESC

#define EMAC_DMA_TXSTAT_RUN_CLOSE_DESC (0x07 << 20)

§ EMAC_DMA_TXSTAT_TS_WRITE

#define EMAC_DMA_TXSTAT_TS_WRITE (0x04 << 20)

§ EMAC_DMA_TXSTAT_SUSPENDED

#define EMAC_DMA_TXSTAT_SUSPENDED (0x06 << 20)

§ EMAC_DMA_RXSTAT_MASK

#define EMAC_DMA_RXSTAT_MASK (0x07 << 17)

§ EMAC_DMA_RXSTAT_STOPPED

#define EMAC_DMA_RXSTAT_STOPPED (0x00 << 17)

§ EMAC_DMA_RXSTAT_RUN_FETCH_DESC

#define EMAC_DMA_RXSTAT_RUN_FETCH_DESC (0x01 << 17)

§ EMAC_DMA_RXSTAT_RUN_WAIT_PACKET

#define EMAC_DMA_RXSTAT_RUN_WAIT_PACKET (0x03 << 17)

§ EMAC_DMA_RXSTAT_SUSPENDED

#define EMAC_DMA_RXSTAT_SUSPENDED (0x04 << 17)

§ EMAC_DMA_RXSTAT_RUN_CLOSE_DESC

#define EMAC_DMA_RXSTAT_RUN_CLOSE_DESC (0x05 << 17)

§ EMAC_DMA_RXSTAT_TS_WRITE

#define EMAC_DMA_RXSTAT_TS_WRITE (0x06 << 17)

§ EMAC_DMA_RXSTAT_RUN_RECEIVING

#define EMAC_DMA_RXSTAT_RUN_RECEIVING (0x07 << 17)

§ EMAC_TX_DMA_STATE

#define EMAC_TX_DMA_STATE ( x ) ((x) & EMAC_DMA_TXSTAT_MASK)

§ EMAC_RX_DMA_STATE

#define EMAC_RX_DMA_STATE ( x ) ((x) & EMAC_DMA_RXSTAT_MASK)

§ EMAC_DMA_ERROR

#define EMAC_DMA_ERROR 0x00002000

§ EMAC_DMA_ERR_MASK

#define EMAC_DMA_ERR_MASK 0x03800000

§ EMAC_DMA_ERR_RX_DATA_WRITE

#define EMAC_DMA_ERR_RX_DATA_WRITE 0x00000000

§ EMAC_DMA_ERR_TX_DATA_READ

#define EMAC_DMA_ERR_TX_DATA_READ 0x01800000

§ EMAC_DMA_ERR_RX_DESC_WRITE

#define EMAC_DMA_ERR_RX_DESC_WRITE 0x02000000

§ EMAC_DMA_ERR_TX_DESC_WRITE

#define EMAC_DMA_ERR_TX_DESC_WRITE 0x02800000

§ EMAC_DMA_ERR_RX_DESC_READ

#define EMAC_DMA_ERR_RX_DESC_READ 0x03000000

§ EMAC_DMA_ERR_TX_DESC_READ

#define EMAC_DMA_ERR_TX_DESC_READ 0x03800000

§ EMAC_FILTER_ADDR_ENABLE

#define EMAC_FILTER_ADDR_ENABLE 0x80000000

Referenced by EMACAddrFilterGet(), and EMACAddrFilterSet().

§ EMAC_FILTER_SOURCE_ADDR

#define EMAC_FILTER_SOURCE_ADDR 0x40000000

Referenced by EMACAddrFilterGet(), and EMACAddrFilterSet().

§ EMAC_FILTER_MASK_BYTE_6

#define EMAC_FILTER_MASK_BYTE_6 0x20000000

§ EMAC_FILTER_MASK_BYTE_5

#define EMAC_FILTER_MASK_BYTE_5 0x10000000

§ EMAC_FILTER_MASK_BYTE_4

#define EMAC_FILTER_MASK_BYTE_4 0x08000000

§ EMAC_FILTER_MASK_BYTE_3

#define EMAC_FILTER_MASK_BYTE_3 0x04000000

§ EMAC_FILTER_MASK_BYTE_2

#define EMAC_FILTER_MASK_BYTE_2 0x03000000

§ EMAC_FILTER_MASK_BYTE_1

#define EMAC_FILTER_MASK_BYTE_1 0x01000000

§ EMAC_FILTER_BYTE_MASK_M

#define EMAC_FILTER_BYTE_MASK_M 0x3F000000

Referenced by EMACAddrFilterGet(), and EMACAddrFilterSet().

§ EMAC_FILTER_BYTE_MASK_S

#define EMAC_FILTER_BYTE_MASK_S 24

§ EMAC_TS_MAC_FILTER_ENABLE

#define EMAC_TS_MAC_FILTER_ENABLE 0x00040000

§ EMAC_TS_MAC_FILTER_DISABLE

#define EMAC_TS_MAC_FILTER_DISABLE 0x00000000

§ EMAC_TS_SYNC_FOLLOW_DREQ_DRESP

#define EMAC_TS_SYNC_FOLLOW_DREQ_DRESP 0x00000000

§ EMAC_TS_SYNC_ONLY

#define EMAC_TS_SYNC_ONLY 0x00004000

§ EMAC_TS_DELAYREQ_ONLY

#define EMAC_TS_DELAYREQ_ONLY 0x0000C000

§ EMAC_TS_ALL

#define EMAC_TS_ALL 0x00010000

§ EMAC_TS_SYNC_PDREQ_PDRESP

#define EMAC_TS_SYNC_PDREQ_PDRESP 0x00014000

§ EMAC_TS_DREQ_PDREQ_PDRESP

#define EMAC_TS_DREQ_PDREQ_PDRESP 0x0001C000

§ EMAC_TS_SYNC_DELAYREQ

#define EMAC_TS_SYNC_DELAYREQ 0x00020000

§ EMAC_TS_PDREQ_PDRESP

#define EMAC_TS_PDREQ_PDRESP 0x00030000

§ EMAC_TS_PROCESS_IPV4_UDP

#define EMAC_TS_PROCESS_IPV4_UDP 0x00002000

§ EMAC_TS_PROCESS_IPV6_UDP

#define EMAC_TS_PROCESS_IPV6_UDP 0x00001000

§ EMAC_TS_PROCESS_ETHERNET

#define EMAC_TS_PROCESS_ETHERNET 0x00000800

§ EMAC_TS_PTP_VERSION_2

#define EMAC_TS_PTP_VERSION_2 0x00000400

§ EMAC_TS_PTP_VERSION_1

#define EMAC_TS_PTP_VERSION_1 0x00000000

§ EMAC_TS_DIGITAL_ROLLOVER

#define EMAC_TS_DIGITAL_ROLLOVER 0x00000200

Referenced by EMACTimestampPPSSimpleModeSet().

§ EMAC_TS_BINARY_ROLLOVER

#define EMAC_TS_BINARY_ROLLOVER 0x00000000

§ EMAC_TS_ALL_RX_FRAMES

#define EMAC_TS_ALL_RX_FRAMES 0x00000100

§ EMAC_TS_UPDATE_FINE

#define EMAC_TS_UPDATE_FINE 0x00000002

§ EMAC_TS_UPDATE_COARSE

#define EMAC_TS_UPDATE_COARSE 0x00000000

§ EPHY_SCR_INPOL_EXT

#define EPHY_SCR_INPOL_EXT 0x00000008

§ EPHY_SCR_TINT_EXT

#define EPHY_SCR_TINT_EXT 0x00000004

§ EPHY_SCR_INTEN_EXT

#define EPHY_SCR_INTEN_EXT 0x00000002

§ EPHY_SCR_INTOE_EXT

#define EPHY_SCR_INTOE_EXT 0x00000001

§ EMAC_INT_PHY

#define EMAC_INT_PHY 0x80000000

Referenced by EMACIntClear(), EMACIntDisable(), EMACIntEnable(), and EMACIntStatus().

§ EMAC_INT_EARLY_RECEIVE

#define EMAC_INT_EARLY_RECEIVE 0x00004000

§ EMAC_INT_BUS_ERROR

#define EMAC_INT_BUS_ERROR 0x00002000

§ EMAC_INT_EARLY_TRANSMIT

#define EMAC_INT_EARLY_TRANSMIT 0x00000400

§ EMAC_INT_RX_WATCHDOG

#define EMAC_INT_RX_WATCHDOG 0x00000200

§ EMAC_INT_RX_STOPPED

#define EMAC_INT_RX_STOPPED 0x00000100

§ EMAC_INT_RX_NO_BUFFER

#define EMAC_INT_RX_NO_BUFFER 0x00000080

§ EMAC_INT_RECEIVE

#define EMAC_INT_RECEIVE 0x00000040

§ EMAC_INT_TX_UNDERFLOW

#define EMAC_INT_TX_UNDERFLOW 0x00000020

§ EMAC_INT_RX_OVERFLOW

#define EMAC_INT_RX_OVERFLOW 0x00000010

§ EMAC_INT_TX_JABBER

#define EMAC_INT_TX_JABBER 0x00000008

§ EMAC_INT_TX_NO_BUFFER

#define EMAC_INT_TX_NO_BUFFER 0x00000004

§ EMAC_INT_TX_STOPPED

#define EMAC_INT_TX_STOPPED 0x00000002

§ EMAC_INT_TRANSMIT

#define EMAC_INT_TRANSMIT 0x00000001

§ EMAC_INT_NORMAL_INT

#define EMAC_INT_NORMAL_INT 0x00010000

Referenced by EMACIntClear(), EMACIntDisable(), and EMACIntEnable().

§ EMAC_INT_ABNORMAL_INT

#define EMAC_INT_ABNORMAL_INT 0x00008000

Referenced by EMACIntClear(), EMACIntDisable(), and EMACIntEnable().

§ EMAC_INT_LPI

#define EMAC_INT_LPI 0x40000000

§ EMAC_INT_TIMESTAMP

#define EMAC_INT_TIMESTAMP 0x20000000

§ EMAC_TS_INT_TARGET_REACHED

#define EMAC_TS_INT_TARGET_REACHED 0x00000002

§ EMAC_TS_INT_TS_SEC_OVERFLOW

#define EMAC_TS_INT_TS_SEC_OVERFLOW 0x00000001

§ EMAC_INT_POWER_MGMNT

#define EMAC_INT_POWER_MGMNT 0x10000000

§ EMAC_PPS_SINGLE_PULSE

#define EMAC_PPS_SINGLE_PULSE 0x00000000

Referenced by EMACTimestampPPSSimpleModeSet().

§ EMAC_PPS_1HZ

#define EMAC_PPS_1HZ 0x00000001

Referenced by EMACTimestampPPSSimpleModeSet().

§ EMAC_PPS_2HZ

#define EMAC_PPS_2HZ 0x00000002

§ EMAC_PPS_4HZ

#define EMAC_PPS_4HZ 0x00000003

§ EMAC_PPS_8HZ

#define EMAC_PPS_8HZ 0x00000004

§ EMAC_PPS_16HZ

#define EMAC_PPS_16HZ 0x00000005

§ EMAC_PPS_32HZ

#define EMAC_PPS_32HZ 0x00000006

§ EMAC_PPS_64HZ

#define EMAC_PPS_64HZ 0x00000007

§ EMAC_PPS_128HZ

#define EMAC_PPS_128HZ 0x00000008

§ EMAC_PPS_256HZ

#define EMAC_PPS_256HZ 0x00000009

§ EMAC_PPS_512HZ

#define EMAC_PPS_512HZ 0x0000000A

§ EMAC_PPS_1024HZ

#define EMAC_PPS_1024HZ 0x0000000B

§ EMAC_PPS_2048HZ

#define EMAC_PPS_2048HZ 0x0000000C

§ EMAC_PPS_4096HZ

#define EMAC_PPS_4096HZ 0x0000000D

§ EMAC_PPS_8192HZ

#define EMAC_PPS_8192HZ 0x0000000E

§ EMAC_PPS_16384HZ

#define EMAC_PPS_16384HZ 0x0000000F

§ EMAC_PPS_32768HZ

#define EMAC_PPS_32768HZ 0x00000010

Referenced by EMACTimestampPPSSimpleModeSet().

§ EMAC_PPS_TARGET_INT

#define EMAC_PPS_TARGET_INT 0x00000000

Referenced by EMACTimestampPPSCommandModeSet().

§ EMAC_PPS_TARGET_PPS

#define EMAC_PPS_TARGET_PPS 0x00000060

Referenced by EMACTimestampPPSCommandModeSet().

§ EMAC_PPS_TARGET_BOTH

#define EMAC_PPS_TARGET_BOTH 0x00000040

Referenced by EMACTimestampPPSCommandModeSet().

§ EMAC_PPS_COMMAND_NONE

#define EMAC_PPS_COMMAND_NONE 0x00

§ EMAC_PPS_COMMAND_START_SINGLE

#define EMAC_PPS_COMMAND_START_SINGLE 0x01

§ EMAC_PPS_COMMAND_START_TRAIN

#define EMAC_PPS_COMMAND_START_TRAIN 0x02

§ EMAC_PPS_COMMAND_CANCEL_START

#define EMAC_PPS_COMMAND_CANCEL_START 0x03

§ EMAC_PPS_COMMAND_STOP_AT_TIME

#define EMAC_PPS_COMMAND_STOP_AT_TIME 0x04

§ EMAC_PPS_COMMAND_STOP_NOW

#define EMAC_PPS_COMMAND_STOP_NOW 0x05

§ EMAC_PPS_COMMAND_CANCEL_STOP

#define EMAC_PPS_COMMAND_CANCEL_STOP 0x06

§ EMAC_VLAN_RX_HASH_ENABLE

#define EMAC_VLAN_RX_HASH_ENABLE 0x00080000

§ EMAC_VLAN_RX_HASH_DISABLE

#define EMAC_VLAN_RX_HASH_DISABLE 0x00000000

§ EMAC_VLAN_RX_SVLAN_ENABLE

#define EMAC_VLAN_RX_SVLAN_ENABLE 0x00040000

§ EMAC_VLAN_RX_SVLAN_DISABLE

#define EMAC_VLAN_RX_SVLAN_DISABLE 0x00000000

§ EMAC_VLAN_RX_NORMAL_MATCH

#define EMAC_VLAN_RX_NORMAL_MATCH 0x00000000

§ EMAC_VLAN_RX_INVERSE_MATCH

#define EMAC_VLAN_RX_INVERSE_MATCH 0x00020000

§ EMAC_VLAN_RX_12BIT_TAG

#define EMAC_VLAN_RX_12BIT_TAG 0x00010000

§ EMAC_VLAN_RX_16BIT_TAG

#define EMAC_VLAN_RX_16BIT_TAG 0x00000000

§ EMAC_VLAN_TX_CVLAN

#define EMAC_VLAN_TX_CVLAN 0x00000000

§ EMAC_VLAN_TX_SVLAN

#define EMAC_VLAN_TX_SVLAN 0x00080000

§ EMAC_VLAN_TX_USE_VLC

#define EMAC_VLAN_TX_USE_VLC 0x00040000

§ EMAC_VLAN_TX_VLC_NONE

#define EMAC_VLAN_TX_VLC_NONE 0x00000000

§ EMAC_VLAN_TX_VLC_DELETE

#define EMAC_VLAN_TX_VLC_DELETE 0x00010000

§ EMAC_VLAN_TX_VLC_INSERT

#define EMAC_VLAN_TX_VLC_INSERT 0x00020000

§ EMAC_VLAN_TX_VLC_REPLACE

#define EMAC_VLAN_TX_VLC_REPLACE 0x00030000

§ EMAC_VLAN_TX_VLC_MASK

#define EMAC_VLAN_TX_VLC_MASK 0x00030000

§ EMAC_RWU_FILTER_ENABLE

#define EMAC_RWU_FILTER_ENABLE 1

§ EMAC_RWU_FILTER_DISABLE

#define EMAC_RWU_FILTER_DISABLE 0

§ EMAC_RWU_FILTER_MULTICAST

#define EMAC_RWU_FILTER_MULTICAST 8

§ EMAC_RWU_FILTER_UNICAST

#define EMAC_RWU_FILTER_UNICAST 0

§ EMAC_PMT_GLOBAL_UNICAST_ENABLE

#define EMAC_PMT_GLOBAL_UNICAST_ENABLE 0x00000200

Referenced by EMACPowerManagementControlSet().

§ EMAC_PMT_WAKEUP_PACKET_ENABLE

#define EMAC_PMT_WAKEUP_PACKET_ENABLE 0x00000004

Referenced by EMACPowerManagementControlSet().

§ EMAC_PMT_MAGIC_PACKET_ENABLE

#define EMAC_PMT_MAGIC_PACKET_ENABLE 0x00000002

Referenced by EMACPowerManagementControlSet().

§ EMAC_PMT_POWER_DOWN

#define EMAC_PMT_POWER_DOWN 0x00000001

Referenced by EMACPowerManagementControlSet().

§ EMAC_PMT_WAKEUP_PACKET_RECEIVED

#define EMAC_PMT_WAKEUP_PACKET_RECEIVED 0x00000040

§ EMAC_PMT_MAGIC_PACKET_RECEIVED

#define EMAC_PMT_MAGIC_PACKET_RECEIVED 0x00000020

Typedef Documentation

§ tEMACDMADescriptor

typedef struct tEMACDMADescriptor tEMACDMADescriptor

Function Documentation

§ EMACInit()

void EMACInit	(	uint32_t	ui32Base,
		uint32_t	ui32SysClk,
		uint32_t	ui32BusConfig,
		uint32_t	ui32RxBurst,
		uint32_t	ui32TxBurst,
		uint32_t	ui32DescSkipSize
	)

Initializes the Ethernet MAC and sets bus-related DMA parameters.

Parameters

ui32Base	is the base address of the Ethernet controller.
ui32SysClk	is the current system clock frequency in Hertz.
ui32BusConfig	defines the bus operating mode for the Ethernet MAC DMA controller.
ui32RxBurst	is the maximum receive burst size in words.
ui32TxBurst	is the maximum transmit burst size in words.
ui32DescSkipSize	is the number of 32-bit words to skip between two unchained DMA descriptors. Values in the range 0 to 31 are valid.

This function sets bus-related parameters for the Ethernet MAC DMA engines. It must be called after EMACPHYConfigSet() and called again after any subsequent call to EMACPHYConfigSet().

The ui32BusConfig parameter is the logical OR of various fields. The first sets the DMA channel priority weight:

EMAC_BCONFIG_DMA_PRIO_WEIGHT_1
EMAC_BCONFIG_DMA_PRIO_WEIGHT_2
EMAC_BCONFIG_DMA_PRIO_WEIGHT_3
EMAC_BCONFIG_DMA_PRIO_WEIGHT_4

The second field sets the receive and transmit priorities used when arbitrating between the Rx and Tx DMA. The priorities are Rx:Tx unless EMAC_BCONFIG_TX_PRIORITY is also specified, in which case they become Tx:Rx. The priority provided here is ignored if EMAC_BCONFIG_PRIORITY_FIXED is specified.

EMAC_BCONFIG_PRIORITY_1_1
EMAC_BCONFIG_PRIORITY_2_1
EMAC_BCONFIG_PRIORITY_3_1
EMAC_BCONFIG_PRIORITY_4_1

The following additional flags may also be defined:

EMAC_BCONFIG_TX_PRIORITY indicates that the transmit DMA should be higher priority in all arbitration for the system-side bus. If this is not defined, the receive DMA has higher priority.
EMAC_BCONFIG_ADDR_ALIGNED works in tandem with EMAC_BCONFIG_FIXED_BURST to control address alignment of AHB bursts. When both flags are specified, all bursts are aligned to the start address least significant bits. If EMAC_BCONFIG_FIXED_BURST is not specified, the first burst is unaligned but subsequent bursts are aligned to the address.
EMAC_BCONFIG_ALT_DESCRIPTORS indicates that the DMA engine should use the alternate descriptor format as defined in type tEMACDMADescriptor. If absent, the basic descriptor type is used. Alternate descriptors are required if using IEEE 1588-2008 advanced timestamping, VLAN or TCP/UDP/ICMP CRC insertion features. Note that, for clarity, emac.h does not contain type definitions for the basic descriptor type. Please see the technical reference manual/datasheet for information on basic descriptor structures.
EMAC_BCONFIG_PRIORITY_FIXED indicates that a fixed priority scheme should be employed when arbitrating between the transmit and receive DMA for system-side bus access. In this case, the receive channel always has priority unless EMAC_BCONFIG_TX_PRIORITY is set, in which case the transmit channel has priority. If EMAC_BCONFIG_PRIORITY_FIXED is not specified, a weighted round-robin arbitration scheme is used with the weighting defined using EMAC_BCONFIG_PRIORITY_1_1, EMAC_BCONFIG_PRIORITY_2_1, EMAC_BCONFIG_PRIORITY_3_1 or EMAC_BCONFIG_PRIORITY_4_1, and EMAC_BCONFIG_TX_PRIORITY.
EMAC_BCONFIG_FIXED_BURST indicates that fixed burst transfers should be used.
EMAC_BCONFIG_MIXED_BURST indicates that the DMA engine should use mixed burst types depending on the length of data to be transferred across the system bus.

The ui32RxBurst and ui32TxBurst parameters indicate the maximum number of words that the relevant DMA should transfer in a single transaction. Valid values are 1, 2, 4, 8, 16 and 32. Any other value results in undefined behavior.

The ui32DescSkipSize parameter is used when the descriptor lists are using ring mode (where descriptors are contiguous in memory with the last descriptor marked with the END_OF_RING flag) rather than chained mode (where each descriptor includes a field that points to the next descriptor in the list). In ring mode, the hardware uses the ui32DescSkipSize to skip past any application-defined fields after the end of the hardware- defined descriptor fields. The parameter value indicates the number of 32-bit words to skip after the last field of the hardware-defined descriptor to get to the first field of the next descriptor. When using arrays of either the tEMACDMADescriptor or tEMACAltDMADescriptor types defined for this driver, ui32DescSkipSize must be set to 1 to skip the pvNext pointer added to the end of each of these structures. Applications may modify these structure definitions to include their own application-specific data and modify ui32DescSkipSize appropriately if desired.

Returns: None.

References ASSERT, EMAC_DMABUSMOD_8XPBL, EMAC_DMABUSMOD_ATDS, EMAC_DMABUSMOD_DSL_S, EMAC_DMABUSMOD_PBL_S, EMAC_DMABUSMOD_RPBL_S, EMAC_DMABUSMOD_SWR, EMAC_DMABUSMOD_USP, EMAC_O_DMABUSMOD, and HWREG.

§ EMACReset()

void EMACReset ( uint32_t ui32Base )

Resets the Ethernet MAC.

Parameters

ui32Base is the base address of the Ethernet controller.

This function performs a reset of the Ethernet MAC by resetting all logic and returning all registers to their default values. The function returns only after the hardware indicates that the reset has completed.

Note: To ensure that the reset completes, the selected PHY clock must be enabled when this function is called. If the PHY clock is absent, this function does not return.

Returns: None.

References EMAC_DMABUSMOD_SWR, EMAC_O_DMABUSMOD, and HWREG.

Referenced by EMACPHYConfigSet().

§ EMACPHYConfigSet()

void EMACPHYConfigSet	(	uint32_t	ui32Base,
		uint32_t	ui32Config
	)

Selects the Ethernet PHY in use.

Parameters

ui32Base	is the base address of the Ethernet controller.
ui32Config	selects the PHY in use and, when using the internal PHY, allows various various PHY parameters to be configured.

This function must be called prior to EMACInit() and EMACConfigSet() to select the Ethernet PHY to be used. If the internal PHY is selected, the function also allows configuration of various PHY parameters. Note that the Ethernet MAC is reset during this function call because parameters used by this function are latched by the hardware only on a MAC reset. The call sequence to select and configure the PHY, therefore, must be as follows:

//!     // Enable and reset the MAC.
//!     SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
//!     SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
//!     if(<using internal PHY>)
//!     {
//!         // Enable and reset the internal PHY.
//!         SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
//!         SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
//!     }
//!
//!     // Ensure the MAC is completed its reset.
//!     while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0))
//!     {
//!     }
//!
//!     // Set the PHY type and configuration options.
//!     EMACPHYConfigSet(EMAC0_BASE, <config>);
//!
//!     // Initialize and configure the MAC.
//!     EMACInit(EMAC0_BASE, <system clock rate>, <bus config>,
//!              <Rx burst size>, <Tx burst size>, <desc skip>);
//!     EMACConfigSet(EMAC0_BASE, <parameters>);
//!

The \e ui32Config parameter must specify one of the following values:

- \b EMAC_PHY_TYPE_INTERNAL selects the internal Ethernet PHY.
- \b EMAC_PHY_TYPE_EXTERNAL_MII selects an external PHY connected via the
MII interface.
- \b EMAC_PHY_TYPE_EXTERNAL_RMII selects an external PHY connected via the
RMII interface.

If \b EMAC_PHY_TYPE_INTERNAL is selected, the following flags may be ORed
into \e ui32Config to control various PHY features and modes.  These flags
are ignored if an external PHY is selected.

- \b EMAC_PHY_INT_NIB_TXERR_DET_DIS disables odd nibble transmit error
detection (sets the default value of PHY register MR10, bit 1).
- \b EMAC_PHY_INT_RX_ER_DURING_IDLE enables receive error detection during
idle  (sets the default value of PHY register MR10, bit 2).
- \b EMAC_PHY_INT_ISOLATE_MII_LLOSS ties the MII outputs low if no link is
established in 100B-T and full duplex modes (sets the default value of PHY
register MR10, bit 3).
- \b EMAC_PHY_INT_LINK_LOSS_RECOVERY enables link loss recovery (sets the
default value of PHY register MR9, bit 7).
- \b EMAC_PHY_INT_TDRRUN enables execution of the TDR procedure after a link
down event (sets the default value of PHY register MR9, bit 8).
- \b EMAC_PHY_INT_LD_ON_RX_ERR_COUNT enables link down if the receiver
error count reaches 32 within a 10-us interval (sets the default value of
PHY register MR11 bit 3).
- \b EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT enables link down if the MTL3 error
count reaches 20 in a 10 us-interval (sets the default value of PHY register
MR11 bit 2).
- \b EMAC_PHY_INT_LD_ON_LOW_SNR enables link down if the low SNR threshold
is crossed 20 times in a 10 us-interval (sets the default value of PHY
register MR11 bit 1).
- \b EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY enables link down if energy detector
indicates Energy Loss (sets the default value of PHY register MR11 bit 0).
- \b EMAC_PHY_INT_POLARITY_SWAP inverts the polarity on both TPTD and TPRD
pairs (sets the default value of PHY register MR11 bit 5).
- \b EMAC_PHY_INT_MDI_SWAP swaps the MDI pairs putting receive on the TPTD
pair and transmit on TPRD (sets the default value of PHY register MR11 bit
6).
- \b EMAC_PHY_INT_ROBUST_MDIX enables robust auto MDI-X resolution (sets the
default value of PHY register MR9 bit 5).
- \b EMAC_PHY_INT_FAST_MDIX enables fast auto-MDI/MDIX resolution (sets the
default value of PHY register MR9 bit 6).
- \b EMAC_PHY_INT_MDIX_EN enables auto-MDI/MDIX crossover (sets the
default value of PHY register MR9 bit 14).
- \b EMAC_PHY_INT_FAST_RXDV_DETECT enables fast RXDV detection (set the
default value of PHY register MR9 bit 1).
- \b EMAC_PHY_INT_FAST_L_UP_DETECT enables fast link-up time during parallel
detection (sets the default value of PHY register MR10 bit 6)
- \b EMAC_PHY_INT_EXT_FULL_DUPLEX forces full-duplex while working with a
link partner in forced 100B-TX (sets the default value of PHY register
MR10 bit 5).
- \b EMAC_PHY_INT_FAST_AN_80_50_35 enables fast auto-negotiation using
break link, link fail inhibit and wait timers set to 80, 50 and 35
respectively (sets the default value of PHY register MR9 bits [4:2] to
3b100).
- \b EMAC_PHY_INT_FAST_AN_120_75_50 enables fast auto-negotiation using
break link, link fail inhibit and wait timers set to 120, 75 and 50
respectively (sets the default value of PHY register MR9 bits [4:2] to
3b101).
- \b EMAC_PHY_INT_FAST_AN_140_150_100 enables fast auto-negotiation using
break link, link fail inhibit and wait timers set to 140, 150 and 100
respectively (sets the default value of PHY register MR9 bits [4:2] to
3b110).
- \b EMAC_PHY_FORCE_10B_T_HALF_DUPLEX disables auto-negotiation and forces
operation in 10Base-T, half duplex mode (sets the default value of PHY
register MR9 bits [13:11] to 3b000).
- \b EMAC_PHY_FORCE_10B_T_FULL_DUPLEX disables auto-negotiation and forces
operation in 10Base-T, full duplex mode (sets the default value of PHY
register MR9 bits [13:11] to 3b001).
- \b EMAC_PHY_FORCE_100B_T_HALF_DUPLEX disables auto-negotiation and forces
operation in 100Base-T, half duplex mode (sets the default value of PHY
register MR9 bits [13:11] to 3b010).
- \b EMAC_PHY_FORCE_100B_T_FULL_DUPLEX disables auto-negotiation and forces
operation in 100Base-T, full duplex mode (sets the default value of PHY
register MR9 bits [13:11] to 3b011).
- \b EMAC_PHY_AN_10B_T_HALF_DUPLEX enables auto-negotiation and advertises
10Base-T, half duplex mode (sets the default value of PHY register MR9 bits
[13:11] to 3b100).
- \b EMAC_PHY_AN_10B_T_FULL_DUPLEX enables auto-negotiation and advertises
10Base-T half or full duplex modes (sets the default value of PHY register
MR9 bits [13:11] to 3b101).
- \b EMAC_PHY_AN_100B_T_HALF_DUPLEX enables auto-negotiation and advertises
10Base-T half or full duplex, and 100Base-T half duplex modes (sets the
default value of PHY register MR9 bits [13:11] to 3b110).
- \b EMAC_PHY_AN_100B_T_FULL_DUPLEX enables auto-negotiation and advertises
10Base-T half or full duplex, and 100Base-T half or full duplex modes (sets
the default value of PHY register MR9 bits [13:11] to 3b111).
- \b EMAC_PHY_INT_HOLD prevents the PHY from transmitting energy on the
line.

As a side effect of this function, the Ethernet MAC is reset so any
previous MAC configuration is lost.

\return None.

References EMAC_CC_CLKEN, EMAC_O_CC, EMAC_O_PC, EMAC_PHY_TYPE_EXTERNAL_RMII, EMAC_PHY_TYPE_INTERNAL, EMAC_PHY_TYPE_MASK, EMACReset(), HWREG, SYSCTL_PERIPH_EPHY0, SysCtlDelay(), SysCtlPeripheralReady(), and SysCtlPeripheralReset().

§ EMACConfigSet()

void EMACConfigSet	(	uint32_t	ui32Base,
		uint32_t	ui32Config,
		uint32_t	ui32ModeFlags,
		uint32_t	ui32RxMaxFrameSize
	)

Configures basic Ethernet MAC operation parameters.

Parameters

ui32Base	is the base address of the Ethernet controller.
ui32Config	provides various flags and values configuring the MAC.
ui32ModeFlags	provides configuration relating to the transmit and receive DMA engines.
ui32RxMaxFrameSize	sets the maximum receive frame size above which an error is reported.

This function is called to configure basic operating parameters for the MAC and its DMA engines.

The ui32Config parameter is the logical OR of various fields and flags. The first field determines which MAC address is used during insertion or replacement for all transmitted frames. Valid options are

EMAC_CONFIG_USE_MACADDR1 and
EMAC_CONFIG_USE_MACADDR0

The interframe gap between transmitted frames is controlled using one of the following values:

EMAC_CONFIG_IF_GAP_96BITS
EMAC_CONFIG_IF_GAP_88BITS
EMAC_CONFIG_IF_GAP_80BITS
EMAC_CONFIG_IF_GAP_72BITS
EMAC_CONFIG_IF_GAP_64BITS
EMAC_CONFIG_IF_GAP_56BITS
EMAC_CONFIG_IF_GAP_48BITS
EMAC_CONFIG_IF_GAP_40BITS

The number of bytes of preamble added to the beginning of every transmitted frame is selected using one of the following values:

EMAC_CONFIG_7BYTE_PREAMBLE
EMAC_CONFIG_5BYTE_PREAMBLE
EMAC_CONFIG_3BYTE_PREAMBLE

The back-off limit determines the range of the random time that the MAC delays after a collision and before attempting to retransmit a frame. One of the following values must be used to select this limit. In each case, the retransmission delay in terms of 512 bit time slots, is the lower of (2 ** N) and a random number between 0 and the selected backoff-limit.

EMAC_CONFIG_BO_LIMIT_1024
EMAC_CONFIG_BO_LIMIT_256
EMAC_CONFIG_BO_LIMIT_16
EMAC_CONFIG_BO_LIMIT_2

Control over insertion or replacement of the source address in all transmitted frames is provided by using one of the following fields:

EMAC_CONFIG_SA_INSERT causes the MAC address (0 or 1 depending on whether EMAC_CONFIG_USE_MACADDR0 or EMAC_CONFIG_USE_MACADDR1 was specified) to be inserted into all transmitted frames.
EMAC_CONFIG_SA_REPLACE causes the MAC address to be replaced with the selected address in all transmitted frames.
EMAC_CONFIG_SA_FROM_DESCRIPTOR causes control of source address insertion or deletion to be controlled by fields in the DMA transmit descriptor, allowing control on a frame-by-frame basis.

Whether the interface attempts to operate in full- or half-duplex mode is controlled by one of the following flags:

EMAC_CONFIG_FULL_DUPLEX
EMAC_CONFIG_HALF_DUPLEX

The following additional flags may also be specified:

EMAC_CONFIG_2K_PACKETS enables IEEE802.3as support for 2K packets. When specified, the MAC considers all frames up to 2000 bytes in length as normal packets. When EMAC_CONFIG_JUMBO_ENABLE is not specified, all frames larger than 2000 bytes are treated as Giant frames. This flag is ignored if EMAC_CONFIG_JUMBO_ENABLE is specified.
EMAC_CONFIG_STRIP_CRC causes the 4-byte CRC of all Ethernet type frames to be stripped and dropped before the frame is forwarded to the application.
EMAC_CONFIG_JABBER_DISABLE disables the jabber timer on the transmitter and enables frames of up to 16384 bytes to be transmitted. If this flag is absent, the MAC does not allow more than 2048 (or 10240 if EMAC_CONFIG_JUMBO_ENABLE is specified) bytes to be sent in any one frame.
EMAC_CONFIG_JUMBO_ENABLE enables Jumbo Frames, allowing frames of up to 9018 (or 9022 if using VLAN tagging) to be handled without reporting giant frame errors.
EMAC_CONFIG_100MBPS forces the MAC to communicate with the PHY using 100Mbps signaling. If this option is not specified, the MAC uses 10Mbps signaling. This speed setting is important when using an external RMII PHY where the selected rate must match the PHY's setting which may have been made as a result of auto-negotiation. When using the internal PHY or an external MII PHY, the signaling rate is controlled by the PHY- provided transmit and receive clocks.
EMAC_CONFIG_CS_DISABLE disables Carrier Sense during transmission when operating in half-duplex mode.
EMAC_CONFIG_RX_OWN_DISABLE disables reception of transmitted frames when operating in half-duplex mode.
EMAC_CONFIG_LOOPBACK enables internal loopback.
EMAC_CONFIG_CHECKSUM_OFFLOAD enables IPv4 header checksum checking and IPv4 or IPv6 TCP, UPD or ICMP payload checksum checking. The results of the checksum calculations are reported via status fields in the DMA receive descriptors.
EMAC_CONFIG_RETRY_DISABLE disables retransmission in cases where half-duplex mode is in use and a collision occurs. This condition causes the current frame to be ignored and a frame abort to be reported in the transmit frame status.
EMAC_CONFIG_AUTO_CRC_STRIPPING strips the last 4 bytes (frame check sequence) from all Ether type frames before forwarding the frames to the application.
EMAC_CONFIG_DEFERRAL_CHK_ENABLE enables transmit deferral checking in half-duplex mode. When enabled, the transmitter reports an error if it is unable to transmit a frame for more than 24288 bit times (or 155680 bit times in Jumbo frame mode) due to an active carrier sense signal on the MII.

The ui32ModeFlags parameter sets operating parameters related to the internal MAC FIFOs. It comprises a logical OR of the following fields. The first selects the transmit FIFO threshold. Transmission of a frame begins when this amount of data or a full frame exists in the transmit FIFO. This field is ignored if EMAC_MODE_TX_STORE_FORWARD is included. One of the following must be specified:

EMAC_MODE_TX_THRESHOLD_16_BYTES
EMAC_MODE_TX_THRESHOLD_24_BYTES
EMAC_MODE_TX_THRESHOLD_32_BYTES
EMAC_MODE_TX_THRESHOLD_40_BYTES
EMAC_MODE_TX_THRESHOLD_64_BYTES
EMAC_MODE_TX_THRESHOLD_128_BYTES
EMAC_MODE_TX_THRESHOLD_192_BYTES
EMAC_MODE_TX_THRESHOLD_256_BYTES

The second field controls the receive FIFO threshold. DMA transfers of received data begin either when the receive FIFO contains a full frame or this number of bytes. This field is ignored if EMAC_MODE_RX_STORE_FORWARD is included. One of the following must be specified:

EMAC_MODE_RX_THRESHOLD_64_BYTES
EMAC_MODE_RX_THRESHOLD_32_BYTES
EMAC_MODE_RX_THRESHOLD_96_BYTES
EMAC_MODE_RX_THRESHOLD_128_BYTES

The following additional flags may be specified:

EMAC_MODE_KEEP_BAD_CRC causes frames with TCP/IP checksum errors to be forwarded to the application if those frames do not have any errors (including FCS errors) in the Ethernet framing. In these cases, the frames have errors only in the payload. If this flag is not specified, all frames with any detected error are discarded unless EMAC_MODE_RX_ERROR_FRAMES is also specified.
EMAC_MODE_RX_STORE_FORWARD causes the receive DMA to read frames from the FIFO only after the complete frame has been written to it. If this mode is enabled, the receive threshold is ignored.
EMAC_MODE_RX_FLUSH_DISABLE disables the flushing of received frames in cases where receive descriptors or buffers are unavailable.
EMAC_MODE_TX_STORE_FORWARD causes the transmitter to start transmitting a frame only after the whole frame has been written to the transmit FIFO. If this mode is enabled, the transmit threshold is ignored.
EMAC_MODE_RX_ERROR_FRAMES causes all frames other than runt error frames to be forwarded to the receive DMA regardless of any errors detected in the frames.
EMAC_MODE_RX_UNDERSIZED_FRAMES causes undersized frames (frames shorter than 64 bytes but with no errors) to the application. If this option is not selected, all undersized frames are dropped by the receiver unless it has already started transferring them to the receive FIFO due to the receive threshold setting.
EMAC_MODE_OPERATE_2ND_FRAME enables the transmit DMA to operate on a second frame while waiting for the previous frame to be transmitted and associated status and timestamps to be reported. If absent, the transmit DMA works on a single frame at any one time, waiting for that frame to be transmitted and its status to be received before moving on to the next frame.

The ui32RxMaxFrameSize parameter may be used to override the default setting for the maximum number of bytes that can be received in a frame before that frame is flagged as being in error. If the parameter is set to 0, the default hardware settings are applied. If non-zero, any frame received which is longer than the ui32RxMaxFrameSize, regardless of whether the MAC is configured for normal or Jumbo frame operation, is flagged as an error.

Returns: None.

References ASSERT, EMAC_CFG_PS, EMAC_CONFIG_RX_ENABLED, EMAC_CONFIG_TX_ENABLED, EMAC_O_CFG, EMAC_O_DMAOPMODE, EMAC_O_WDOGTO, EMAC_WDOGTO_PWE, HWREG, and VALID_CONFIG_FLAGS.

§ EMACConfigGet()

void EMACConfigGet	(	uint32_t	ui32Base,
		uint32_t *	pui32Config,
		uint32_t *	pui32Mode,
		uint32_t *	pui32RxMaxFrameSize
	)

Returns the Ethernet MAC's current basic configuration parameters.

Parameters

ui32Base	is the base address of the Ethernet controller.
pui32Config	points to storage that is written with Ethernet MAC configuration.
pui32Mode	points to storage that is written with Ethernet MAC mode information.
pui32RxMaxFrameSize	points to storage that is written with the maximum receive frame size.

This function is called to query the basic operating parameters for the MAC and its DMA engines.

The pui32Config parameter is written with the logical OR of various fields and flags. The first field describes which MAC address is used during insertion or replacement for all transmitted frames. Valid options are

EMAC_CONFIG_USE_MACADDR1
EMAC_CONFIG_USE_MACADDR0

The interframe gap between transmitted frames is given using one of the following values:

EMAC_CONFIG_IF_GAP_96BITS
EMAC_CONFIG_IF_GAP_88BITS
EMAC_CONFIG_IF_GAP_80BITS
EMAC_CONFIG_IF_GAP_72BITS
EMAC_CONFIG_IF_GAP_64BITS
EMAC_CONFIG_IF_GAP_56BITS
EMAC_CONFIG_IF_GAP_48BITS
EMAC_CONFIG_IF_GAP_40BITS

The number of bytes of preamble added to the beginning of every transmitted frame is described using one of the following values:

EMAC_CONFIG_7BYTE_PREAMBLE
EMAC_CONFIG_5BYTE_PREAMBLE
EMAC_CONFIG_3BYTE_PREAMBLE

The back-off limit determines the range of the random time that the MAC delays after a collision and before attempting to retransmit a frame. One of the following values provides the currently selected limit. In each case the retransmission delay in terms of 512 bit time slots, is the lower of (2 ** N) and a random number between 0 and the reported backoff-limit.

EMAC_CONFIG_BO_LIMIT_1024
EMAC_CONFIG_BO_LIMIT_256
EMAC_CONFIG_BO_LIMIT_16
EMAC_CONFIG_BO_LIMIT_2

Handling of insertion or replacement of the source address in all transmitted frames is described by one of the following fields:

EMAC_CONFIG_SA_INSERT causes the MAC address (0 or 1 depending on whether EMAC_CONFIG_USE_MACADDR0 or EMAC_CONFIG_USE_MACADDR1 was specified) to be inserted into all transmitted frames.
EMAC_CONFIG_SA_REPLACE causes the MAC address to be replaced with the selected address in all transmitted frames.
EMAC_CONFIG_SA_FROM_DESCRIPTOR causes control of source address insertion or deletion to be controlled by fields in the DMA transmit descriptor, allowing control on a frame-by-frame basis.

Whether the interface attempts to operate in full- or half-duplex mode is reported by one of the following flags:

EMAC_CONFIG_FULL_DUPLEX
EMAC_CONFIG_HALF_DUPLEX

The following additional flags may also be included:

EMAC_CONFIG_2K_PACKETS indicates that IEEE802.3as support for 2K packets is enabled. When present, the MAC considers all frames up to 2000 bytes in length as normal packets. When EMAC_CONFIG_JUMBO_ENABLE is not reported, all frames larger than 2000 bytes are treated as Giant frames. The value of this flag should be ignored if EMAC_CONFIG_JUMBO_ENABLE is also reported.
EMAC_CONFIG_STRIP_CRC indicates that the 4-byte CRC of all Ethernet type frames is being stripped and dropped before the frame is forwarded to the application.
EMAC_CONFIG_JABBER_DISABLE indicates that the the jabber timer on the transmitter is disabled, allowing frames of up to 16384 bytes to be transmitted. If this flag is absent, the MAC does not allow more than 2048 (or 10240 if EMAC_CONFIG_JUMBO_ENABLE is reported) bytes to be sent in any one frame.
EMAC_CONFIG_JUMBO_ENABLE indicates that Jumbo Frames of up to 9018 (or 9022 if using VLAN tagging) are enabled.
EMAC_CONFIG_CS_DISABLE indicates that Carrier Sense is disabled during transmission when operating in half-duplex mode.
EMAC_CONFIG_100MBPS indicates that the MAC is using 100Mbps signaling to communicate with the PHY.
EMAC_CONFIG_RX_OWN_DISABLE indicates that reception of transmitted frames is disabled when operating in half-duplex mode.
EMAC_CONFIG_LOOPBACK indicates that internal loopback is enabled.
EMAC_CONFIG_CHECKSUM_OFFLOAD indicates that IPv4 header checksum checking and IPv4 or IPv6 TCP, UPD or ICMP payload checksum checking is enabled. The results of the checksum calculations are reported via status fields in the DMA receive descriptors.
EMAC_CONFIG_RETRY_DISABLE indicates that retransmission is disabled in cases where half-duplex mode is in use and a collision occurs. This condition causes the current frame to be ignored and a frame abort to be reported in the transmit frame status.
EMAC_CONFIG_AUTO_CRC_STRIPPING indicates that the last 4 bytes (frame check sequence) from all Ether type frames are being stripped before frames are forwarded to the application.
EMAC_CONFIG_DEFERRAL_CHK_ENABLE indicates that transmit deferral checking is disabled in half-duplex mode. When enabled, the transmitter reports an error if it is unable to transmit a frame for more than 24288 bit times (or 155680 bit times in Jumbo frame mode) due to an active carrier sense signal on the MII.
EMAC_CONFIG_TX_ENABLED indicates that the MAC transmitter is currently enabled.
EMAC_CONFIG_RX_ENABLED indicates that the MAC receiver is currently enabled.

The pui32ModeFlags parameter is written with operating parameters related to the internal MAC FIFOs. It comprises a logical OR of the following fields. The first field reports the transmit FIFO threshold. Transmission of a frame begins when this amount of data or a full frame exists in the transmit FIFO. This field should be ignored if EMAC_MODE_TX_STORE_FORWARD is also reported. One of the following values is reported:

EMAC_MODE_TX_THRESHOLD_16_BYTES
EMAC_MODE_TX_THRESHOLD_24_BYTES
EMAC_MODE_TX_THRESHOLD_32_BYTES
EMAC_MODE_TX_THRESHOLD_40_BYTES
EMAC_MODE_TX_THRESHOLD_64_BYTES
EMAC_MODE_TX_THRESHOLD_128_BYTES
EMAC_MODE_TX_THRESHOLD_192_BYTES
EMAC_MODE_TX_THRESHOLD_256_BYTES

The second field reports the receive FIFO threshold. DMA transfers of received data begin either when the receive FIFO contains a full frame or this number of bytes. This field should be ignored if EMAC_MODE_RX_STORE_FORWARD is included. One of the following values is reported:

EMAC_MODE_RX_THRESHOLD_64_BYTES
EMAC_MODE_RX_THRESHOLD_32_BYTES
EMAC_MODE_RX_THRESHOLD_96_BYTES
EMAC_MODE_RX_THRESHOLD_128_BYTES

The following additional flags may be included:

EMAC_MODE_KEEP_BAD_CRC indicates that frames with TCP/IP checksum errors are being forwarded to the application if those frames do not have any errors (including FCS errors) in the Ethernet framing. In these cases, the frames have errors only in the payload. If this flag is not reported, all frames with any detected error are discarded unless EMAC_MODE_RX_ERROR_FRAMES is also reported.
EMAC_MODE_RX_STORE_FORWARD indicates that the receive DMA is configured to read frames from the FIFO only after the complete frame has been written to it. If this mode is enabled, the receive threshold is ignored.
EMAC_MODE_RX_FLUSH_DISABLE indicates that the flushing of received frames is disabled in cases where receive descriptors or buffers are unavailable.
EMAC_MODE_TX_STORE_FORWARD indicates that the transmitter is configured to transmit a frame only after the whole frame has been written to the transmit FIFO. If this mode is enabled, the transmit threshold is ignored.
EMAC_MODE_RX_ERROR_FRAMES indicates that all frames other than runt error frames are being forwarded to the receive DMA regardless of any errors detected in the frames.
EMAC_MODE_RX_UNDERSIZED_FRAMES indicates that undersized frames (frames shorter than 64 bytes but with no errors) are being forwarded to the application. If this option is not reported, all undersized frames are dropped by the receiver unless it has already started transferring them to the receive FIFO due to the receive threshold setting.
EMAC_MODE_OPERATE_2ND_FRAME indicates that the transmit DMA is configured to operate on a second frame while waiting for the previous frame to be transmitted and associated status and timestamps to be reported. If absent, the transmit DMA works on a single frame at any one time, waiting for that frame to be transmitted and its status to be received before moving on to the next frame.
EMAC_MODE_TX_DMA_ENABLED indicates that the transmit DMA engine is currently enabled.
EMAC_MODE_RX_DMA_ENABLED indicates that the receive DMA engine is currently enabled.

The pui32RxMaxFrameSize is written with the currently configured maximum receive packet size. Packets larger than this are flagged as being in error.

Returns: None.

References ASSERT, EMAC_CFG_JFEN, EMAC_CONFIG_RX_ENABLED, EMAC_CONFIG_TX_ENABLED, EMAC_O_CFG, EMAC_O_DMAOPMODE, EMAC_O_WDOGTO, EMAC_WDOGTO_PWE, EMAC_WDOGTO_WTO_M, HWREG, and VALID_CONFIG_FLAGS.

§ EMACAddrSet()

void EMACAddrSet	(	uint32_t	ui32Base,
		uint32_t	ui32Index,
		const uint8_t *	pui8MACAddr
	)

Sets the MAC address of the Ethernet controller.

Parameters

ui32Base	is the base address of the Ethernet controller.
ui32Index	is the zero-based index of the MAC address to set.
pui8MACAddr	is the pointer to the array of MAC-48 address octets.

This function programs the IEEE-defined MAC-48 address specified in pui8MACAddr into the Ethernet controller. This address is used by the Ethernet controller for hardware-level filtering of incoming Ethernet packets (when promiscuous mode is not enabled). Index 0 is used to hold the local node's MAC address which is inserted into all transmitted packets.

The controller may support several Ethernet MAC address slots, each of which may be programmed independently and used to filter incoming packets. The number of MAC addresses that the hardware supports may be queried using a call to EMACNumAddrGet(). The value of the ui32Index parameter must lie in the range from 0 to (number of MAC addresses - 1) inclusive.

The MAC-48 address is defined as 6 octets, illustrated by the following example address. The numbers are shown in hexadecimal format.

    AC-DE-48-00-00-80

In this representation, the first three octets (AC-DE-48) are the Organizationally Unique Identifier (OUI). This is a number assigned by the IEEE to an organization that requests a block of MAC addresses. The last three octets (00-00-80) are a 24-bit number managed by the OUI owner to uniquely identify a piece of hardware within that organization that is to be connected to the Ethernet.

In this representation, the octets are transmitted from left to right, with the AC'' octet being transmitted first and the80'' octet being transmitted last. Within an octet, the bits are transmitted LSB to MSB. For this address, the first bit to be transmitted would be 0'', the LSB ofAC'', and the last bit to be transmitted would be 1'', the MSB of 80''.

The address passed to this function in the pui8MACAddr array is ordered with the first byte to be transmitted in the first array entry. For example, the address given above could be represented using the following array:

uint8_t g_pui8MACAddr[] = { 0xAC, 0xDE, 0x48, 0x00, 0x00, 0x80 };

If the MAC address set by this function is currently enabled, it remains enabled following this call. Similarly, any filter configured for the MAC address remains unaffected by a change in the address.

Returns: None.

References ASSERT, EMAC_O_ADDRH, EMAC_O_ADDRL, HWREG, and NUM_MAC_ADDR.

§ EMACAddrGet()

void EMACAddrGet	(	uint32_t	ui32Base,
		uint32_t	ui32Index,
		uint8_t *	pui8MACAddr
	)

Gets one of the MAC addresses stored in the Ethernet controller.

Parameters

ui32Base	is the base address of the controller.
ui32Index	is the zero-based index of the MAC address to return.
pui8MACAddr	is the pointer to the location in which to store the array of MAC-48 address octets.

This function reads the currently programmed MAC address into the pui8MACAddr buffer. The ui32Index parameter defines which of the hardware's MAC addresses to return. The number of MAC addresses supported by the controller may be queried using a call to EMACNumAddrGet(). Index 0 refers to the MAC address of the local node. Other indices are used to define MAC addresses when filtering incoming packets.

The address is written to the pui8MACAddr array ordered with the first byte to be transmitted in the first array entry. For example, if the address is written in its usual form with the Organizationally Unique Identifier (OUI) shown first as:

AC-DE-48-00-00-80

the data is returned with 0xAC in the first byte of the array, 0xDE in the second, 0x48 in the third and so on.

Returns: None.

References ASSERT, EMAC_O_ADDRH, EMAC_O_ADDRL, HWREG, and NUM_MAC_ADDR.

§ EMACNumAddrGet()

uint32_t EMACNumAddrGet ( uint32_t ui32Base )

Returns the number of MAC addresses supported by the Ethernet controller.

Parameters

ui32Base is the base address of the Ethernet controller.

This function may be used to determine the number of MAC addresses that the given controller supports. MAC address slots may be used when performing perfect (rather than hash table) filtering of packets.

Returns: Returns the number of supported MAC addresses.

References NUM_MAC_ADDR.

§ EMACAddrFilterSet()

void EMACAddrFilterSet	(	uint32_t	ui32Base,
		uint32_t	ui32Index,
		uint32_t	ui32Config
	)

Sets filtering parameters associated with one of the configured MAC addresses.

Parameters

ui32Base	is the base address of the controller.
ui32Index	is the index of the MAC address slot for which the filter is to be set.
ui32Config	sets the filter parameters for the given MAC address.

This function sets filtering parameters associated with one of the MAC address slots that the controller supports. This configuration is used when perfect filtering (rather than hash table filtering) is selected.

Valid values for ui32Index are from 1 to (number of MAC address slots - 1). The number of supported MAC address slots may be found by calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does not have filtering parameters associated with it.

The ui32Config parameter determines how the given MAC address is used when filtering incoming Ethernet frames. It is comprised of a logical OR of the fields:

EMAC_FILTER_ADDR_ENABLE indicates that this MAC address is enabled and should be used when performing perfect filtering. If this flag is absent, the MAC address at the given index is disabled and is not used in filtering.
EMAC_FILTER_SOURCE_ADDR indicates that the MAC address at the given index is compared to the source address of incoming frames while performing perfect filtering. If absent, the MAC address is compared against the destination address.
EMAC_FILTER_MASK_BYTE_6 indicates that the MAC should ignore the sixth byte of the source or destination address when filtering.
EMAC_FILTER_MASK_BYTE_5 indicates that the MAC should ignore the fifth byte of the source or destination address when filtering.
EMAC_FILTER_MASK_BYTE_4 indicates that the MAC should ignore the fourth byte of the source or destination address when filtering.
EMAC_FILTER_MASK_BYTE_3 indicates that the MAC should ignore the third byte of the source or destination address when filtering.
EMAC_FILTER_MASK_BYTE_2 indicates that the MAC should ignore the second byte of the source or destination address when filtering.
EMAC_FILTER_MASK_BYTE_1 indicates that the MAC should ignore the first byte of the source or destination address when filtering.

Returns: None.

References ASSERT, EMAC_FILTER_ADDR_ENABLE, EMAC_FILTER_BYTE_MASK_M, EMAC_FILTER_SOURCE_ADDR, EMAC_O_ADDRH, EMAC_O_ADDRL, HWREG, and NUM_MAC_ADDR.

§ EMACAddrFilterGet()

uint32_t EMACAddrFilterGet	(	uint32_t	ui32Base,
		uint32_t	ui32Index
	)

Gets filtering parameters associated with one of the configured MAC addresses.

Parameters

ui32Base	is the base address of the controller.
ui32Index	is the index of the MAC address slot for which the filter is to be queried.

This function returns filtering parameters associated with one of the MAC address slots that the controller supports. This configuration is used when perfect filtering (rather than hash table filtering) is selected.

Valid values for ui32Index are from 1 to (number of MAC address slots - 1). The number of supported MAC address slots may be found by calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does not have filtering parameters associated with it.

Returns: Returns the filter configuration as the logical OR of the following labels:

EMAC_FILTER_ADDR_ENABLE indicates that this MAC address is enabled and is used when performing perfect filtering. If this flag is absent, the MAC address at the given index is disabled and is not used in filtering.
EMAC_FILTER_SOURCE_ADDR indicates that the MAC address at the given index is compared to the source address of incoming frames while performing perfect filtering. If absent, the MAC address is compared against the destination address.
EMAC_FILTER_MASK_BYTE_6 indicates that the MAC ignores the sixth byte of the source or destination address when filtering.
EMAC_FILTER_MASK_BYTE_5 indicates that the MAC ignores the fifth byte of the source or destination address when filtering.
EMAC_FILTER_MASK_BYTE_4 indicates that the MAC ignores the fourth byte of the source or destination address when filtering.
EMAC_FILTER_MASK_BYTE_3 indicates that the MAC ignores the third byte of the source or destination address when filtering.
EMAC_FILTER_MASK_BYTE_2 indicates that the MAC ignores the second byte of the source or destination address when filtering.
EMAC_FILTER_MASK_BYTE_1 indicates that the MAC ignores the first byte of the source or destination address when filtering.

References ASSERT, EMAC_FILTER_ADDR_ENABLE, EMAC_FILTER_BYTE_MASK_M, EMAC_FILTER_SOURCE_ADDR, EMAC_O_ADDRH, HWREG, and NUM_MAC_ADDR.

§ EMACFrameFilterSet()

void EMACFrameFilterSet	(	uint32_t	ui32Base,
		uint32_t	ui32FilterOpts
	)

Sets options related to Ethernet frame filtering.

Parameters

ui32Base	is the base address of the controller.
ui32FilterOpts	is a logical OR of flags defining the required MAC address filtering options.

This function allows various filtering options to be defined and allows an application to control which frames are received based on various criteria related to the frame source and destination MAC addresses or VLAN tagging.

The ui32FilterOpts parameter is a logical OR of any of the following flags:

EMAC_FRMFILTER_RX_ALL configures the MAC to pass all received frames regardless of whether or not they pass any address filter that is configured. The receive status word in the relevant DMA descriptor is updated to indicate whether the configured filter passed or failed for the frame.
EMAC_FRMFILTER_VLAN configures the MAC to drop any frames that do not pass the VLAN tag comparison.
EMAC_FRMFILTER_HASH_AND_PERFECT configures the MAC to filter frames based on both any perfect filters set and the hash filter if enabled using EMAC_FRMFILTER_HASH_UNICAST or EMAC_FRMFILTER_HASH_MULTICAST. In this case, only if both filters fail is the packet rejected. If this option is absent, only one of the filter types is used, as controlled by EMAC_FRMFILTER_HASH_UNICAST and EMAC_FRMFILTER_HASH_MULTICAST for unicast and multicast frames respectively.
EMAC_FRMFILTER_SADDR configures the MAC to drop received frames when the source address field in the frame does not match the values programmed into the enabled SA registers.
EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering. When this option is specified, frames for which the SA does not match the SA registers are marked as passing the source address filter.
EMAC_FRMFILTER_BROADCAST configures the MAC to discard all incoming broadcast frames.
EMAC_FRMFILTER_PASS_MULTICAST configures the MAC to pass all incoming frames with multicast destinations addresses.
EMAC_FRMFILTER_INV_DADDR inverts the sense of the destination address filtering for both unicast and multicast frames.
EMAC_FRMFILTER_HASH_MULTICAST enables destination address filtering of received multicast frames using the hash table. If absent, perfect destination address filtering is used. If used in conjunction with EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter should be used for incoming multicast packets along with the perfect filter.
EMAC_FRMFILTER_HASH_UNICAST enables destination address filtering of received unicast frames using the hash table. If absent, perfect destination address filtering is used. If used in conjunction with EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter should be used for incoming unicast packets along with the perfect filter.
EMAC_FRMFILTER_PROMISCUOUS configures the MAC to operate in promiscuous mode where all received frames are passed to the application and the SA and DA filter status bits of the descriptor receive status word are always cleared.

Control frame filtering may be configured by ORing one of the following values into ui32FilterOpts:

EMAC_FRMFILTER_PASS_NO_CTRL prevents any control frame from reaching the application.
EMAC_FRMFILTER_PASS_NO_PAUSE passes all control frames other than PAUSE even if they fail the configured address filter.
EMAC_FRMFILTER_PASS_ALL_CTRL passes all control frames, including PAUSE even if they fail the configured address filter.
EMAC_FRMFILTER_PASS_ADDR_CTRL passes all control frames only if they pass the configured address filter.

Returns: None.

References ASSERT, EMAC_O_FRAMEFLTR, HWREG, and VALID_FRMFILTER_FLAGS.

§ EMACFrameFilterGet()

uint32_t EMACFrameFilterGet ( uint32_t ui32Base )

Returns the current Ethernet frame filtering settings.

Parameters

ui32Base is the base address of the controller.

This function may be called to retrieve the frame filtering configuration set using a prior call to EMACFrameFilterSet().

Returns: Returns a value comprising the logical OR of various flags indicating the frame filtering options in use. Possible flags are:

EMAC_FRMFILTER_RX_ALL indicates that the MAC to is configured to pass all received frames regardless of whether or not they pass any address filter that is configured. The receive status word in the relevant DMA descriptor is updated to indicate whether the configured filter passed or failed for the frame.
EMAC_FRMFILTER_VLAN indicates that the MAC is configured to drop any frames which do not pass the VLAN tag comparison.
EMAC_FRMFILTER_HASH_AND_PERFECT indicates that the MAC is configured to pass frames if they match either the hash filter or the perfect filter. If this flag is absent, frames passing based on the result of a single filter, the perfect filter if EMAC_FRMFILTER_HASH_MULTICAST or EMAC_FRMFILTER_HASH_UNICAST are clear or the hash filter otherwise.
EMAC_FRMFILTER_SADDR indicates that the MAC is configured to drop received frames when the source address field in the frame does not match the values programmed into the enabled SA registers.
EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering. When this option is specified, frames for which the SA does not match the SA registers are marked as passing the source address filter.
EMAC_FRMFILTER_BROADCAST indicates that the MAC is configured to discard all incoming broadcast frames.
EMAC_FRMFILTER_PASS_MULTICAST indicates that the MAC is configured to pass all incoming frames with multicast destinations addresses.
EMAC_FRMFILTER_INV_DADDR indicates that the sense of the destination address filtering for both unicast and multicast frames is inverted.
EMAC_FRMFILTER_HASH_MULTICAST indicates that destination address filtering of received multicast frames is enabled using the hash table. If absent, perfect destination address filtering is used. If used in conjunction with EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter should be used for incoming multicast packets along with the perfect filter.
EMAC_FRMFILTER_HASH_UNICAST indicates that destination address filtering of received unicast frames is enabled using the hash table. If absent, perfect destination address filtering is used. If used in conjunction with EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter should be used for incoming unicast packets along with the perfect filter.
EMAC_FRMFILTER_PROMISCUOUS indicates that the MAC is configured to operate in promiscuous mode where all received frames are passed to the application and the SA and DA filter status bits of the descriptor receive status word are always cleared.

Control frame filtering configuration is indicated by one of the following values which may be extracted from the returned value using the mask EMAC_FRMFILTER_PASS_MASK:

EMAC_FRMFILTER_PASS_NO_CTRL prevents any control frame from reaching the application.
EMAC_FRMFILTER_PASS_NO_PAUSE passes all control frames other than PAUSE even if they fail the configured address filter.
EMAC_FRMFILTER_PASS_ALL_CTRL passes all control frames, including PAUSE even if they fail the configured address filter.
EMAC_FRMFILTER_PASS_ADDR_CTRL passes all control frames only if they pass the configured address filter.

References EMAC_O_FRAMEFLTR, HWREG, and VALID_FRMFILTER_FLAGS.

§ EMACHashFilterSet()

void EMACHashFilterSet	(	uint32_t	ui32Base,
		uint32_t	ui32HashHi,
		uint32_t	ui32HashLo
	)

Sets the MAC address hash filter table.

Parameters

ui32Base	is the base address of the controller.
ui32HashHi	is the upper 32 bits of the current 64-bit hash filter table to set.
ui32HashLo	is the lower 32 bits of the current 64-bit hash filter table to set.

This function may be used to set the current 64-bit hash filter table used by the MAC to filter incoming packets when hash filtering is enabled. Hash filtering is enabled by passing EMAC_FRMFILTER_HASH_UNICAST and/or EMAC_FRMFILTER_HASH_MULTICAST in the ui32FilterOpts parameter to EMACFrameFilterSet(). The current hash filter may be retrieved by calling EMACHashFilterGet().

Hash table filtering allows many different MAC addresses to be filtered simultaneously at the cost of some false-positive results (in the form of packets passing the filter when their MAC address was not one of those required). A CRC of the packet source or destination MAC address is calculated and the bottom 6 bits are used as a bit index into the 64-bit hash filter table. If the bit in the hash table is set, the filter is considered to have passed. If the bit is clear, the filter fails and the packet is rejected (assuming normal rather than inverse filtering is configured).

Returns: None.

References EMAC_O_HASHTBLH, EMAC_O_HASHTBLL, and HWREG.

§ EMACHashFilterGet()

void EMACHashFilterGet	(	uint32_t	ui32Base,
		uint32_t *	pui32HashHi,
		uint32_t *	pui32HashLo
	)

Returns the current MAC address hash filter table.

Parameters

ui32Base	is the base address of the controller.
pui32HashHi	points to storage to be written with the upper 32 bits of the current 64-bit hash filter table.
pui32HashLo	points to storage to be written with the lower 32 bits of the current 64-bit hash filter table.

This function may be used to retrieve the current 64-bit hash filter table from the MAC prior to making changes and setting the new hash filter via a call to EMACHashFilterSet().

Hash table filtering allows many different MAC addresses to be filtered simultaneously at the cost of some false-positive results in the form of packets passing the filter when their MAC address was not one of those required. A CRC of the packet source or destination MAC address is calculated and the bottom 6 bits are used as a bit index into the 64-bit hash filter table. If the bit in the hash table is set, the filter is considered to have passed. If the bit is clear, the filter fails and the packet is rejected (assuming normal rather than inverse filtering is configured).

Returns: None.

References ASSERT, EMAC_O_HASHTBLH, EMAC_O_HASHTBLL, and HWREG.

§ EMACHashFilterBitCalculate()

uint32_t EMACHashFilterBitCalculate ( uint8_t * pui8MACAddr )

Returns the bit number to set in the MAC hash filter corresponding to a given MAC address.

Parameters

pui8MACAddr points to a buffer containing the 6-byte MAC address for which the hash filter bit is to be determined.

This function may be used to determine which bit in the MAC address hash filter to set to describe a given 6-byte MAC address. The returned value is a 6-bit number where bit 5 indicates which of the two hash table words is affected and the bottom 5 bits indicate the bit number to set within that word. For example, if 0x22 (100010b) is returned, this indicates that bit 2 of word 1 (ui32HashHi as passed to EMACHashFilterSet()) must be set to describe the passed MAC address.

Returns: Returns the bit number to set in the MAC hash table to describe the passed MAC address.

References ASSERT, and Crc32().

§ EMACRxWatchdogTimerSet()

void EMACRxWatchdogTimerSet	(	uint32_t	ui32Base,
		uint8_t	ui8Timeout
	)

Sets the receive interrupt watchdog timer period.

Parameters

ui32Base	is the base address of the Ethernet controller.
ui8Timeout	is the desired timeout expressed as a number of 256 system clock periods.

This function configures the receive interrupt watchdog timer. The uiTimeout parameter specifies the number of 256 system clock periods that elapse before the timer expires. In cases where the DMA has transferred a frame using a descriptor that has DES1_RX_CTRL_DISABLE_INT set, the watchdog causes a receive interrupt to be generated when it times out. The watchdog timer is reset whenever a packet is transferred to memory using a DMA descriptor that does not disable the receive interrupt.

To disable the receive interrupt watchdog function, set ui8Timeout to 0.

Returns: None.

References EMAC_O_RXINTWDT, and HWREG.

§ EMACStatusGet()

uint32_t EMACStatusGet ( uint32_t ui32Base )

Returns the current Ethernet MAC status.

Parameters

ui32Base is the base address of the Ethernet controller.

This function returns information on the current status of all the main modules in the MAC transmit and receive data paths.

Returns: Returns the current MAC status as a logical OR of any of the following flags:

EMAC_STATUS_TX_NOT_EMPTY
EMAC_STATUS_TX_WRITING_FIFO
EMAC_STATUS_TX_PAUSED
EMAC_STATUS_MAC_NOT_IDLE
EMAC_STATUS_RWC_ACTIVE
EMAC_STATUS_RPE_ACTIVE

The transmit frame controller status can be extracted from the returned value by ANDing with EMAC_STATUS_TFC_STATE_MASK and is one of the following:

EMAC_STATUS_TFC_STATE_IDLE
EMAC_STATUS_TFC_STATE_WAITING
EMAC_STATUS_TFC_STATE_PAUSING
EMAC_STATUS_TFC_STATE_WRITING

The transmit FIFO read controller status can be extracted from the returned value by ANDing with EMAC_STATUS_TRC_STATE_MASK and is one of the following:

EMAC_STATUS_TRC_STATE_IDLE
EMAC_STATUS_TRC_STATE_READING
EMAC_STATUS_TRC_STATE_WAITING
EMAC_STATUS_TRC_STATE_STATUS

The current receive FIFO levels can be extracted from the returned value by ANDing with EMAC_STATUS_RX_FIFO_LEVEL_MASK and is one of the following:

EMAC_STATUS_RX_FIFO_EMPTY indicating that the FIFO is empty.
EMAC_STATUS_RX_FIFO_BELOW indicating that the FIFO fill level is below the flow-control deactivate threshold.
EMAC_STATUS_RX_FIFO_ABOVE indicating that the FIFO fill level is above the flow-control activate threshold.
EMAC_STATUS_RX_FIFO_FULL indicating that the FIFO is full.

The current receive FIFO state can be extracted from the returned value by ANDing with EMAC_STATUS_RX_FIFO_STATE_MASK and is one of the following:

EMAC_STATUS_RX_FIFO_IDLE
EMAC_STATUS_RX_FIFO_READING
EMAC_STATUS_RX_FIFO_STATUS
EMAC_STATUS_RX_FIFO_FLUSHING

References EMAC_O_STATUS, and HWREG.

§ EMACTxDMAPollDemand()

void EMACTxDMAPollDemand ( uint32_t ui32Base )

Orders the MAC DMA controller to attempt to acquire the next transmit descriptor.

Parameters

ui32Base is the base address of the Ethernet controller.

This function must be called to restart the transmitter if it has been suspended due to the current transmit DMA descriptor being owned by the host. Once the application writes new values to the descriptor and marks it as being owned by the MAC DMA, this function causes the hardware to attempt to acquire the descriptor and start transmission of the new data.

Returns: None.

References EMAC_O_TXPOLLD, and HWREG.

§ EMACRxDMAPollDemand()

void EMACRxDMAPollDemand ( uint32_t ui32Base )

Orders the MAC DMA controller to attempt to acquire the next receive descriptor.

Parameters

ui32Base is the base address of the Ethernet controller.

This function must be called to restart the receiver if it has been suspended due to the current receive DMA descriptor being owned by the host. Once the application reads any data from the descriptor and marks it as being owned by the MAC DMA, this function causes the hardware to attempt to acquire the descriptor before writing the next received packet into its buffer(s).

Returns: None.

References EMAC_O_RXPOLLD, and HWREG.

§ EMACRxDMADescriptorListSet()

void EMACRxDMADescriptorListSet	(	uint32_t	ui32Base,
		tEMACDMADescriptor *	pDescriptor
	)

Sets the DMA receive descriptor list pointer.

Parameters

ui32Base	is the base address of the controller.
pDescriptor	points to the first DMA descriptor in the list to be passed to the receive DMA engine.

This function sets the Ethernet MAC's receive DMA descriptor list pointer. The pDescriptor pointer must point to one or more descriptor structures.

When multiple descriptors are provided, they can be either chained or unchained. Chained descriptors are indicated by setting the DES0_TX_CTRL_CHAINED or DES1_RX_CTRL_CHAINED bit in the relevant word of the transmit or receive descriptor. If this bit is clear, unchained descriptors are assumed.

Chained descriptors use a link pointer in each descriptor to point to the next descriptor in the chain.

Unchained descriptors are assumed to be contiguous in memory with a consistent offset between the start of one descriptor and the next. If unchained descriptors are used, the pvLink field in the descriptor becomes available to store a second buffer pointer, allowing each descriptor to point to two buffers rather than one. In this case, the ui32DescSkipSize parameter to EMACInit() must previously have been set to the number of words between the end of one descriptor and the start of the next. This value must be 0 in cases where a packed array of tEMACDMADescriptor structures is used. If the application wishes to add new state fields to the end of the descriptor structure, the skip size should be set to accommodate the newly sized structure.

Applications are responsible for initializing all descriptor fields appropriately before passing the descriptor list to the hardware.

Returns: None.

References ASSERT, EMAC_O_RXDLADDR, and HWREG.

§ EMACRxDMADescriptorListGet()

tEMACDMADescriptor* EMACRxDMADescriptorListGet ( uint32_t ui32Base )

Returns a pointer to the start of the DMA receive descriptor list.

Parameters

ui32Base is the base address of the controller.

This function returns a pointer to the head of the Ethernet MAC's receive DMA descriptor list. This value corresponds to the pointer originally set using a call to EMACRxDMADescriptorListSet().

Returns: Returns a pointer to the start of the DMA receive descriptor list.

References EMAC_O_RXDLADDR, and HWREG.

§ EMACRxDMACurrentDescriptorGet()

tEMACDMADescriptor* EMACRxDMACurrentDescriptorGet ( uint32_t ui32Base )

Returns the current DMA receive descriptor pointer.

Parameters

ui32Base is the base address of the controller.

This function returns a pointer to the current Ethernet receive descriptor read by the DMA.

Returns: Returns a pointer to the start of the current receive DMA descriptor.

References EMAC_O_HOSRXDESC, and HWREG.

§ EMACRxDMACurrentBufferGet()

uint8_t* EMACRxDMACurrentBufferGet ( uint32_t ui32Base )

Returns the current DMA receive buffer pointer.

Parameters

ui32Base is the base address of the controller.

This function may be called to determine which buffer the receive DMA engine is currently writing to.

Returns: Returns the receive buffer address currently being written by the DMA engine.

References EMAC_O_HOSRXBA, and HWREG.

§ EMACTxDMADescriptorListSet()

void EMACTxDMADescriptorListSet	(	uint32_t	ui32Base,
		tEMACDMADescriptor *	pDescriptor
	)

Sets the DMA transmit descriptor list pointer.

Parameters

ui32Base	is the base address of the controller.
pDescriptor	points to the first DMA descriptor in the list to be passed to the transmit DMA engine.

This function sets the Ethernet MAC's transmit DMA descriptor list pointer. The pDescriptor pointer must point to one or more descriptor structures.

When multiple descriptors are provided, they can be either chained or unchained. Chained descriptors are indicated by setting the DES0_TX_CTRL_CHAINED or DES1_RX_CTRL_CHAINED bit in the relevant word of the transmit or receive descriptor. If this bit is clear, unchained descriptors are assumed.

Chained descriptors use a link pointer in each descriptor to point to the next descriptor in the chain.

Unchained descriptors are assumed to be contiguous in memory with a consistent offset between the start of one descriptor and the next. If unchained descriptors are used, the pvLink field in the descriptor becomes available to store a second buffer pointer, allowing each descriptor to point to two buffers rather than one. In this case, the ui32DescSkipSize parameter to EMACInit() must previously have been set to the number of words between the end of one descriptor and the start of the next. This value must be 0 in cases where a packed array of tEMACDMADescriptor structures is used. If the application wishes to add new state fields to the end of the descriptor structure, the skip size should be set to accommodate the newly sized structure.

Applications are responsible for initializing all descriptor fields appropriately before passing the descriptor list to the hardware.

Returns: None.

References ASSERT, EMAC_O_TXDLADDR, and HWREG.

§ EMACTxDMADescriptorListGet()

tEMACDMADescriptor* EMACTxDMADescriptorListGet ( uint32_t ui32Base )

Returns a pointer to the start of the DMA transmit descriptor list.

Parameters

ui32Base is the base address of the controller.

This function returns a pointer to the head of the Ethernet MAC's transmit DMA descriptor list. This value corresponds to the pointer originally set using a call to EMACTxDMADescriptorListSet().

Returns: Returns a pointer to the start of the DMA transmit descriptor list.

References EMAC_O_TXDLADDR, and HWREG.

§ EMACTxDMACurrentDescriptorGet()

tEMACDMADescriptor* EMACTxDMACurrentDescriptorGet ( uint32_t ui32Base )

Returns the current DMA transmit descriptor pointer.

Parameters

ui32Base is the base address of the controller.

This function returns a pointer to the current Ethernet transmit descriptor read by the DMA.

Returns: Returns a pointer to the start of the current transmit DMA descriptor.

References EMAC_O_HOSTXDESC, and HWREG.

§ EMACTxDMACurrentBufferGet()

uint8_t* EMACTxDMACurrentBufferGet ( uint32_t ui32Base )

Returns the current DMA transmit buffer pointer.

Parameters

ui32Base is the base address of the controller.

This function may be called to determine which buffer the transmit DMA engine is currently reading from.

Returns: Returns the transmit buffer address currently being read by the DMA engine.

References EMAC_O_HOSTXBA, and HWREG.

§ EMACDMAStateGet()

uint32_t EMACDMAStateGet ( uint32_t ui32Base )

Returns the current states of the Ethernet MAC transmit and receive DMA engines.

Parameters

ui32Base is the base address of the controller.

This function may be used to query the current states of the transmit and receive DMA engines. The return value contains two fields, one providing the transmit state and the other the receive state. Macros EMAC_TX_DMA_STATE() and EMAC_RX_DMA_STATE() may be used to extract these fields from the returned value. Alternatively, masks EMAC_DMA_TXSTAT_MASK and EMAC_DMA_RXSTAT_MASK may be used directly to mask out the individual states from the returned value.

Returns: Returns the states of the transmit and receive DMA engines. These states are ORed together into a single word containing one of:

EMAC_DMA_TXSTAT_STOPPED indicating that the transmit engine is stopped.
EMAC_DMA_TXSTAT_RUN_FETCH_DESC indicating that the transmit engine is fetching the next descriptor.
EMAC_DMA_TXSTAT_RUN_WAIT_STATUS indicating that the transmit engine is waiting for status from the MAC.
EMAC_DMA_TXSTAT_RUN_READING indicating that the transmit engine is currently transferring data from memory to the MAC transmit FIFO.
EMAC_DMA_TXSTAT_RUN_CLOSE_DESC indicating that the transmit engine is closing the descriptor after transmission of the buffer data.
EMAC_DMA_TXSTAT_TS_WRITE indicating that the transmit engine is currently writing timestamp information to the descriptor.
EMAC_DMA_TXSTAT_SUSPENDED indicating that the transmit engine is suspended due to the next descriptor being unavailable (owned by the host) or a transmit buffer underflow.

and one of:

EMAC_DMA_RXSTAT_STOPPED indicating that the receive engine is stopped.
EMAC_DMA_RXSTAT_RUN_FETCH_DESC indicating that the receive engine is fetching the next descriptor.
EMAC_DMA_RXSTAT_RUN_WAIT_PACKET indicating that the receive engine is waiting for the next packet.
EMAC_DMA_RXSTAT_SUSPENDED indicating that the receive engine is suspended due to the next descriptor being unavailable.
EMAC_DMA_RXSTAT_RUN_CLOSE_DESC indicating that the receive engine is closing the descriptor after receiving a buffer of data.
EMAC_DMA_RXSTAT_TS_WRITE indicating that the transmit engine is currently writing timestamp information to the descriptor.
EMAC_DMA_RXSTAT_RUN_RECEIVING indicating that the receive engine is currently transferring data from the MAC receive FIFO to memory.

Additionally, a DMA bus error may be signaled using EMAC_DMA_ERROR. If this flag is present, the source of the error is identified using one of the following values which may be extracted from the return value using EMAC_DMA_ERR_MASK:

EMAC_DMA_ERR_RX_DATA_WRITE indicates that an error occurred when writing received data to memory.
EMAC_DMA_ERR_TX_DATA_READ indicates that an error occurred when reading data from memory for transmission.
EMAC_DMA_ERR_RX_DESC_WRITE indicates that an error occurred when writing to the receive descriptor.
EMAC_DMA_ERR_TX_DESC_WRITE indicates that an error occurred when writing to the transmit descriptor.
EMAC_DMA_ERR_RX_DESC_READ indicates that an error occurred when reading the receive descriptor.
EMAC_DMA_ERR_TX_DESC_READ indicates that an error occurred when reading the transmit descriptor.

References EMAC_DMARIS_AE_M, EMAC_DMARIS_FBI, EMAC_DMARIS_RS_M, EMAC_DMARIS_TS_M, EMAC_O_DMARIS, and HWREG.

§ EMACTxFlush()

void EMACTxFlush ( uint32_t ui32Base )

Flushes the Ethernet controller transmit FIFO.

Parameters

ui32Base is the base address of the controller.

This function flushes any data currently held in the Ethernet transmit FIFO. Data that has already been passed to the MAC for transmission is transmitted, possibly resulting in a transmit underflow or runt frame transmission.

Returns: None.

References EMAC_DMAOPMODE_FTF, EMAC_O_DMAOPMODE, EMAC_O_STATUS, EMAC_STATUS_TXFE, and HWREG.

§ EMACTxEnable()

void EMACTxEnable ( uint32_t ui32Base )

Enables the Ethernet controller transmitter.

Parameters

ui32Base is the base address of the controller.

When starting operations on the Ethernet interface, this function should be called to enable the transmitter after all configuration has been completed.

Returns: None.

References EMAC_CFG_TE, EMAC_DMAOPMODE_ST, EMAC_O_CFG, EMAC_O_DMAOPMODE, and HWREG.

§ EMACTxDisable()

void EMACTxDisable ( uint32_t ui32Base )

Disables the Ethernet controller transmitter.

Parameters

ui32Base is the base address of the controller.

When terminating operations on the Ethernet interface, this function should be called. This function disables the transmitter.

Returns: None.

References EMAC_CFG_TE, EMAC_DMAOPMODE_ST, EMAC_O_CFG, EMAC_O_DMAOPMODE, and HWREG.

§ EMACRxEnable()

void EMACRxEnable ( uint32_t ui32Base )

Enables the Ethernet controller receiver.

Parameters

ui32Base is the base address of the controller.

When starting operations on the Ethernet interface, this function should be called to enable the receiver after all configuration has been completed.

Returns: None.

References EMAC_CFG_RE, EMAC_DMAOPMODE_SR, EMAC_O_CFG, EMAC_O_DMAOPMODE, and HWREG.

§ EMACRxDisable()

void EMACRxDisable ( uint32_t ui32Base )

Disables the Ethernet controller receiver.

Parameters

ui32Base is the base address of the controller.

When terminating operations on the Ethernet interface, this function should be called. This function disables the receiver.

Returns: None.

References EMAC_CFG_RE, EMAC_DMAOPMODE_SR, EMAC_O_CFG, EMAC_O_DMAOPMODE, and HWREG.

§ EMACIntRegister()

void EMACIntRegister	(	uint32_t	ui32Base,
		void(*)(void)	pfnHandler
	)

Registers an interrupt handler for an Ethernet interrupt.

Parameters

ui32Base	is the base address of the controller.
pfnHandler	is a pointer to the function to be called when the enabled Ethernet interrupts occur.

This function sets the handler to be called when the Ethernet interrupt occurs. This function enables the global interrupt in the interrupt controller; specific Ethernet interrupts must be enabled via EMACIntEnable(). It is the interrupt handler's responsibility to clear the interrupt source.

See also: IntRegister() for important information about registering interrupt handlers.

Returns: None.

References ASSERT, INT_EMAC0, IntEnable(), and IntRegister().

§ EMACIntUnregister()

void EMACIntUnregister ( uint32_t ui32Base )

Unregisters an interrupt handler for an Ethernet interrupt.

Parameters

ui32Base is the base address of the controller.

This function unregisters the interrupt handler. This function disables the global interrupt in the interrupt controller so that the interrupt handler is no longer called.

See also: IntRegister() for important information about registering interrupt handlers.

Returns: None.

References INT_EMAC0, IntDisable(), and IntUnregister().

§ EMACIntEnable()

void EMACIntEnable	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Enables individual Ethernet MAC interrupt sources.

Parameters

ui32Base	is the base address of the Ethernet MAC.
ui32IntFlags	is the bit mask of the interrupt sources to be enabled.

This function enables the indicated Ethernet MAC interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

The ui32IntFlags parameter is the logical OR of any of the following:

EMAC_INT_PHY indicates that the PHY has signaled a change of state. Software must read and write the appropriate PHY registers to enable and disable particular notifications.
EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the first data buffer of a packet.
EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and that the DMA engine has been disabled.
EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has been fully written from memory into the MAC transmit FIFO.
EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received.
EMAC_INT_RX_STOPPED indicates that the receive process has entered the stopped state.
EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer in the DMA's receive descriptor list and the DMA cannot, therefore, acquire a buffer. The receive process is suspended and can be resumed by changing the descriptor ownership and calling EMACRxDMAPollDemand().
EMAC_INT_RECEIVE indicates that reception of a frame has completed and all requested status has been written to the appropriate DMA receive descriptor.
EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an underflow during transmission. The transmit process is suspended.
EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced during reception.
EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. This condition occurs when the frame size exceeds 2048 bytes (or 10240 bytes in Jumbo Frame mode) and causes the transmit process to abort and enter the Stopped state.
EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer in the DMA's transmit descriptor list and that the DMA cannot, therefore, acquire a buffer. Transmission is suspended and can be resumed by changing the descriptor ownership and calling EMACTxDMAPollDemand().
EMAC_INT_TX_STOPPED indicates that the transmit process has stopped.
EMAC_INT_TRANSMIT indicates that transmission of a frame has completed and that all requested status has been updated in the descriptor.

Summary interrupt bits EMAC_INT_NORMAL_INT and EMAC_INT_ABNORMAL_INT are enabled automatically by the driver if any of their constituent sources are enabled. Applications do not need to explicitly enable these bits.

Note: Timestamp-related interrupts from the IEEE 1588 module must be enabled independently by using a call to EMACTimestampTargetIntEnable().

Returns: None.

References ASSERT, EMAC_ABNORMAL_INTS, EMAC_EPHYIM_INT, EMAC_INT_ABNORMAL_INT, EMAC_INT_NORMAL_INT, EMAC_INT_PHY, EMAC_MASKABLE_INTS, EMAC_NORMAL_INTS, EMAC_O_DMAIM, EMAC_O_EPHYIM, and HWREG.

§ EMACIntDisable()

void EMACIntDisable	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Disables individual Ethernet MAC interrupt sources.

Parameters

ui32Base	is the base address of the Ethernet MAC.
ui32IntFlags	is the bit mask of the interrupt sources to be disabled.

This function disables the indicated Ethernet MAC interrupt sources.

The ui32IntFlags parameter is the logical OR of any of the following:

EMAC_INT_PHY indicates that the PHY has signaled a change of state. Software must read and write the appropriate PHY registers to enable and disable particular notifications.
EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the first data buffer of a packet.
EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and that the DMA engine has been disabled.
EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has been fully written from memory into the MAC transmit FIFO.
EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received.
EMAC_INT_RX_STOPPED indicates that the receive process has entered the stopped state.
EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer in the DMA's receive descriptor list and the DMA cannot, therefore, acquire a buffer. The receive process is suspended and can be resumed by changing the descriptor ownership and calling EMACRxDMAPollDemand().
EMAC_INT_RECEIVE indicates that reception of a frame has completed and all requested status has been written to the appropriate DMA receive descriptor.
EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an underflow during transmission. The transmit process is suspended.
EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced during reception.
EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. This condition occurs when the frame size exceeds 2048 bytes (or 10240 bytes in Jumbo Frame mode) and causes the transmit process to abort and enter the Stopped state.
EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer in the DMA's transmit descriptor list and that the DMA cannot, therefore, acquire a buffer. Transmission is suspended and can be resumed by changing the descriptor ownership and calling EMACTxDMAPollDemand().
EMAC_INT_TX_STOPPED indicates that the transmit process has stopped.
EMAC_INT_TRANSMIT indicates that transmission of a frame has completed and that all requested status has been updated in the descriptor.
EMAC_INT_TIMESTAMP indicates that an interrupt from the timestamp module has occurred. This precise source of the interrupt can be determined by calling EMACTimestampIntStatus(), which also clears this bit.

Summary interrupt bits EMAC_INT_NORMAL_INT and EMAC_INT_ABNORMAL_INT are disabled automatically by the driver if none of their constituent sources are enabled. Applications do not need to explicitly disable these bits.

Note: Timestamp-related interrupts from the IEEE 1588 module must be disabled independently by using a call to EMACTimestampTargetIntDisable().

Returns: None.

References ASSERT, EMAC_ABNORMAL_INTS, EMAC_EPHYIM_INT, EMAC_INT_ABNORMAL_INT, EMAC_INT_NORMAL_INT, EMAC_INT_PHY, EMAC_MASKABLE_INTS, EMAC_NORMAL_INTS, EMAC_O_DMAIM, EMAC_O_EPHYIM, and HWREG.

§ EMACIntStatus()

uint32_t EMACIntStatus	(	uint32_t	ui32Base,
		bool	bMasked
	)

Gets the current Ethernet MAC interrupt status.

Parameters

ui32Base	is the base address of the Ethernet MAC.
bMasked	is true to return the masked interrupt status or false to return the unmasked status.

This function returns the interrupt status for the Ethernet MAC. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Returns: Returns the current interrupt status as the logical OR of any of the following:

EMAC_INT_PHY indicates that the PHY interrupt has occurred. Software must read the relevant PHY interrupt status register to determine the cause.
EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the first data buffer of a packet.
EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and that the DMA engine has been disabled. The cause of the error can be determined by calling EMACDMAStateGet().
EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has been fully written from memory into the MAC transmit FIFO.
EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received.
EMAC_INT_RX_STOPPED indicates that the receive process has entered the stopped state.
EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer in the DMA's receive descriptor list and the DMA cannot, therefore, acquire a buffer. The receive process is suspended and can be resumed by changing the descriptor ownership and calling EMACRxDMAPollDemand().
EMAC_INT_RECEIVE indicates that reception of a frame has completed and all requested status has been written to the appropriate DMA receive descriptor.
EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an underflow during transmission. The transmit process is suspended.
EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced during reception.
EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. This condition occurs when the frame size exceeds 2048 bytes (or 10240 bytes in Jumbo Frame mode) and causes the transmit process to abort and enter the Stopped state.
EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer in the DMA's transmit descriptor list and that the DMA cannot, therefore, acquire a buffer. Transmission is suspended and can be resumed by changing the descriptor ownership and calling EMACTxDMAPollDemand().
EMAC_INT_TX_STOPPED indicates that the transmit process has stopped.
EMAC_INT_TRANSMIT indicates that transmission of a frame has completed and that all requested status has been updated in the descriptor.
EMAC_INT_NORMAL_INT is a summary interrupt comprising the logical OR of the masked state of EMAC_INT_TRANSMIT, EMAC_INT_RECEIVE, EMAC_INT_TX_NO_BUFFER and EMAC_INT_EARLY_RECEIVE.
EMAC_INT_ABNORMAL_INT is a summary interrupt comprising the logical OR of the masked state of EMAC_INT_TX_STOPPED, EMAC_INT_TX_JABBER, EMAC_INT_RX_OVERFLOW, EMAC_INT_TX_UNDERFLOW, EMAC_INT_RX_NO_BUFFER, EMAC_INT_RX_STOPPED, EMAC_INT_RX_WATCHDOG, EMAC_INT_EARLY_TRANSMIT and EMAC_INT_BUS_ERROR.

References ASSERT, EMAC_DMARIS_AE_M, EMAC_DMARIS_RS_M, EMAC_DMARIS_TS_M, EMAC_EPHYMISC_INT, EMAC_INT_PHY, EMAC_NON_MASKED_INTS, EMAC_O_DMAIM, EMAC_O_DMARIS, EMAC_O_EPHYMISC, EMAC_O_EPHYRIS, and HWREG.

§ EMACIntClear()

void EMACIntClear	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Clears individual Ethernet MAC interrupt sources.

Parameters

ui32Base	is the base address of the Ethernet MAC.
ui32IntFlags	is the bit mask of the interrupt sources to be cleared.

This function disables the indicated Ethernet MAC interrupt sources.

The ui32IntFlags parameter is the logical OR of any of the following:

EMAC_INT_PHY indicates that the PHY has signaled a change of state. Software must read and write the appropriate PHY registers to enable, disable and clear particular notifications.
EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the first data buffer of a packet.
EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and that the DMA engine has been disabled.
EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has been fully written from memory into the MAC transmit FIFO.
EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received.
EMAC_INT_RX_STOPPED indicates that the receive process has entered the stopped state.
EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer in the DMA's receive descriptor list and the DMA cannot, therefore, acquire a buffer. The receive process is suspended and can be resumed by changing the descriptor ownership and calling EMACRxDMAPollDemand().
EMAC_INT_RECEIVE indicates that reception of a frame has completed and all requested status has been written to the appropriate DMA receive descriptor.
EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an underflow during transmission. The transmit process is suspended.
EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced during reception.
EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. This condition occurs when the frame size exceeds 2048 bytes (or 10240 bytes in Jumbo Frame mode) and causes the transmit process to abort and enter the Stopped state.
EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer in the DMA's transmit descriptor list and that the DMA cannot, therefore, acquire a buffer. Transmission is suspended and can be resumed by changing the descriptor ownership and calling EMACTxDMAPollDemand().
EMAC_INT_TX_STOPPED indicates that the transmit process has stopped.
EMAC_INT_TRANSMIT indicates that transmission of a frame has completed and that all requested status has been updated in the descriptor.

Summary interrupt bits EMAC_INT_NORMAL_INT and EMAC_INT_ABNORMAL_INT are cleared automatically by the driver if any of their constituent sources are cleared. Applications do not need to explicitly clear these bits.

Returns: None.

References ASSERT, EMAC_ABNORMAL_INTS, EMAC_EPHYMISC_INT, EMAC_INT_ABNORMAL_INT, EMAC_INT_NORMAL_INT, EMAC_INT_PHY, EMAC_NORMAL_INTS, EMAC_O_DMARIS, EMAC_O_EPHYMISC, and HWREG.

§ EMACPHYWrite()

void EMACPHYWrite	(	uint32_t	ui32Base,
		uint8_t	ui8PhyAddr,
		uint8_t	ui8RegAddr,
		uint16_t	ui16Data
	)

Writes to the PHY register.

Parameters

ui32Base	is the base address of the controller.
ui8PhyAddr	is the physical address of the PHY to access.
ui8RegAddr	is the address of the PHY register to be accessed.
ui16Data	is the data to be written to the PHY register.

This function writes the ui16Data value to the PHY register specified by ui8RegAddr.

Returns: None.

References ASSERT, EMAC_MIIADDR_CR_M, EMAC_MIIADDR_MII_S, EMAC_MIIADDR_MIIB, EMAC_MIIADDR_MIIW, EMAC_MIIADDR_PLA_S, EMAC_O_MIIADDR, EMAC_O_MIIDATA, and HWREG.

Referenced by EMACPHYExtendedRead(), EMACPHYExtendedWrite(), EMACPHYMMDRead(), EMACPHYMMDWrite(), EMACPHYPowerOff(), and EMACPHYPowerOn().

§ EMACPHYRead()

uint16_t EMACPHYRead	(	uint32_t	ui32Base,
		uint8_t	ui8PhyAddr,
		uint8_t	ui8RegAddr
	)

Reads from a PHY register.

Parameters

ui32Base	is the base address of the controller.
ui8PhyAddr	is the physical address of the PHY to access.
ui8RegAddr	is the address of the PHY register to be accessed.

This function returns the contents of the PHY register specified by ui8RegAddr.

Returns: Returns the 16-bit value read from the PHY.

References ASSERT, EMAC_MIIADDR_CR_M, EMAC_MIIADDR_MII_S, EMAC_MIIADDR_MIIB, EMAC_MIIADDR_PLA_S, EMAC_MIIDATA_DATA_M, EMAC_O_MIIADDR, EMAC_O_MIIDATA, and HWREG.

Referenced by EMACPHYExtendedRead(), EMACPHYMMDRead(), EMACPHYPowerOff(), and EMACPHYPowerOn().

§ EMACPHYExtendedRead()

uint16_t EMACPHYExtendedRead	(	uint32_t	ui32Base,
		uint8_t	ui8PhyAddr,
		uint16_t	ui16RegAddr
	)

Reads from an extended PHY register.

Parameters

ui32Base	is the base address of the controller.
ui8PhyAddr	is the physical address of the PHY to access.
ui16RegAddr	is the address of the PHY extended register to be accessed.

When using the internal PHY or when connected to an external PHY supporting extended registers, this function returns the contents of the extended PHY register specified by ui16RegAddr.

Returns: Returns the 16-bit value read from the PHY.

References ASSERT, EMACPHYRead(), EMACPHYWrite(), EPHY_ADDAR, and EPHY_REGCTL.

§ EMACPHYExtendedWrite()

void EMACPHYExtendedWrite	(	uint32_t	ui32Base,
		uint8_t	ui8PhyAddr,
		uint16_t	ui16RegAddr,
		uint16_t	ui16Value
	)

Writes a value to an extended PHY register.

Parameters

ui32Base	is the base address of the controller.
ui8PhyAddr	is the physical address of the PHY to access.
ui16RegAddr	is the address of the PHY extended register to be accessed.
ui16Value	is the value to write to the register.

When using the internal PHY or when connected to an external PHY supporting extended registers, this function allows a value to be written to the extended PHY register specified by ui16RegAddr.

Returns: None.

References ASSERT, EMACPHYWrite(), EPHY_ADDAR, and EPHY_REGCTL.

§ EMACPHYPowerOff()

void EMACPHYPowerOff	(	uint32_t	ui32Base,
		uint8_t	ui8PhyAddr
	)

Powers off the Ethernet PHY.

Parameters

ui32Base	is the base address of the controller.
ui8PhyAddr	is the physical address of the PHY to power down.

This function powers off the Ethernet PHY, reducing the current consumption of the device. While in the powered-off state, the Ethernet controller is unable to connect to Ethernet.

Returns: None.

References EMACPHYRead(), EMACPHYWrite(), EPHY_BMCR, EPHY_BMCR_ANEN, and EPHY_BMCR_PWRDWN.

§ EMACPHYPowerOn()

void EMACPHYPowerOn	(	uint32_t	ui32Base,
		uint8_t	ui8PhyAddr
	)

Powers on the Ethernet PHY.

Parameters

ui32Base	is the base address of the controller.
ui8PhyAddr	is the physical address of the PHY to power up.

This function powers on the Ethernet PHY, enabling it return to normal operation. By default, the PHY is powered on, so this function is only called if EMACPHYPowerOff() has previously been called.

Returns: None.

References EMACPHYRead(), EMACPHYWrite(), EPHY_BMCR, EPHY_BMCR_ANEN, and EPHY_BMCR_PWRDWN.

§ EMACTimestampConfigSet()

void EMACTimestampConfigSet	(	uint32_t	ui32Base,
		uint32_t	ui32Config,
		uint32_t	ui32SubSecondInc
	)

Configures the Ethernet MAC's IEEE 1588 timestamping options.

Parameters

ui32Base	is the base address of the controller.
ui32Config	contains flags selecting particular configuration options.
ui32SubSecondInc	is the number that the IEEE 1588 subsecond clock should increment on each tick.

This function is used to configure the operation of the Ethernet MAC's internal timestamping clock. This clock is used to timestamp incoming and outgoing packets and as an accurate system time reference when IEEE 1588 Precision Time Protocol is in use.

The ui32Config parameter contains a collection of flags selecting the desired options. Valid flags are:

One of the following to determine whether IEEE 1588 version 1 or version 2 packet format is to be processed:

EMAC_TS_PTP_VERSION_2
EMAC_TS_PTP_VERSION_1

One of the following to determine how the IEEE 1588 clock's subsecond value should be interpreted and handled:

EMAC_TS_DIGITAL_ROLLOVER causes the clock's subsecond value to roll over at 0x3BA9C9FF (999999999 decimal). In this mode, it can be considered as a nanosecond counter with each digit representing 1 ns.
EMAC_TS_BINARY_ROLLOVER causes the clock's subsecond value to roll over at 0x7FFFFFFF. In this mode, the subsecond value counts 0.465 ns periods.

One of the following to enable or disable MAC address filtering. When enabled, PTP frames are filtered unless the destination MAC address matches any of the currently programmed MAC addresses.

EMAC_TS_MAC_FILTER_ENABLE
EMAC_TS_MAC_FILTER_DISABLE

One of the following to determine how the clock is updated:

EMAC_TS_UPDATE_COARSE causes the IEEE 1588 clock to advance by the value supplied in the ui32SubSecondInc parameter on each main oscillator clock cycle.
EMAC_TS_UPDATE_FINE selects the fine update method which causes the IEEE 1588 clock to advance by the the value supplied in the ui32SubSecondInc parameter each time a carry is generated from the addend accumulator register.

One of the following to determine which IEEE 1588 messages are timestamped:

EMAC_TS_SYNC_FOLLOW_DREQ_DRESP timestamps SYNC, Follow_Up, Delay_Req and Delay_Resp messages.
EMAC_TS_SYNC_ONLY timestamps only SYNC messages.
EMAC_TS_DELAYREQ_ONLY timestamps only Delay_Req messages.
EMAC_TS_ALL timestamps all IEEE 1588 messages.
EMAC_TS_SYNC_PDREQ_PDRESP timestamps only SYNC, Pdelay_Req and Pdelay_Resp messages.
EMAC_TS_DREQ_PDREQ_PDRESP timestamps only Delay_Req, Pdelay_Req and Pdelay_Resp messages.
EMAC_TS_SYNC_DELAYREQ timestamps only Delay_Req messages.
EMAC_TS_PDREQ_PDRESP timestamps only Pdelay_Req and Pdelay_Resp messages.

Optional, additional flags are:

EMAC_TS_PROCESS_IPV4_UDP processes PTP packets encapsulated in UDP over IPv4 packets. If absent, the MAC ignores these frames.
EMAC_TS_PROCESS_IPV6_UDP processes PTP packets encapsulated in UDP over IPv6 packets. If absent, the MAC ignores these frames.
EMAC_TS_PROCESS_ETHERNET processes PTP packets encapsulated directly in Ethernet frames. If absent, the MAC ignores these frames.
EMAC_TS_ALL_RX_FRAMES enables timestamping for all frames received by the MAC, regardless of type.

The ui32SubSecondInc controls the rate at which the timestamp clock's subsecond count increments. Its meaning depends on which of EMAC_TS_DIGITAL_ROLLOVER or EMAC_TS_BINARY_ROLLOVER and EMAC_TS_UPDATE_FINE or EMAC_TS_UPDATE_COARSE were included in ui32Config.

The timestamp second counter is incremented each time the subsecond counter rolls over. In digital rollover mode, the subsecond counter acts as a simple 31-bit counter, rolling over to 0 after reaching 0x7FFFFFFF. In this case, each lsb of the subsecond counter represents 0.465 ns (assuming the definition of 1 second resolution for the seconds counter). When binary rollover mode is selected, the subsecond counter acts as a nanosecond counter and rolls over to 0 after reaching 999,999,999 making each lsb represent 1 nanosecond.

In coarse update mode, the timestamp subsecond counter is incremented by ui32SubSecondInc on each main oscillator clock tick. Setting ui32SubSecondInc to the main oscillator clock period in either 1 ns or 0.465 ns units ensures that the time stamp, read as seconds and subseconds, increments at the same rate as the main oscillator clock. For example, if the main oscillator is 25 MHz, ui32SubSecondInc is set to 40 if digital rollover mode is selected or (40 / 0.465) = 86 in binary rollover mode.

In fine update mode, the subsecond increment value must be set according to the desired accuracy of the recovered IEEE 1588 clock which must be lower than the system clock rate. Fine update mode is typically used when synchronizing the local clock to the IEEE 1588 master clock. The subsecond counter is incremented by ui32SubSecondInc counts each time a 32-bit accumulator register generates a carry. The accumulator register is incremented by the addend value on each main oscillator tick and this addend value is modified to allow fine control over the rate of change of the timestamp counter. The addend value is calculated using the ratio of the main oscillator clock rate and the desired IEEE 1588 clock rate and the ui32SubSecondInc value is set to correspond to the desired IEEE 1588 clock rate. As an example, using digital rollover mode and a 25-MHz main oscillator clock with a desired IEEE 1588 clock accuracy of 12.5 MHz, we would set ui32SubSecondInc to the 12.5-MHz clock period of 80 ns and set the initial addend value to 0x80000000 to generate a carry on every second system clock.

See also: EMACTimestampAddendSet()

Returns: None.

References ASSERT, EMAC_CC_PTPCEN, EMAC_O_CC, EMAC_O_SUBSECINC, EMAC_O_TIMSTCTRL, EMAC_SUBSECINC_SSINC_M, EMAC_SUBSECINC_SSINC_S, and HWREG.

§ EMACTimestampConfigGet()

uint32_t EMACTimestampConfigGet	(	uint32_t	ui32Base,
		uint32_t *	pui32SubSecondInc
	)

Returns the current IEEE 1588 timestamping configuration.

Parameters

ui32Base	is the base address of the controller.
pui32SubSecondInc	points to storage that is written with the current subsecond increment value for the IEEE 1588 clock.

This function may be used to retreive the current MAC timestamping configuration.

See also: EMACTimestampConfigSet()

Returns: Returns the current timestamping configuration as a logical OR of the following flags:

EMAC_TS_PTP_VERSION_2 indicates that the MAC is processing PTP version 2 messages. If this flag is absent, PTP version 1 messages are expected.
EMAC_TS_DIGITAL_ROLLOVER causes the clock's subsecond value to roll over at 0x3BA9C9FF (999999999 decimal). In this mode, it can be considered as a nanosecond counter with each digit representing 1 ns. If this flag is absent, the subsecond value rolls over at 0x7FFFFFFF, effectively counting increments of 0.465 ns.
EMAC_TS_MAC_FILTER_ENABLE indicates that incoming PTP messages are filtered using any of the configured MAC addresses. Messages with a destination address programmed into the MAC address filter are passed, others are discarded. If this flag is absent, the MAC address is ignored.
EMAC_TS_UPDATE_FINE implements the fine update method that causes the IEEE 1588 clock to advance by the the value returned in the *pui32SubSecondInc parameter each time a carry is generated from the addend accumulator register. If this flag is absent, the coarse update method is in use and the clock is advanced by the *pui32SubSecondInc value on each system clock tick.
EMAC_TS_SYNC_ONLY indicates that timestamps are only generated for SYNC messages.
EMAC_TS_DELAYREQ_ONLY indicates that timestamps are only generated for Delay_Req messages.
EMAC_TS_ALL indicates that timestamps are generated for all IEEE 1588 messages.
EMAC_TS_SYNC_PDREQ_PDRESP timestamps only SYNC, Pdelay_Req and Pdelay_Resp messages.
EMAC_TS_DREQ_PDREQ_PDRESP indicates that timestamps are only generated for Delay_Req, Pdelay_Req and Pdelay_Resp messages.
EMAC_TS_SYNC_DELAYREQ indicates that timestamps are only generated for Delay_Req messages.
EMAC_TS_PDREQ_PDRESP indicates that timestamps are only generated for Pdelay_Req and Pdelay_Resp messages.
EMAC_TS_PROCESS_IPV4_UDP indicates that PTP packets encapsulated in UDP over IPv4 packets are being processed. If absent, the MAC ignores these frames.
EMAC_TS_PROCESS_IPV6_UDP indicates that PTP packets encapsulated in UDP over IPv6 packets are being processed. If absent, the MAC ignores these frames.
EMAC_TS_PROCESS_ETHERNET indicates that PTP packets encapsulated directly in Ethernet frames are being processd. If absent, the MAC ignores these frames.
EMAC_TS_ALL_RX_FRAMES indicates that timestamping is enabled for all frames received by the MAC, regardless of type.

If EMAC_TS_ALL_RX_FRAMES and none of the options specifying subsets of PTP packets to timestamp are set, the MAC is configured to timestamp SYNC, Follow_Up, Delay_Req and Delay_Resp messages only.

References ASSERT, EMAC_O_SUBSECINC, EMAC_O_TIMSTCTRL, EMAC_SUBSECINC_SSINC_M, EMAC_SUBSECINC_SSINC_S, and HWREG.

§ EMACTimestampEnable()

void EMACTimestampEnable ( uint32_t ui32Base )

Enables packet timestamping and starts the system clock running.

Parameters

ui32Base is the base address of the controller.

This function is used to enable the system clock used to timestamp Ethernet frames and to enable that timestamping.

Returns: None.

References ASSERT, EMAC_O_TIMSTCTRL, EMAC_TIMSTCTRL_TSEN, EMAC_TIMSTCTRL_TSINIT, and HWREG.

§ EMACTimestampDisable()

void EMACTimestampDisable ( uint32_t ui32Base )

Disables packet timestamping and stops the system clock.

Parameters

ui32Base is the base address of the controller.

This function is used to stop the system clock used to timestamp Ethernet frames and to disable timestamping.

Returns: None.

References ASSERT, EMAC_O_TIMSTCTRL, EMAC_TIMSTCTRL_TSEN, and HWREG.

§ EMACTimestampSysTimeSet()

void EMACTimestampSysTimeSet	(	uint32_t	ui32Base,
		uint32_t	ui32Seconds,
		uint32_t	ui32SubSeconds
	)

Sets the current system time.

Parameters

ui32Base	is the base address of the controller.
ui32Seconds	is the seconds value of the new system clock setting.
ui32SubSeconds	is the subseconds value of the new system clock setting.

This function may be used to set the current system time. The system clock is set to the value passed in the ui32Seconds and ui32SubSeconds parameters.

The meaning of ui32SubSeconds depends on the current system time configuration. If EMACTimestampConfigSet() was previously called with the EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the ui32SubSeconds value represents 1 ns. If EMAC_TS_BINARY_ROLLOVER was specified instead, a ui32SubSeconds bit represents 0.46 ns.

Returns: None.

References ASSERT, EMAC_O_TIMNANOU, EMAC_O_TIMSECU, EMAC_O_TIMSTCTRL, EMAC_TIMSTCTRL_TSINIT, and HWREG.

§ EMACTimestampSysTimeGet()

void EMACTimestampSysTimeGet	(	uint32_t	ui32Base,
		uint32_t *	pui32Seconds,
		uint32_t *	pui32SubSeconds
	)

Gets the current system time.

Parameters

ui32Base	is the base address of the controller.
pui32Seconds	points to storage for the current seconds value.
pui32SubSeconds	points to storage for the current subseconds value.

This function may be used to get the current system time.

The meaning of ui32SubSeconds depends on the current system time configuration. If EMACTimestampConfigSet() was previously called with the EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the ui32SubSeconds value represents 1 ns. If EMAC_TS_BINARY_ROLLOVER was specified instead, a ui32SubSeconds bit represents 0.46 ns.

Returns: None.

References ASSERT, EMAC_O_TIMNANO, EMAC_O_TIMSEC, and HWREG.

§ EMACTimestampSysTimeUpdate()

void EMACTimestampSysTimeUpdate	(	uint32_t	ui32Base,
		uint32_t	ui32Seconds,
		uint32_t	ui32SubSeconds,
		bool	bInc
	)

Adjusts the current system time upwards or downwards by a given amount.

Parameters

ui32Base	is the base address of the controller.
ui32Seconds	is the seconds value of the time update to apply.
ui32SubSeconds	is the subseconds value of the time update to apply.
bInc	defines the direction of the update.

This function may be used to adjust the current system time either upwards or downwards by a given amount. The size of the adjustment is given by the ui32Seconds and ui32SubSeconds parameter and the direction by the bInc parameter. When bInc is true, the system time is advanced by the interval given. When it is false, the time is retarded by the interval.

The meaning of ui32SubSeconds depends on the current system time configuration. If EMACTimestampConfigSet() was previously called with the EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the subsecond value represents 1 ns. If EMAC_TS_BINARY_ROLLOVER was specified instead, a subsecond bit represents 0.46 ns.

Returns: None.

References ASSERT, EMAC_O_TIMNANOU, EMAC_O_TIMSECU, EMAC_O_TIMSTCTRL, EMAC_TIMNANOU_ADDSUB, EMAC_TIMSTCTRL_TSUPDT, and HWREG.

§ EMACTimestampAddendSet()

void EMACTimestampAddendSet	(	uint32_t	ui32Base,
		uint32_t	ui32Increment
	)

Adjusts the system time update rate when using the fine correction method.

Parameters

ui32Base	is the base address of the controller.
ui32Increment	is the number to add to the accumulator register on each tick of the 25-MHz main oscillator.

This function is used to control the rate of update of the system time when in fine update mode. Fine correction mode is selected if EMAC_TS_UPDATE_FINE is supplied in the ui32Config parameter passed to a previous call to EMACTimestampConfigSet(). Fine update mode is typically used when synchronizing the local clock to the IEEE 1588 master clock. The subsecond counter is incremented by the number passed to EMACTimestampConfigSet() in the ui32SubSecondInc parameter each time a 32-bit accumulator register generates a carry. The accumulator register is incremented by the "addend" value on each main oscillator tick, and this addend value is modified to allow fine control over the rate of change of the timestamp counter. The addend value is calculated using the ratio of the main oscillator clock rate and the desired IEEE 1588 clock rate and the ui32SubSecondInc value is set to correspond to the desired IEEE 1588 clock rate.

As an example, using digital rollover mode and a 25-MHz main oscillator clock with a desired IEEE 1588 clock accuracy of 12.5 MHz, and having made a previous call to EMACTimestampConfigSet() with ui32SubSecondInc set to the 12.5-MHz clock period of 80 ns, the initial ui32Increment value would be set to 0x80000000 to generate a carry on every second main oscillator tick. Because the system time updates each time the accumulator overflows, small changes in the ui32Increment value can be used to very finely control the system time rate.

Returns: None.

See also: EMACTimestampConfigSet()

References ASSERT, EMAC_O_TIMADD, EMAC_O_TIMSTCTRL, EMAC_TIMSTCTRL_ADDREGUP, and HWREG.

§ EMACTimestampTargetSet()

void EMACTimestampTargetSet	(	uint32_t	ui32Base,
		uint32_t	ui32Seconds,
		uint32_t	ui32SubSeconds
	)

Sets the target system time at which the next Ethernet timer interrupt is generated.

Parameters

ui32Base	is the base address of the controller.
ui32Seconds	is the second value of the desired target time.
ui32SubSeconds	is the subseconds value of the desired target time.

This function may be used to schedule an interrupt at some future time. The time reference for the function is the IEEE 1588 time as returned by EMACTimestampSysTimeGet(). To generate an interrupt when the system time exceeds a given value, call this function to set the desired time, then EMACTimestampTargetIntEnable() to enable the interrupt. When the system time increments past the target time, an Ethernet interrupt with status EMAC_INT_TIMESTAMP is generated.

The accuracy of the interrupt timing depends on the Ethernet timer update frequency and the subsecond increment value currently in use. The interrupt is generated on the first timer increment that causes the system time to be greater than or equal to the target time set.

Returns: None.

References ASSERT, EMAC_O_TARGNANO, EMAC_O_TARGSEC, EMAC_TARGNANO_TRGTBUSY, and HWREG.

§ EMACTimestampTargetIntEnable()

void EMACTimestampTargetIntEnable ( uint32_t ui32Base )

Enables the Ethernet system time interrupt.

Parameters

ui32Base is the base address of the controller.

This function may be used after EMACTimestampTargetSet() to schedule an interrupt at some future time. The time reference for the function is the IEEE 1588 time as returned by EMACTimestampSysTimeGet(). To generate an interrupt when the system time exceeds a given value, call this function to set the desired time, then EMACTimestampTargetIntEnable() to enable the interrupt. When the system time increments past the target time, an Ethernet interrupt with status EMAC_INT_TIMESTAMP is generated.

Returns: None.

References ASSERT, EMAC_O_TIMSTCTRL, EMAC_TIMSTCTRL_INTTRIG, and HWREG.

§ EMACTimestampTargetIntDisable()

void EMACTimestampTargetIntDisable ( uint32_t ui32Base )

Disables the Ethernet system time interrupt.

Parameters

ui32Base is the base address of the controller.

This function may be used to disable any pending Ethernet system time interrupt previously scheduled using calls to EMACTimestampTargetSet() and EMACTimestampTargetIntEnable().

Returns: None.

References ASSERT, EMAC_O_TIMSTCTRL, EMAC_TIMSTCTRL_INTTRIG, and HWREG.

§ EMACTimestampIntStatus()

uint32_t EMACTimestampIntStatus ( uint32_t ui32Base )

Reads the status of the Ethernet system time interrupt.

Parameters

ui32Base is the base address of the controller.

When an Ethernet interrupt occurs and EMAC_INT_TIMESTAMP is reported bu EMACIntStatus(), this function must be called to read and clear the timer interrupt status.

Returns: The return value is the logical OR of the values EMAC_TS_INT_TS_SEC_OVERFLOW and EMAC_TS_INT_TARGET_REACHED.

EMAC_TS_INT_TS_SEC_OVERFLOW indicates that the second counter in the hardware timer has rolled over.
EMAC_TS_INT_TARGET_REACHED indicates that the system time incremented past the value set in an earlier call to EMACTimestampTargetSet(). When this occurs, a new target time may be set and the interrupt re-enabled using calls to EMACTimestampTargetSet() and EMACTimestampTargetIntEnable().

References ASSERT, EMAC_O_TIMSTAT, and HWREG.

§ EMACTimestampPPSSimpleModeSet()

void EMACTimestampPPSSimpleModeSet	(	uint32_t	ui32Base,
		uint32_t	ui32FreqConfig
	)

Configures the Ethernet MAC PPS output in simple mode.

Parameters

ui32Base	is the base address of the controller.
ui32FreqConfig	determines the frequency of the output generated on the PPS pin.

This function configures the Ethernet MAC PPS (Pulse Per Second) engine to operate in its simple mode which allows the generation of a few, fixed frequencies and pulse widths on the PPS pin. If more complex pulse train generation is required, the MAC also provides a command-based PPS control mode that can be selected by calling EMACTimestampPPSCommandModeSet().

The ui32FreqConfig parameter may take one of the following values:

EMAC_PPS_SINGLE_PULSE generates a single high pulse on the PPS output once per second. The pulse width is the same as the system clock period.
EMAC_PPS_1HZ generates a 1Hz signal on the PPS output. This option is not available if the system time subsecond counter is currently configured to operate in binary rollover mode.
EMAC_PPS_2HZ, EMAC_PPS_4HZ, EMAC_PPS_8HZ, EMAC_PPS_16HZ, EMAC_PPS_32HZ, EMAC_PPS_64HZ, EMAC_PPS_128HZ, EMAC_PPS_256HZ, EMAC_PPS_512HZ, EMAC_PPS_1024HZ, EMAC_PPS_2048HZ, EMAC_PPS_4096HZ, EMAC_PPS_8192HZ, EMAC_PPS_16384HZ generate the requested frequency on the PPS output in both binary and digital rollover modes.
EMAC_PPS_32768HZ generates a 32KHz signal on the PPS output. This option is not available if the system time subsecond counter is currently configured to operate in digital rollover mode.

Except when EMAC_PPS_SINGLE_PULSE is specified, the signal generated on PPS has a duty cycle of 50% when binary rollover mode is used for the system time subsecond count. In digital mode, the output frequency averages the value requested and is resynchronized each second. For example, if EMAC_PPS_4HZ is selected in digital rollover mode, the output generates three clocks with 50 percent duty cycle and 268 ms period followed by a fourth clock of 195 ms period, 134 ms low and 61 ms high.

Returns: None.

References ASSERT, EMAC_O_PPSCTRL, EMAC_O_TIMSTCTRL, EMAC_PPS_1HZ, EMAC_PPS_32768HZ, EMAC_PPS_SINGLE_PULSE, EMAC_TS_DIGITAL_ROLLOVER, and HWREG.

§ EMACTimestampPPSCommandModeSet()

void EMACTimestampPPSCommandModeSet	(	uint32_t	ui32Base,
		uint32_t	ui32Config
	)

Configures the Ethernet MAC PPS output in command mode.

Parameters

ui32Base	is the base address of the controller.
ui32Config	determines how the system target time is used.

The simple mode of operation offered by the PPS (Pulse Per Second) engine may be too restrictive for some applications. The second mode, however, allows complex pulse trains to be generated using commands that tell the engine to send individual pulses or start and stop trains if pulses. In this mode, the pulse width and period may be set arbitrarily based on ticks of the clock used to update the system time. Commands are triggered at specific times using the target time last set using a call to EMACTimestampTargetSet().

The ui32Config parameter may be used to control whether the target time is used to trigger commands only or can also generate an interrupt to the CPU. Valid values are:

EMAC_PPS_TARGET_INT configures the target time to only raise an interrupt and not to trigger any pending PPS command.
EMAC_PPS_TARGET_PPS configures the target time to trigger a pending PPS command but not raise an interrupt.
EMAC_PPS_TARGET_BOTH configures the target time to trigger any pending PPS command and also raise an interrupt.

To use command mode, an application must call this function to enable the mode, then call:

EMACTimestampPPSPeriodSet() to set the desired pulse width and period then
EMACTimestampTargetSet() to set the time at which the next command is executed, and finally
EMACTimestampPPSCommand() to send a command to cause the pulse or pulse train to be started at the required time.

Returns: None.

References ASSERT, EMAC_O_PPSCTRL, EMAC_PPS_TARGET_BOTH, EMAC_PPS_TARGET_INT, EMAC_PPS_TARGET_PPS, EMAC_PPSCTRL_PPSCTRL_M, EMAC_PPSCTRL_PPSEN0, and HWREG.

§ EMACTimestampPPSCommand()

void EMACTimestampPPSCommand	(	uint32_t	ui32Base,
		uint8_t	ui8Cmd
	)

Sends a command to control the PPS output from the Ethernet MAC.

Parameters

ui32Base	is the base address of the controller.
ui8Cmd	identifies the command to be sent.

This function may be used to send a command to the MAC PPS (Pulse Per Second) controller when it is operating in command mode. Command mode is selected by calling EMACTimestampPPSCommandModeSet(). Valid commands are as follow:

EMAC_PPS_COMMAND_NONE indicates no command.
EMAC_PPS_COMMAND_START_SINGLE indicates that a single high pulse should be generated when the system time reaches the current target time.
EMAC_PPS_COMMAND_START_TRAIN indicates that a train of pulses should be started when the system time reaches the current target time.
EMAC_PPS_COMMAND_CANCEL_START cancels any pending start command if the system time has not yet reached the programmed target time.
EMAC_PPS_COMMAND_STOP_AT_TIME indicates that the current pulse train should be stopped when the system time reaches the current target time.
EMAC_PPS_COMMAND_STOP_NOW indicates that the current pulse train should be stopped immediately.
EMAC_PPS_COMMAND_CANCEL_STOP cancels any pending stop command if the system time has not yet reached the programmed target time.

In all cases, the width of the pulses generated is governed by the ui32Width parameter passed to EMACTimestampPPSPeriodSet(). If a command starts a train of pulses, the period of the pulses is governed by the ui32Period parameter passed to the same function. Target times associated with PPS commands are set by calling EMACTimestampTargetSet().

Returns: None.

References ASSERT, EMAC_O_PPSCTRL, EMAC_PPSCTRL_PPSCTRL_M, EMAC_PPSCTRL_PPSEN0, and HWREG.

§ EMACTimestampPPSPeriodSet()

void EMACTimestampPPSPeriodSet	(	uint32_t	ui32Base,
		uint32_t	ui32Period,
		uint32_t	ui32Width
	)

Sets the period and width of the pulses on the Ethernet MAC PPS output.

Parameters

ui32Base	is the base address of the controller.
ui32Period	is the period of the PPS output expressed in terms of system time update ticks.
ui32Width	is the width of the high portion of the PPS output expressed in terms of system time update ticks.

This function may be used to control the period and duty cycle of the signal output on the Ethernet MAC PPS pin when the PPS generator is operating in command mode and a command to send one or more pulses has been executed. Command mode is selected by calling EMACTimestampPPSCommandModeSet().

In simple mode, the PPS output signal frequency is controlled by the ui32FreqConfig parameter passed to EMACTimestampPPSSimpleModeSet().

The ui32Period and ui32Width parameters are expressed in terms of system time update ticks. When the system time is operating in coarse update mode, each tick is equivalent to the system clock. In fine update mode, a tick occurs every time the 32-bit system time accumulator overflows and this, in turn, is determined by the value passed to the function EMACTimestampAddendSet(). Regardless of the tick source, each tick increments the actual system time, queried using EMACTimestampSysTimeGet() by the subsecond increment value passed in the ui32SubSecondInc to EMACTimestampConfigSet().

Returns: None.

References ASSERT, EMAC_O_PPS0INTVL, EMAC_O_PPS0WIDTH, and HWREG.

§ EMACVLANRxConfigSet()

void EMACVLANRxConfigSet	(	uint32_t	ui32Base,
		uint16_t	ui16Tag,
		uint32_t	ui32Config
	)

Sets options related to reception of VLAN-tagged frames.

Parameters

ui32Base	is the base address of the controller.
ui16Tag	is the IEEE 802.1Q VLAN tag expected for incoming frames.
ui32Config	determines how the receiver handles VLAN-tagged frames.

This function configures the receiver's handling of IEEE 802.1Q VLAN tagged frames. Incoming tagged frames are filtered using either a perfect filter or a hash filter. When hash filtering is disabled, VLAN frames tagged with the value of ui16Tag pass the filter and all others are rejected. The tag comparison may involve all 16 bits or only the 12-bit VLAN ID portion of the tag.

The ui32Config parameter is a logical OR of the following values:

EMAC_VLAN_RX_HASH_ENABLE enables hash filtering for VLAN tags. If this flag is absent, perfect filtering using the tag supplied in ui16Tag is performed. The hash filter may be set using EMACVLANHashFilterSet(), and EMACVLANHashFilterBitCalculate() may be used to determine which bits to set in the filter for given VLAN tags.
EMAC_VLAN_RX_SVLAN_ENABLE causes the receiver to recognize S-VLAN (Type = 0x88A8) frames as valid VLAN-tagged frames. If absent, only frames with type 0x8100 are considered valid VLAN frames.
EMAC_VLAN_RX_INVERSE_MATCH causes the receiver to pass all VLAN frames for which the tags do not match the supplied ui16Tag value. If this flag is absent, only tagged frames matching ui16Tag are passed.
EMAC_VLAN_RX_12BIT_TAG causes the receiver to compare only the bottom 12 bits of ui16Tag when performing either perfect or hash filtering of VLAN frames. If this flag is absent, all 16 bits of the frame tag are examined when filtering. If this flag is set and ui16Tag has all bottom 12 bits clear, the receiver passes all frames with types 0x8100 or 0x88A8 regardless of the tag values they contain.

Note: To ensure that VLAN frames that fail the tag filter are dropped by the MAC, EMACFrameFilterSet() must be called with the EMAC_FRMFILTER_VLAN flag set in the ui32FilterOpts parameter. If this flag is not set, failing VLAN packets are received by the application, but bit 10 of RDES0 (EMAC_FRMFILTER_VLAN) is clear indicating that the packet did not match the current VLAG tag filter.

See also: EMACVLANRxConfigGet()

Returns: None

References ASSERT, EMAC_O_VLANTG, EMAC_VLANTG_VL_S, and HWREG.

§ EMACVLANRxConfigGet()

uint32_t EMACVLANRxConfigGet	(	uint32_t	ui32Base,
		uint16_t *	pui16Tag
	)

Returns the currently-set options related to reception of VLAN-tagged frames.

Parameters

ui32Base	is the base address of the controller.
pui16Tag	points to storage which is written with the currently configured VLAN tag used for perfect filtering.

This function returns information on how the receiver is currently handling IEEE 802.1Q VLAN-tagged frames.

See also: EMACVLANRxConfigSet()

Returns: Returns flags defining how VLAN-tagged frames are handled. The value is a logical OR of the following flags:

EMAC_VLAN_RX_HASH_ENABLE indicates that hash filtering is enabled for VLAN tags. If this flag is absent, perfect filtering using the tag returned in *pui16Tag is performed.
EMAC_VLAN_RX_SVLAN_ENABLE indicates that the receiver recognizes S-VLAN (Type = 0x88A8) frames as valid VLAN-tagged frames. If absent, only frames with type 0x8100 are considered valid VLAN frames.
EMAC_VLAN_RX_INVERSE_MATCH indicates that the receiver passes all VLAN frames for which the tags do not match the *pui16Tag value. If this flag is absent, only tagged frames matching *pui16Tag are passed.
EMAC_VLAN_RX_12BIT_TAG indicates that the receiver is comparing only the bottom 12 bits of *pui16Tag when performing either perfect or hash filtering of VLAN frames. If this flag is absent, all 16 bits of the frame tag are examined when filtering. If this flag is set and *pui16Tag has all bottom 12 bits clear, the receiver passes all frames with types 0x8100 or 0x88A8 regardless of the tag values they contain.

References ASSERT, EMAC_O_VLANTG, EMAC_VLANTG_VL_M, EMAC_VLANTG_VL_S, and HWREG.

§ EMACVLANTxConfigSet()

void EMACVLANTxConfigSet	(	uint32_t	ui32Base,
		uint16_t	ui16Tag,
		uint32_t	ui32Config
	)

Sets options related to transmission of VLAN-tagged frames.

Parameters

ui32Base	is the base address of the controller.
ui16Tag	is the VLAN tag to be used when inserting or replacing tags in transmitted frames.
ui32Config	determines the VLAN-related processing performed by the transmitter.

This function is used to configure transmitter options relating to IEEE 802.1Q VLAN tagging. The transmitter may be set to insert tagging into untagged frames or replace existing tags with new values.

The ui16Tag parameter contains the VLAN tag to be used in outgoing tagged frames. The ui32Config parameter is a logical OR of the following labels:

EMAC_VLAN_TX_SVLAN uses the S-VLAN type (0x88A8) when inserting or replacing tags in transmitted frames. If this label is absent, C-VLAN type (0x8100) is used.
EMAC_VLAN_TX_USE_VLC informs the transmitter that the VLAN tag handling should be defined by the VLAN control (VLC) value provided in this function call. If this tag is absent, VLAN handling is controlled by fields in the transmit descriptor.

If EMAC_VLAN_TX_USE_VLC is set, one of the following four labels must also be included to define the transmit VLAN tag handling:

EMAC_VLAN_TX_VLC_NONE instructs the transmitter to perform no VLAN tag insertion, deletion or replacement.
EMAC_VLAN_TX_VLC_DELETE instructs the transmitter to remove VLAN tags from all transmitted frames that contain them. As a result, bytes 13, 14, 15 and 16 are removed from all frames with types 0x8100 or 0x88A8.
EMAC_VLAN_TX_VLC_INSERT instructs the transmitter to insert a VLAN type and tag into all outgoing frames regardless of whether or not they already contain a VLAN tag.
EMAC_VLAN_TX_VLC_REPLACE instructs the transmitter to replace the VLAN tag in all frames of type 0x8100 or 0x88A8 with the value provided to this function in the ui16Tag parameter.

Returns: None

References ASSERT, EMAC_O_VLNINCREP, EMAC_VLNINCREP_VLT_S, and HWREG.

§ EMACVLANTxConfigGet()

uint32_t EMACVLANTxConfigGet	(	uint32_t	ui32Base,
		uint16_t *	pui16Tag
	)

Returns currently-selected options related to transmission of VLAN-tagged frames.

Parameters

ui32Base	is the base address of the controller.
pui16Tag	points to storage that is written with the VLAN tag currently being used for insertion or replacement.

This function returns information on the current settings related to VLAN tagging of transmitted frames.

See also: EMACVLANTxConfigSet()

Returns: Returns flags describing the current VLAN configuration relating to frame transmission. The return value is a logical OR of the following values:

EMAC_VLAN_TX_SVLAN indicates that the S-VLAN type (0x88A8) is being used when inserting or replacing tags in transmitted frames. If this label is absent, C-VLAN type (0x8100) is being used.
EMAC_VLAN_TX_USE_VLC indicates that the transmitter is processing VLAN frames according to the VLAN control (VLC) value returned here. If this tag is absent, VLAN handling is controlled by fields in the transmit descriptor.

If EMAC_VLAN_TX_USE_VLC is returned, one of the following four labels is also included to define the transmit VLAN tag handling. Note that this value may be extracted from the return value using the mask EMAC_VLAN_TX_VLC_MASK.

EMAC_VLAN_TX_VLC_NONE indicates that the transmitter is not performing VLAN tag insertion, deletion or replacement.
EMAC_VLAN_TX_VLC_DELETE indicates that the transmitter is removing VLAN tags from all transmitted frames which contain them.
EMAC_VLAN_TX_VLC_INSERT indicates that the transmitter is inserting a VLAN type and tag into all outgoing frames regardless of whether or not they already contain a VLAN tag.
EMAC_VLAN_TX_VLC_REPLACE indicates that the transmitter is replacing the VLAN tag in all transmitted frames of type 0x8100 or 0x88A8 with the value returned in *pui16Tag.

References ASSERT, EMAC_O_VLNINCREP, EMAC_VLNINCREP_VLT_M, EMAC_VLNINCREP_VLT_S, and HWREG.

§ EMACVLANHashFilterBitCalculate()

uint32_t EMACVLANHashFilterBitCalculate ( uint16_t ui16Tag )

Returns the bit number to set in the VLAN hash filter corresponding to a given tag.

Parameters

ui16Tag is the VLAN tag for which the hash filter bit number is to be determined.

This function may be used to determine which bit in the VLAN hash filter to set to describe a given 12- or 16-bit VLAN tag. The returned value is a 4-bit value indicating the bit number to set within the 16-bit VLAN hash filter. For example, if 0x02 is returned, this indicates that bit 2 of the hash filter must be set to pass the supplied VLAN tag.

Returns: Returns the bit number to set in the VLAN hash filter to describe the passed tag.

References Crc32().

§ EMACVLANHashFilterSet()

void EMACVLANHashFilterSet	(	uint32_t	ui32Base,
		uint32_t	ui32Hash
	)

Sets the hash filter used to control reception of VLAN-tagged frames.

Parameters

ui32Base	is the base address of the controller.
ui32Hash	is the hash filter value to set.

This function allows the VLAG tag hash filter to be set. By using hash filtering, several different VLAN tags can be filtered very easily at the cost of some false positive results that must be removed by software.

The hash filter value passed in ui32Hash may be built up by calling EMACVLANHashFilterBitCalculate() for each VLAN tag that is to pass the filter and then set each of the bits for which the numbers are returned by that function. Care must be taken when clearing bits in the hash filter due to the fact that there is a many-to-one correspondence between VLAN tags and hash filter bits.

Returns: None

References ASSERT, EMAC_O_VLANHASH, and HWREG.

§ EMACVLANHashFilterGet()

uint32_t EMACVLANHashFilterGet ( uint32_t ui32Base )

Returns the current value of the hash filter used to control reception of VLAN-tagged frames.

Parameters

ui32Base is the base address of the controller.

This function allows the current VLAN tag hash filter value to be returned. Additional VLAN tags may be added to this filter by setting the appropriate bits, determined by calling EMACVLANHashFilterBitCalculate(), and then calling EMACVLANHashFilterSet() to set the new filter value.

Returns: Returns the current value of the VLAN hash filter.

References ASSERT, EMAC_O_VLANHASH, and HWREG.

§ EMACRemoteWakeUpFrameFilterSet()

void EMACRemoteWakeUpFrameFilterSet	(	uint32_t	ui32Base,
		const tEMACWakeUpFrameFilter *	pFilter
	)

Sets values defining up to four frames used to trigger a remote wake-up.

Parameters

ui32Base	is the base address of the controller.
pFilter	points to the structure containing remote wake-up frame filter information.

This function may be used to define up to four different frames that are considered by the Ethernet MAC to be remote wake-up signals. The data passed to the function describes a wake-up frame in terms of a CRC calculated on up to 31 payload bytes in the frame. The actual bytes used in the CRC calculation are defined by means of a bit mask where a ``1'' indicates that a byte in the frame should contribute to the CRC calculation and a ``0'' indicates that the byte should be skipped, as well as an offset from the start of the frame to the payload byte that represents the first byte in the 31-byte CRC-checked sequence.

The pFilter parameter points to a structure containing the information necessary to set up the filters. This structure contains the following fields, each of which is replicated 4 times, once for each possible wake-up frame:

pui32ByteMask defines whether a given byte in the chosen 31-byte sequence within the frame should contribute to the CRC calculation or not. A 1 indicates that the byte should contribute to the calculation, a 0 causes the byte to be skipped.
pui8Command contains flags defining whether this filter is enabled and, if so, whether it refers to unicast or multicast packets. Valid values are one of EMAC_RWU_FILTER_MULTICAST or EMAC_RWU_FILTER_UNICAST ORed with one of EMAC_RWU_FILTER_ENABLE or EMAC_RWU_FILTER_DISABLE.
pui8Offset defines the zero-based index of the byte within the frame at which CRC checking defined by pui32ByteMask begins. Alternatively, this value can be thought of as the number of bytes in the frame that the MAC skips before accumulating the CRC based on the pattern in pui32ByteMask.
pui16CRC provides the value of the calculated CRC for a valid remote wake-up frame. If the incoming frame is processed according to the filter values provided and the final CRC calculation equals this value, the frame is considered to be a valid remote wake-up frame.

Note that this filter uses CRC16 rather than CRC32 as used in frame checksums. The required CRC uses a direct algorithm with polynomial 0x8005, initial seed value 0xFFFF, no final XOR and reversed data order. CRCs for use in this function may be determined using the online calculator found at http://www.zorc.breitbandkatze.de/crc.html.

Returns: None.

References ASSERT, EMAC_O_PMTCTLSTAT, EMAC_O_RWUFF, EMAC_PMTCTLSTAT_WUPFRRST, and HWREG.

§ EMACRemoteWakeUpFrameFilterGet()

void EMACRemoteWakeUpFrameFilterGet	(	uint32_t	ui32Base,
		tEMACWakeUpFrameFilter *	pFilter
	)

Returns the current remote wake-up frame filter configuration.

Parameters

ui32Base	is the base address of the controller.
pFilter	points to the structure that is written with the current remote wake-up frame filter information.

This function may be used to read the current wake-up frame filter settings. The data returned by the function describes wake-up frames in terms of a CRC calculated on up to 31 payload bytes in the frame. The actual bytes used in the CRC calculation are defined by means of a bit mask where a 1'' indicates that a byte in the frame should contribute to the CRC calculation and a0'' indicates that the byte should be skipped, and an offset from the start of the frame to the payload byte that represents the first byte in the 31-byte CRC-checked sequence.

The pFilter parameter points to storage that is written with a structure containing the information defining the frame filters. This structure contains the following fields, each of which is replicated 4 times, once for each possible wake-up frame:

pui32ByteMask defines whether a given byte in the chosen 31-byte sequence within the frame should contribute to the CRC calculation or not. A 1 indicates that the byte should contribute to the calculation, a 0 causes the byte to be skipped.
pui8Command contains flags defining whether this filter is enabled and, if so, whether it refers to unicast or multicast packets. Valid values are one of EMAC_RWU_FILTER_MULTICAST or EMAC_RWU_FILTER_UNICAST ORed with one of EMAC_RWU_FILTER_ENABLE or EMAC_RWU_FILTER_DISABLE.
pui8Offset defines the zero-based index of the byte within the frame at which CRC checking defined by pui32ByteMask begins. Alternatively, this value can be thought of as the number of bytes in the frame that the MAC skips before accumulating the CRC based on the pattern in pui32ByteMask.
pui16CRC provides the value of the calculated CRC for a valid remote wake-up frame. If the incoming frame is processed according to the filter values provided and the final CRC calculation equals this value, the frame is considered to be a valid remote wake-up frame.

Note that this filter uses CRC16 rather than CRC32 as used in frame checksums.

Returns: None.

References ASSERT, EMAC_O_PMTCTLSTAT, EMAC_O_RWUFF, EMAC_PMTCTLSTAT_WUPFRRST, and HWREG.

§ EMACPowerManagementControlSet()

void EMACPowerManagementControlSet	(	uint32_t	ui32Base,
		uint32_t	ui32Flags
	)

Sets the Ethernet MAC remote wake-up configuration.

Parameters

ui32Base	is the base address of the controller.
ui32Flags	defines which types of frame should trigger a remote wake-up and allows the MAC to be put into power-down mode.

This function allows the MAC's remote wake-up features to be configured, determining which types of frame should trigger a wake-up event and allowing an application to place the MAC in power-down mode. In this mode, the MAC ignores all received frames until one matching a configured remote wake-up frame is received, at which point the MAC automatically exits power-down mode and continues to receive frames.

The ui32Flags parameter is a logical OR of the following flags:

EMAC_PMT_GLOBAL_UNICAST_ENABLE instructs the MAC to wake up when any unicast frame matching the MAC destination address filter is received.
EMAC_PMT_WAKEUP_PACKET_ENABLE instructs the MAC to wake up when any received frame matches the remote wake-up filter configured via a call to EMACRemoteWakeUpFrameFilterSet().
EMAC_PMT_MAGIC_PACKET_ENABLE instructs the MAC to wake up when a standard Wake-on-LAN "magic packet" is received. The magic packet contains 6 bytes of 0xFF followed immediately by 16 repetitions of the destination MAC address.
EMAC_PMT_POWER_DOWN instructs the MAC to enter power-down mode and wait for an incoming frame matching the remote wake-up frames as described by other flags and via the remote wake-up filter. This flag should only set set if at least one other flag is specified to configure a wake-up frame type.

When the MAC is in power-down mode, software may exit the mode by calling this function with the EMAC_PMT_POWER_DOWN flag absent from ui32Flags. If a configured wake-up frame is received while in power-down mode, the EMAC_INT_POWER_MGMNT interrupt is signaled and may be cleared by reading the status using EMACPowerManagementStatusGet().

Note: While it is possible to gate the clock to the MAC while it is in power-down mode, doing so prevents the reading of the registers required to determine the interrupt status and also prevents power-down mode from exiting via another call to this function.

Returns: None.

References ASSERT, EMAC_O_PMTCTLSTAT, EMAC_PMT_GLOBAL_UNICAST_ENABLE, EMAC_PMT_MAGIC_PACKET_ENABLE, EMAC_PMT_POWER_DOWN, EMAC_PMT_WAKEUP_PACKET_ENABLE, EMAC_PMTCTLSTAT_GLBLUCAST, EMAC_PMTCTLSTAT_MGKPKTEN, EMAC_PMTCTLSTAT_PWRDWN, EMAC_PMTCTLSTAT_WUPFREN, and HWREG.

§ EMACPowerManagementControlGet()

uint32_t EMACPowerManagementControlGet ( uint32_t ui32Base )

Queries the current Ethernet MAC remote wake-up configuration.

Parameters

ui32Base is the base address of the controller.

This function allows the MAC's remote wake-up settings to be queried. These settings determine which types of frame should trigger a remote wake-up event

Returns: Returns a logical OR of the following flags:

EMAC_PMT_GLOBAL_UNICAST_ENABLE indicates that the MAC wakes up when any unicast frame matching the MAC destination address filter is received.
EMAC_PMT_WAKEUP_PACKET_ENABLE indicates that the MAC wakes up when any received frame matches the remote wake-up filter configured via a call to EMACRemoteWakeUpFrameFilterSet().
EMAC_PMT_MAGIC_PACKET_ENABLE indicates that the MAC wakes up when a standard Wake-on-LAN "magic packet" is received. The magic packet contains 6 bytes of 0xFF followed immediately by 16 repetitions of the destination MAC address.
EMAC_PMT_POWER_DOWN indicates that the MAC is currently in power-down mode and is waiting for an incoming frame matching the remote wake-up frames as described by other returned flags and via the remote wake-up filter.

References ASSERT, EMAC_O_PMTCTLSTAT, EMAC_PMTCTLSTAT_GLBLUCAST, EMAC_PMTCTLSTAT_MGKPKTEN, EMAC_PMTCTLSTAT_PWRDWN, EMAC_PMTCTLSTAT_WUPFREN, and HWREG.

§ EMACPowerManagementStatusGet()

uint32_t EMACPowerManagementStatusGet ( uint32_t ui32Base )

Queries the current Ethernet MAC remote wake-up status.

Parameters

ui32Base is the base address of the controller.

This function returns information on the remote wake-up state of the Ethernet MAC. If the MAC has been woken up since the last call, the returned value indicates the type of received frame that caused the MAC to exit power-down state.

Returns: Returns a logical OR of the following flags:

EMAC_PMT_POWER_DOWN indicates that the MAC is currently in power-down mode.
EMAC_PMT_WAKEUP_PACKET_RECEIVED indicates that the MAC exited power-down mode due to a remote wake-up frame being received. This function call clears this flag.
EMAC_PMT_MAGIC_PACKET_RECEIVED indicates that the MAC exited power-down mode due to a wake-on-LAN magic packet being received. This function call clears this flag.

References ASSERT, EMAC_O_PMTCTLSTAT, EMAC_PMTCTLSTAT_MGKPRX, EMAC_PMTCTLSTAT_PWRDWN, EMAC_PMTCTLSTAT_WUPRX, and HWREG.

§ EMACWoLEnter()

void EMACWoLEnter ( uint32_t ui32Base )

Enables the wake-on-LAN feature of the MAC controller.

Parameters

ui32Base is the base address of the controller.

This function is used to enable the wake-on-LAN feature of the MAC controller. It is done by first checking if the transmit path is idle and disabling the trasnmitter and the transmit DMA controller. Then it checks if any data from the network is being actively received and if not then it disables the receive DMA controller.

Returns: None.

References ASSERT, EMAC_CFG_TE, EMAC_DMAOPMODE_SR, EMAC_DMAOPMODE_ST, EMAC_DMARIS_TI, EMAC_O_CFG, EMAC_O_DMAOPMODE, EMAC_O_DMARIS, EMAC_O_STATUS, EMAC_STATUS_RX_FIFO_EMPTY, EMAC_STATUS_RX_FIFO_LEVEL_MASK, and HWREG.

§ EMACLPIConfig()

void EMACLPIConfig	(	uint32_t	ui32Base,
		bool	bLPIConfig,
		uint16_t	ui16LPILSTimer,
		uint16_t	ui16LPITWTimer
	)

Configures the LPI timers and control register.

Parameters

ui32Base	is the base address of the controller.
bLPIConfig	is state of LPI trasnmit automate bit.
ui16LPILSTimer	is the value of LS timer in milli-seconds.
ui16LPITWTimer	is the value of TW timer in micro-seconds.

This function is used to configure the LPI timer and control registers when the link is established as EEE mode or when the link is lost. When the link is established as EEE, then ui16LPILSTimer is programmed as the link status timer value and ui16LPITWTimer is programmed as the transmit wait timer value. The parameter bLPIConfig is used to decide if the transmit path must be automated or should be under user control.

Returns: None.

References ASSERT, EMAC_LPICTLSTAT_LPITXA, EMAC_LPITIMERCTL_LST_M, EMAC_LPITIMERCTL_LST_S, EMAC_LPITIMERCTL_TWT_M, EMAC_O_LPICTLSTAT, EMAC_O_LPITIMERCTL, and HWREG.

§ EMACLPIEnter()

void EMACLPIEnter ( uint32_t ui32Base )

Enables the transmit path for LPI mode entry.

Parameters

ui32Base is the base address of the controller.

This function is used to enable the transmit path in LPI mode when there is no more data to be transmitted by the MAC controller.

Returns: None.

References ASSERT, EMAC_LPICTLSTAT_LPIEN, EMAC_O_LPICTLSTAT, and HWREG.

§ EMACLPIStatus()

uint16_t EMACLPIStatus ( uint32_t ui32Base )

Returns the status of the LPI link.

Parameters

ui32Base is the base address of the controller.

This function may be used to read the status of the transmit and receive path when the link is configured in LPI mode.

Returns: Returns the lower 16 bits of the LPI Control and Status register.

References ASSERT, EMAC_O_LPICTLSTAT, and HWREG.

§ EMACLPILinkSet()

void EMACLPILinkSet ( uint32_t ui32Base )

Sets the link status of the external PHY.

Parameters

ui32Base is the base address of the controller.

This function is used to set the link status of the external PHY when the link is established in EEE mode.

Returns: None.

References ASSERT, EMAC_LPICTLSTAT_PLS, EMAC_O_LPICTLSTAT, and HWREG.

§ EMACLPILinkClear()

void EMACLPILinkClear ( uint32_t ui32Base )

Clears the link status of the external PHY.

Parameters

ui32Base is the base address of the controller.

This function is used to clear the link status of the external PHY when the link is lost due to a disconnect or EEE mode link is not established.

Returns: None.

References ASSERT, EMAC_LPICTLSTAT_PLS, EMAC_O_LPICTLSTAT, and HWREG.

§ EMACPHYMMDWrite()

void EMACPHYMMDWrite	(	uint32_t	ui32Base,
		uint8_t	ui8PhyAddr,
		uint16_t	ui16RegAddr,
		uint16_t	ui16Data
	)

Writes a value to an extended PHY register in MMD address space.

Parameters

ui32Base	is the base address of the controller.
ui8PhyAddr	is the physical address of the PHY to access.
ui16RegAddr	is the address of the PHY extended register to be accessed.
ui16Value	is the value to write to the register.

When uhen connected to an external PHY supporting extended registers in MMD address space, this function allows a value to be written to the MMD register specified by ui16RegAddr.

Returns: None.

References ASSERT, DEV_ADDR, EMACPHYWrite(), EPHY_ADDAR, EPHY_REGCTL, and REG_ADDR.

§ EMACPHYMMDRead()

uint16_t EMACPHYMMDRead	(	uint32_t	ui32Base,
		uint8_t	ui8PhyAddr,
		uint16_t	ui16RegAddr
	)

Reads from an extended PHY register in MMD address space.

Parameters

ui32Base	is the base address of the controller.
ui8PhyAddr	is the physical address of the PHY to access.
ui16RegAddr	is the address of the PHY extended register to be accessed.

When connected to an external PHY supporting extended registers, this this function returns the contents of the MMD register specified by ui16RegAddr.

Returns: Returns the 16-bit value read from the PHY.

References ASSERT, DEV_ADDR, EMACPHYRead(), EMACPHYWrite(), EPHY_ADDAR, EPHY_REGCTL, and REG_ADDR.

Data Structures

Macros

Typedefs

Functions

Detailed Description

Introduction

API Functions

Ethernet MAC Data Transfer

Programming Example

Macro Definition Documentation

§ VALID_CONFIG_FLAGS

§ VALID_FRMFILTER_FLAGS

§ EMAC_MASKABLE_INTS

§ EMAC_NORMAL_INTS

§ EMAC_ABNORMAL_INTS

§ EMAC_NON_MASKED_INTS

§ NUM_MAC_ADDR

§ MAC_ADDR_OFFSET

§ EMAC_O_ADDRL

§ EMAC_O_ADDRH

§ NUM_CLOCK_DIVISORS

§ DEV_ADDR

§ REG_ADDR

§ EMAC_PHY_ADDR

§ htonl

§ ntohl

§ htons

§ ntohs

§ DES0_TX_CTRL_OWN

§ DES0_TX_CTRL_INTERRUPT

§ DES0_TX_CTRL_LAST_SEG

§ DES0_TX_CTRL_FIRST_SEG

§ DES0_TX_CTRL_DISABLE_CRC

§ DES0_TX_CTRL_DISABLE_PADDING

§ DES0_TX_CTRL_ENABLE_TS

§ DES0_TX_CTRL_REPLACE_CRC

§ DES0_TX_CTRL_CHKSUM_M

§ DES0_TX_CTRL_NO_CHKSUM

§ DES0_TX_CTRL_IP_HDR_CHKSUM

§ DES0_TX_CTRL_IP_HDR_PAY_CHKSUM

§ DES0_TX_CTRL_IP_ALL_CKHSUMS

§ DES0_TX_CTRL_END_OF_RING

§ DES0_TX_CTRL_CHAINED

§ DES0_TX_CTRL_VLAN_M

§ DES0_TX_CTRL_VLAN_NONE

§ DES0_TX_CTRL_VLAN_REMOVE

§ DES0_TX_CTRL_VLAN_INSERT

§ DES0_TX_CTRL_VLAN_REPLACE

§ DES0_TX_STAT_TS_CAPTURED

§ DES0_TX_STAT_IPH_ERR

§ DES0_TX_STAT_ERR

§ DES0_TX_STAT_JABBER_TO

§ DES0_TX_STAT_FLUSHED

§ DES0_TX_STAT_PAYLOAD_ERR

§ DES0_TX_STAT_CARRIER_LOST

§ DES0_TX_STAT_NO_CARRIER

§ DES0_TX_STAT_TX_L_COLLISION

§ DES0_TX_STAT_E_COLLISION

§ DES0_TX_STAT_VLAN_FRAME

§ DES0_TX_STAT_COL_COUNT_M

§ DES0_TX_STAT_COL_COUNT_S

§ DES0_TX_STAT_E_DEFERRAL

§ DES0_TX_STAT_UNDERFLOW

§ DES0_TX_STAT_DEFERRED

§ DES1_TX_CTRL_SADDR_MAC1

§ DES1_TX_CTRL_SADDR_M

§ DES1_TX_CTRL_SADDR_NONE

§ DES1_TX_CTRL_SADDR_INSERT

§ DES1_TX_CTRL_SADDR_REPLACE

§ DES1_TX_CTRL_BUFF2_SIZE_M

§ DES1_TX_CTRL_BUFF1_SIZE_M

§ DES1_TX_CTRL_BUFF2_SIZE_S

§ DES1_TX_CTRL_BUFF1_SIZE_S

§ DES0_RX_CTRL_OWN

§ DES0_RX_STAT_DEST_ADDR_FAIL

§ DES0_RX_STAT_FRAME_LENGTH_M

§ DES0_RX_STAT_FRAME_LENGTH_S

§ DES0_RX_STAT_ERR

§ DES0_RX_STAT_DESCRIPTOR_ERR

§ DES0_RX_STAT_SRC_ADDR_FAIL