Epi_api

Macros
#define	EPI_HB8_CS_MASK
#define	EPI_HB16_CS_MASK   (EPI_HB8_CS_MASK | EPI_HB16_BURST_TRAFFIC)

Functions
void	EPIWorkaroundWordWrite (uint32_t *pui32Addr, uint32_t ui32Value)
uint32_t	EPIWorkaroundWordRead (uint32_t *pui32Addr)
void	EPIWorkaroundHWordWrite (uint16_t *pui16Addr, uint16_t ui16Value)
uint16_t	EPIWorkaroundHWordRead (uint16_t *pui16Addr)
void	EPIWorkaroundByteWrite (uint8_t *pui8Addr, uint8_t ui8Value)
uint8_t	EPIWorkaroundByteRead (uint8_t *pui8Addr)
void	EPIModeSet (uint32_t ui32Base, uint32_t ui32Mode)
void	EPIDividerSet (uint32_t ui32Base, uint32_t ui32Divider)
void	EPIDividerCSSet (uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Divider)
void	EPIDMATxCount (uint32_t ui32Base, uint32_t ui32Count)
void	EPIConfigSDRAMSet (uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32Refresh)
void	EPIConfigHB8Set (uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32MaxWait)
void	EPIConfigHB16Set (uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32MaxWait)
void	EPIConfigHB8CSSet (uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
void	EPIConfigHB16CSSet (uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
void	EPIConfigHB8TimingSet (uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
void	EPIConfigHB16TimingSet (uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
void	EPIPSRAMConfigRegSet (uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32CR)
void	EPIPSRAMConfigRegRead (uint32_t ui32Base, uint32_t ui32CS)
bool	EPIPSRAMConfigRegGetNonBlocking (uint32_t ui32Base, uint32_t ui32CS, uint32_t *pui32CR)
uint32_t	EPIPSRAMConfigRegGet (uint32_t ui32Base, uint32_t ui32CS)
void	EPIConfigGPModeSet (uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32FrameCount, uint32_t ui32MaxWait)
void	EPIAddressMapSet (uint32_t ui32Base, uint32_t ui32Map)
void	EPINonBlockingReadConfigure (uint32_t ui32Base, uint32_t ui32Channel, uint32_t ui32DataSize, uint32_t ui32Address)
void	EPINonBlockingReadStart (uint32_t ui32Base, uint32_t ui32Channel, uint32_t ui32Count)
void	EPINonBlockingReadStop (uint32_t ui32Base, uint32_t ui32Channel)
uint32_t	EPINonBlockingReadCount (uint32_t ui32Base, uint32_t ui32Channel)
uint32_t	EPINonBlockingReadAvail (uint32_t ui32Base)
uint32_t	EPINonBlockingReadGet32 (uint32_t ui32Base, uint32_t ui32Count, uint32_t *pui32Buf)
uint32_t	EPINonBlockingReadGet16 (uint32_t ui32Base, uint32_t ui32Count, uint16_t *pui16Buf)
uint32_t	EPINonBlockingReadGet8 (uint32_t ui32Base, uint32_t ui32Count, uint8_t *pui8Buf)
void	EPIFIFOConfig (uint32_t ui32Base, uint32_t ui32Config)
uint32_t	EPIWriteFIFOCountGet (uint32_t ui32Base)
void	EPIIntEnable (uint32_t ui32Base, uint32_t ui32IntFlags)
void	EPIIntDisable (uint32_t ui32Base, uint32_t ui32IntFlags)
uint32_t	EPIIntStatus (uint32_t ui32Base, bool bMasked)
uint32_t	EPIIntErrorStatus (uint32_t ui32Base)
void	EPIIntErrorClear (uint32_t ui32Base, uint32_t ui32ErrFlags)
void	EPIIntRegister (uint32_t ui32Base, void(*pfnHandler)(void))
void	EPIIntUnregister (uint32_t ui32Base)

Detailed Description

Introduction

The EPI API provides functions to use the EPI module available in the MSP432E4 microcontroller. The EPI module provides a physical interface for external peripherals and memories. The EPI can be configured to support several types of external interfaces and different sized address and data buses.

Some features of the EPI module are:

• configurable interface modes including SDRAM, HostBus, and simple read/write protocols
• configurable address and data sizes
• configurable bus cycle timing
• blocking and non-blocking reads and writes
• FIFO for streaming reads
• interrupt and uDMA support

API Functions

The function EPIModeSet() is used to select the interface mode. The clock divider is set with the EPIDividerSet() function which determines the speed of the external bus. The external device is mapped into the processor memory or peripheral space using the EPIAddressMapSet() function.

Once the mode is selected, the interface is configured with one of the configuration functions. If SDRAM mode is chosen, then the function EPIConfigSDRAMSet() is used to configure the SDRAM interface. If Host-Bus 8 mode is chosen, then EPIConfigHB8Set() is used. If Host-Bus 16 mode is chosen, then EPIConfigHB16Set() is used. If General-Purpose mode is chosen, then EPIConfigGPMode() is used.

After the mode has been selected and configured, then the device can be accessed by reading and writing to the memory or peripheral address space that was programmed with EPIAddressMapSet().

There are more sophisticated ways to use the read/write interface. When an application is writing to the mapped memory or peripheral space, the writes stall the processor until the write to the external interface is completed. However, the EPI contains an internal transaction FIFO and can buffer up to 4 pending writes without stalling the processor. Prior to writing, the application can test to see if the EPI can take more write operations without stalling the processor by using the function EPINonBlockingWriteCount(), which returns the number of non-blocking writes that can be made.

For efficient reads from the external device, the EPI contains a programmable read FIFO. After setting a starting address and a count, data from sequential reads from the device can be stored in the FIFO. The application can then periodically drain the FIFO by polling or by interrupts, optionally using the uDMA controller. A non-blocking read is configured by using the function EPINonBlockingReadConfigure(). The read operation is started with EPINonBlockingReadStart() and can be stopped by calling EPINonBlockingReadStop(). The function EPINonBlockingReadCount() can be used to determine the number of items remaining to be read, while the function EPINonBlockingReadAvail() returns the number of items in the FIFO that can be read immediately without stalling. There are 3 functions available for reading data from the FIFO and into a buffer provided by the application. These functions are EPINonBlockingReadGet32(), EPINonBlockingReadGet16(), EPINonBlockingReadGet8(), to read the data from the FIFO as 32-bit, 16-bit, or 8-bit data items.

The read FIFO and write transaction FIFO can be configured with the function EPIFIFOConfig(). This function is used to set the FIFO trigger levels and to enable error interrupts to be generated when a read or write is stalled.

Interrupts are enabled or disabled with the functions EPIIntEnable() and EPIIntDisable(). The interrupt status can be read by calling EPIIntStatus(). If there is an error interrupt pending, the cause of the error can be determined with the function EPIIntErrorStatus(). The error can then be cleared with EPIIntErrorClear().

If dynamic interrupt registration is being used by the application, then an EPI interrupt handler can be registered by calling EPIIntRegister(). This function loads the interrupt handler's address into the vector table. The handler can be removed with EPIIntUnregister().

Programming Example

This example illustrates the setup steps required to initialize the EPI to access an SDRAM when the system clock is running at 50MHz.

//
// Enable the EPI module.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

//
// Wait for the EPI module to be ready.
//
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPI0))
{
}

//
// Set the EPI divider.
//
EPIDividerSet(EPI0_BASE, 0);

//
// Select SDRAM mode.
//
EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);

//
// Configure SDRAM mode.
//
EPIConfigSDRAMSet(EPI0_BASE, (EPI_SDRAM_CORE_FREQ_50_100 |
                  EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT), 1024);

//
// Set the address map.
//
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_256MB | EPI_ADDR_RAM_BASE_6);

//
// Wait for the EPI initialization to complete.
//
while(HWREG(EPI0_BASE + EPI_O_STAT) &  EPI_STAT_INITSEQ)
{
    //
    // Wait for SDRAM initialization to complete.
    //
}

//
// At this point, the SDRAM is accessible and available for use.
//

Macro Definition Documentation

EPI_HB8_CS_MASK

#define EPI_HB8_CS_MASK

Value:

(EPI_HB8_MODE_FIFO | EPI_HB8_RDWAIT_3 |       \
                                 EPI_HB8_WRWAIT_3 | EPI_HB8_RDHIGH |          \
                                 EPI_HB8_WRHIGH | EPI_HB8_ALE_HIGH)

Referenced by EPIConfigHB8CSSet().

EPI_HB16_CS_MASK

#define EPI_HB16_CS_MASK   (EPI_HB8_CS_MASK | EPI_HB16_BURST_TRAFFIC)

Referenced by EPIConfigHB16CSSet().

Function Documentation

EPIWorkaroundWordWrite()

void EPIWorkaroundWordWrite	(	uint32_t *	pui32Addr,
		uint32_t	ui32Value
	)

Safely writes a word to the EPI 0x10000000 address space.

Parameters

pui32Addr	is the address which is to be written.
ui32Value	is the 32-bit word to write.

This function must be used when writing words to EPI-attached memory configured to use the address space at 0x10000000 on devices affected by the EPI#01 erratum. Direct access to memory in these cases can cause data corruption depending upon memory accesses immediately before or after the EPI access but using this function will allow EPI accesses to complete correctly. The function is defined as ``inline'' in epi.h.

Use of this function on a device not affected by the erratum is safe but will impact performance due to an additional overhead of at least 2 cycles per access. This erratum affects only the 0x10000000 address space typically used to store the LCD controller frame buffer. The 0x60000000 address space is not affected and applications using this address mapping need not use this function.

Returns

None.

EPIWorkaroundWordRead()

uint32_t EPIWorkaroundWordRead

(

uint32_t *

pui32Addr

)

Safely reads a word from the EPI 0x10000000 address space.

Parameters

pui32Addr

is the address which is to be read.

This function must be used when reading words from EPI-attached memory configured to use the address space at 0x10000000 on devices affected by the EPI#01 erratum. Direct access to memory in these cases can cause data corruption depending upon memory accesses immediately before or after the EPI access but using this function will allow EPI accesses to complete correctly. The function is defined as ``inline'' in epi.h.

Use of this function on a device not affected by the erratum is safe but will impact performance due to an additional overhead of at least 2 cycles per access. This erratum affects only the 0x10000000 address space typically used to store the LCD controller frame buffer. The 0x60000000 address space is not affected and applications using this address mapping need not use this function.

Returns

The 32-bit word stored at address pui32Addr.

EPIWorkaroundHWordWrite()

void EPIWorkaroundHWordWrite	(	uint16_t *	pui16Addr,
		uint16_t	ui16Value
	)

Safely writes a half-word to the EPI 0x10000000 address space.

Parameters

pui16Addr	is the address which is to be written.
ui16Value	is the 16-bit half-word to write.

This function must be used when writing half-words to EPI-attached memory configured to use the address space at 0x10000000 on devices affected by the EPI#01 erratum. Direct access to memory in these cases can cause data corruption depending upon memory accesses immediately before or after the EPI access but using this function will allow EPI accesses to complete correctly. The function is defined as ``inline'' in epi.h.

Use of this function on a device not affected by the erratum is safe but will impact performance due to an additional overhead of at least 2 cycles per access. This erratum affects only the 0x10000000 address space typically used to store the LCD controller frame buffer. The 0x60000000 address space is not affected and applications using this address mapping need not use this function.

Returns

None.

EPIWorkaroundHWordRead()

uint16_t EPIWorkaroundHWordRead

(

uint16_t *

pui16Addr

)

Safely reads a half-word from the EPI 0x10000000 address space.

Parameters

pui16Addr

is the address which is to be read.

This function must be used when reading half-words from EPI-attached memory configured to use the address space at 0x10000000 on devices affected by the EPI#01 erratum. Direct access to memory in these cases can cause data corruption depending upon memory accesses immediately before or after the EPI access but using this function will allow EPI accesses to complete correctly. The function is defined as ``inline'' in epi.h.

Use of this function on a device not affected by the erratum is safe but will impact performance due to an additional overhead of at least 2 cycles per access. This erratum affects only the 0x10000000 address space typically used to store the LCD controller frame buffer. The 0x60000000 address space is not affected and applications using this address mapping need not use this function.

Returns

The 16-bit word stored at address pui16Addr.

EPIWorkaroundByteWrite()

void EPIWorkaroundByteWrite	(	uint8_t *	pui8Addr,
		uint8_t	ui8Value
	)

Safely writes a byte to the EPI 0x10000000 address space.

Parameters

pui8Addr	is the address which is to be written.
ui8Value	is the 8-bit byte to write.

This function must be used when writing bytes to EPI-attached memory configured to use the address space at 0x10000000 on devices affected by the EPI#01 erratum. Direct access to memory in these cases can cause data corruption depending upon memory accesses immediately before or after the EPI access but using this function will allow EPI accesses to complete correctly. The function is defined as ``inline'' in epi.h.

Use of this function on a device not affected by the erratum is safe but will impact performance due to an additional overhead of at least 2 cycles per access. This erratum affects only the 0x10000000 address space typically used to store the LCD controller frame buffer. The 0x60000000 address space is not affected and applications using this address mapping need not use this function.

Returns

None.

EPIWorkaroundByteRead()

uint8_t EPIWorkaroundByteRead

(

uint8_t *

pui8Addr

)

Safely reads a byte from the EPI 0x10000000 address space.

Parameters

pui8Addr

is the address which is to be read.

This function must be used when reading bytes from EPI-attached memory configured to use the address space at 0x10000000 on devices affected by the EPI#01 erratum. Direct access to memory in these cases can cause data corruption depending upon memory accesses immediately before or after the EPI access but using this function will allow EPI accesses to complete correctly. The function is defined as ``inline'' in epi.h.

Use of this function on a device not affected by the erratum is safe but will impact performance due to an additional overhead of at least 2 cycles per access. This erratum affects only the 0x10000000 address space typically used to store the LCD controller frame buffer. The 0x60000000 address space is not affected and applications using this address mapping need not use this function.

Returns

The 8-bit byte stored at address pui8Addr.

EPIModeSet()

void EPIModeSet	(	uint32_t	ui32Base,
		uint32_t	ui32Mode
	)

Sets the usage mode of the EPI module.

Parameters

ui32Base	is the EPI module base address.
ui32Mode	is the usage mode of the EPI module.

This functions sets the operating mode of the EPI module. The parameter ui32Mode must be one of the following:

• EPI_MODE_GENERAL - use for general-purpose mode operation
• EPI_MODE_SDRAM - use with SDRAM device
• EPI_MODE_HB8 - use with host-bus 8-bit interface
• EPI_MODE_HB16 - use with host-bus 16-bit interface
• EPI_MODE_DISABLE - disable the EPI module

Selection of any of the above modes enables the EPI module, except for EPI_MODE_DISABLE, which is used to disable the module.

Returns

None.

References ASSERT, EPI_MODE_DISABLE, EPI_MODE_GENERAL, EPI_MODE_HB16, EPI_MODE_HB8, EPI_MODE_SDRAM, EPI_O_CFG, and HWREG.

EPIDividerSet()

void EPIDividerSet	(	uint32_t	ui32Base,
		uint32_t	ui32Divider
	)

Sets the clock divider for the EPI module's CS0n/CS1n.

Parameters

ui32Base	is the EPI module base address.
ui32Divider	is the value of the clock divider to be applied to the external interface (0-65535).

This function sets the clock divider(s) that is used to determine the clock rate of the external interface. The ui32Divider value is used to derive the EPI clock rate from the system clock based on the following formula.

EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2))

For example, a divider value of 1 results in an EPI clock rate of half the system clock, value of 2 or 3 yields one quarter of the system clock and a value of 4 results in one sixth of the system clock rate.

In cases where a dual chip select mode is in use and different clock rates are required for each chip select, the ui32Divider parameter must contain two dividers. The lower 16 bits define the divider to be used with CS0n and the upper 16 bits define the divider for CS1n.

Returns

None.

References ASSERT, EPI_O_BAUD, and HWREG.

EPIDividerCSSet()

void EPIDividerCSSet	(	uint32_t	ui32Base,
		uint32_t	ui32CS,
		uint32_t	ui32Divider
	)

Sets the clock divider for the specified CS in the EPI module.

Parameters

ui32Base	is the EPI module base address.
ui32CS	is the chip select to modify and has a valid range of 0-3.
ui32Divider	is the value of the clock divider to be applied to the external interface (0-65535).

This function sets the clock divider(s) for the specified CS that is used to determine the clock rate of the external interface. The ui32Divider value is used to derive the EPI clock rate from the system clock based on the following formula.

EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2))

For example, a divider value of 1 results in an EPI clock rate of half the system clock, value of 2 or 3 yields one quarter of the system clock and a value of 4 results in one sixth of the system clock rate.

Returns

None.

References ASSERT, EPI_O_BAUD, EPI_O_BAUD2, and HWREG.

EPIDMATxCount()

void EPIDMATxCount	(	uint32_t	ui32Base,
		uint32_t	ui32Count
	)

Sets the transfer count for uDMA transmit operations on EPI.

Parameters

ui32Base	is the EPI module base address.
ui32Count	is the number of units to transmit by uDMA to WRFIFO.

This function is used to help configure the EPI uDMA transmit operations. A non-zero transmit count in combination with a FIFO threshold trigger asserts an EPI uDMA transmit.

Note that, although the EPI peripheral can handle counts of up to 65535, a single uDMA transfer has a maximum length of 1024 units so ui32Count should be set to values less than or equal to 1024.

Returns

None.

References ASSERT, EPI_O_DMATXCNT, and HWREG.

EPIConfigSDRAMSet()

void EPIConfigSDRAMSet	(	uint32_t	ui32Base,
		uint32_t	ui32Config,
		uint32_t	ui32Refresh
	)

Configures the SDRAM mode of operation.

Parameters

ui32Base	is the EPI module base address.
ui32Config	is the SDRAM interface configuration.
ui32Refresh	is the refresh count in core clocks (0-2047).

This function is used to configure the SDRAM interface, when the SDRAM mode is chosen with the function EPIModeSet(). The parameter ui32Config is the logical OR of several sets of choices:

The processor core frequency must be specified with one of the following:

• EPI_SDRAM_CORE_FREQ_0_15 defines core clock as 0 MHz < clk <= 15 MHz
• EPI_SDRAM_CORE_FREQ_15_30 defines core clock as 15 MHz < clk <= 30 MHz
• EPI_SDRAM_CORE_FREQ_30_50 defines core clock as 30 MHz < clk <= 50 MHz
• EPI_SDRAM_CORE_FREQ_50_100 defines core clock as 50 MHz < clk <= 100 MHz

The low power mode is specified with one of the following:

• EPI_SDRAM_LOW_POWER enter low power, self-refresh state.
• EPI_SDRAM_FULL_POWER normal operating state.

The SDRAM device size is specified with one of the following:

• EPI_SDRAM_SIZE_64MBIT size is a 64 Mbit device (8 MB).
• EPI_SDRAM_SIZE_128MBIT size is a 128 Mbit device (16 MB).
• EPI_SDRAM_SIZE_256MBIT size is a 256 Mbit device (32 MB).
• EPI_SDRAM_SIZE_512MBIT size is a 512 Mbit device (64 MB).

The parameter ui16Refresh sets the refresh counter in units of core clock ticks. It is an 11-bit value with a range of 0 - 2047 counts.

Returns

None.

References ASSERT, EPI_O_SDRAMCFG, EPI_SDRAMCFG_RFSH_M, EPI_SDRAMCFG_RFSH_S, and HWREG.

EPIConfigHB8Set()

void EPIConfigHB8Set	(	uint32_t	ui32Base,
		uint32_t	ui32Config,
		uint32_t	ui32MaxWait
	)

Configures the interface for Host-bus 8 operation.

Parameters

ui32Base	is the EPI module base address.
ui32Config	is the interface configuration.
ui32MaxWait	is the maximum number of external clocks to wait if a FIFO ready signal is holding off the transaction, 0-255.

This function is used to configure the interface when used in host-bus 8 operation as chosen with the function EPIModeSet(). The parameter ui32Config is the logical OR of the following:

• Host-bus 8 submode, select one of:
  • EPI_HB8_MODE_ADMUX sets data and address muxed, AD[7:0]
  • EPI_HB8_MODE_ADDEMUX sets up data and address separate, D[7:0]
  • EPI_HB8_MODE_SRAM as EPI_HB8_MODE_ADDEMUX, but uses address switch for multiple reads instead of OEn strobing, D[7:0]
  • EPI_HB8_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO empty, D[7:0]
• EPI_HB8_USE_TXEMPTY enables TXEMPTY signal with FIFO
• EPI_HB8_USE_RXFULL enables RXFULL signal with FIFO
• EPI_HB8_WRHIGH sets active high write strobe, otherwise it is active low
• EPI_HB8_RDHIGH sets active high read strobe, otherwise it is active low
• Write wait state when EPI_HB8_BAUD is used, select one of:
  • EPI_HB8_WRWAIT_0 sets write wait state to 2 EPI clocks (default)
  • EPI_HB8_WRWAIT_1 sets write wait state to 4 EPI clocks
  • EPI_HB8_WRWAIT_2 sets write wait state to 6 EPI clocks
  • EPI_HB8_WRWAIT_3 sets write wait state to 8 EPI clocks
• Read wait state when EPI_HB8_BAUD is used, select one of:
  • EPI_HB8_RDWAIT_0 sets read wait state to 2 EPI clocks (default)
  • EPI_HB8_RDWAIT_1 sets read wait state to 4 EPI clocks
  • EPI_HB8_RDWAIT_2 sets read wait state to 6 EPI clocks
  • EPI_HB8_RDWAIT_3 sets read wait state to 8 EPI clocks
• EPI_HB8_CLOCK_GATE_IDLE sets the EPI clock to be held low when no data is available to read or write
• EPI_HB8_CLOCK_INVERT inverts the EPI clock
• EPI_HB8_IN_READY_EN sets EPIS032 as a ready/stall signal, active high
• EPI_HB8_IN_READY_EN_INVERT sets EPIS032 as ready/stall signal, active low
• EPI_HB8_ALE_HIGH sets the address latch active high (default)
• EPI_HB8_ALE_LOW sets address latch active low
• EPI_HB8_CSBAUD use different baud rates when accessing devices on each chip select. CS0n uses the baud rate specified by the lower 16 bits of the divider passed to EPIDividerSet() and CS1n uses the divider passed in the upper 16 bits. If this option is absent, both chip selects use the baud rate resulting from the divider in the lower 16 bits of the parameter passed to EPIDividerSet().

If EPI_HB8_CSBAUD is configured, EPIDividerCSSet() should be used to to configure the divider for CS2n and CS3n. They both also use the lower 16 bits passed to EPIDividerSet() if this option is absent.

The use of EPI_HB8_CSBAUD also allows for unique chip select configurations. CS0n, CS1n, CS2n, and CS3n can each be configured by calling EPIConfigHB8CSSet() if EPI_HB8_CSBAUD is used. Otherwise, the configuration provided in ui32Config is used for all chip selects enabled.

• Chip select configuration, select one of:
  • EPI_HB8_CSCFG_CS sets EPIS030 to operate as a chip select signal.
  • EPI_HB8_CSCFG_ALE sets EPIS030 to operate as an address latch (ALE).
  • EPI_HB8_CSCFG_DUAL_CS sets EPIS030 to operate as CS0n and EPIS027 as CS1n with the asserted chip select determined from the most significant address bit for the respective external address map.
  • EPI_HB8_CSCFG_ALE_DUAL_CS sets EPIS030 as an address latch (ALE), EPIS027 as CS0n and EPIS026 as CS1n with the asserted chip select determined from the most significant address bit for the respective external address map.
  • EPI_HB8_CSCFG_ALE_SINGLE_CS sets EPIS030 to operate as an address latch (ALE) and EPIS027 is used as a chip select.
  • EPI_HB8_CSCFG_QUAD_CS sets EPIS030 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 as CS3n.
  • EPI_HB8_CSCFG_ALE_QUAD_CS sets EPIS030 as an address latch (ALE), EPIS026 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 as CS3n.

    Note

    Dual or quad chip select configurations cannot be used with EPI_HB8_MODE_SRAM.

    The parameter ui32MaxWait is used if the FIFO mode is chosen. If a FIFO is used aint32_t with RXFULL or TXEMPTY ready signals, then this parameter determines the maximum number of clocks to wait when the transaction is being held off by by the FIFO using one of these ready signals. A value of 0 means to wait forever.

Returns

None.

References ASSERT, EPI_HB8_CSBAUD, EPI_HB8_CSCFG_MASK, EPI_HB8CFG2_CSBAUD, EPI_HB8CFG_MAXWAIT_M, EPI_HB8CFG_MAXWAIT_S, EPI_O_HB8CFG, EPI_O_HB8CFG2, and HWREG.

EPIConfigHB16Set()

void EPIConfigHB16Set	(	uint32_t	ui32Base,
		uint32_t	ui32Config,
		uint32_t	ui32MaxWait
	)

Configures the interface for Host-bus 16 operation.

Parameters

ui32Base	is the EPI module base address.
ui32Config	is the interface configuration.
ui32MaxWait	is the maximum number of external clocks to wait if a FIFO ready signal is holding off the transaction.

This function is used to configure the interface when used in Host-bus 16 operation as chosen with the function EPIModeSet(). The parameter ui32Config is the logical OR of the following:

• Host-bus 16 submode, select one of:
  • EPI_HB16_MODE_ADMUX sets data and address muxed, AD[15:0].
  • EPI_HB16_MODE_ADDEMUX sets up data and address as separate, D[15:0].
  • EPI_HB16_MODE_SRAM sets as EPI_HB16_MODE_ADDEMUX but uses address switch for multiple reads instead of OEn strobing, D[15:0].
  • EPI_HB16_MODE_FIFO addes XFIFO controls with sense of XFIFO full and XFIFO empty, D[15:0]. This submode uses no address or ALE.
• EPI_HB16_USE_TXEMPTY enables TXEMPTY signal with FIFO.
• EPI_HB16_USE_RXFULL enables RXFULL signal with FIFO.
• EPI_HB16_WRHIGH use active high write strobe, otherwise it is active low.
• EPI_HB16_RDHIGH use active high read strobe, otherwise it is active low.
• Write wait state, select one of:
  • EPI_HB16_WRWAIT_0 sets write wait state to 2 EPI clocks.
  • EPI_HB16_WRWAIT_1 sets write wait state to 4 EPI clocks.
  • EPI_HB16_WRWAIT_2 sets write wait state to 6 EPI clocks.
  • EPI_HB16_WRWAIT_3 sets write wait state to 8 EPI clocks.
• Read wait state, select one of:
  • EPI_HB16_RDWAIT_0 sets read wait state to 2 EPI clocks.
  • EPI_HB16_RDWAIT_1 sets read wait state to 4 EPI clocks.
  • EPI_HB16_RDWAIT_2 sets read wait state to 6 EPI clocks.
  • EPI_HB16_RDWAIT_3 sets read wait state to 8 EPI clocks.
• EPI_HB16_CLOCK_GATE_IDLE holds the EPI clock low when no data is available to read or write.
• EPI_HB16_CLOCK_INVERT inverts the EPI clock.
• EPI_HB16_IN_READY_EN sets EPIS032 as a ready/stall signal, active high.
• EPI_HB16_IN_READY_EN_INVERTED sets EPIS032 as ready/stall signal, active low.
• Address latch logic, select one of:
  • EPI_HB16_ALE_HIGH sets the address latch active high (default).
  • EPI_HB16_ALE_LOW sets address latch active low.
• EPI_HB16_BURST_TRAFFIC enables burst traffic. Only valid with EPI_HB16_MODE_ADMUX and a chip select configuration that utilizes an ALE.
• EPI_HB16_BSEL enables byte selects. In this mode, two EPI signals operate as byte selects allowing 8-bit transfers. If this flag is not specified, data must be read and written using only 16-bit transfers.
• EPI_HB16_CSBAUD use different baud rates when accessing devices on each chip select. CS0n uses the baud rate specified by the lower 16 bits of the divider passed to EPIDividerSet() and CS1n uses the divider passed in the upper 16 bits. If this option is absent, both chip selects use the baud rate resulting from the divider in the lower 16 bits of the parameter passed to EPIDividerSet().

If EPI_HB16_CSBAUD is configured, EPIDividerCSSet() should be used to to configure the divider for CS2n and CS3n. They both also use the lower 16 bits passed to EPIDividerSet() if this option is absent.

The use of EPI_HB16_CSBAUD also allows for unique chip select configurations. CS0n, CS1n, CS2n, and CS3n can each be configured by calling EPIConfigHB16CSSet() if EPI_HB16_CSBAUD is used. Otherwise, the configuration provided in ui32Config is used for all chip selects.

• Chip select configuration, select one of:
  • EPI_HB16_CSCFG_CS sets EPIS030 to operate as a chip select signal.
  • EPI_HB16_CSCFG_ALE sets EPIS030 to operate as an address latch (ALE).
  • EPI_HB16_CSCFG_DUAL_CS sets EPIS030 to operate as CS0n and EPIS027 as CS1n with the asserted chip select determined from the most significant address bit for the respective external address map.
  • EPI_HB16_CSCFG_ALE_DUAL_CS sets EPIS030 as an address latch (ALE), EPIS027 as CS0n and EPIS026 as CS1n with the asserted chip select determined from the most significant address bit for the respective external address map.
  • EPI_HB16_CSCFG_ALE_SINGLE_CS sets EPIS030 to operate as an address latch (ALE) and EPIS027 is used as a chip select.
  • EPI_HB16_CSCFG_QUAD_CS sets EPIS030 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 as CS3n.
  • EPI_HB16_CSCFG_ALE_QUAD_CS sets EPIS030 as an address latch (ALE), EPIS026 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 as CS3n.

    Note

    Dual or quad chip select configurations cannot be used with EPI_HB16_MODE_SRAM.

    The parameter ui32MaxWait is used if the FIFO mode is chosen. If a FIFO is used along with RXFULL or TXEMPTY ready signals, then this parameter determines the maximum number of clocks to wait when the transaction is being held off by by the FIFO using one of these ready signals. A value of 0 means to wait forever.

Returns

None.

References ASSERT, EPI_HB16_CSBAUD, EPI_HB16_CSCFG_MASK, EPI_HB16CFG2_CSBAUD, EPI_HB16CFG_MAXWAIT_M, EPI_HB16CFG_MAXWAIT_S, EPI_O_HB16CFG, EPI_O_HB16CFG2, and HWREG.

EPIConfigHB8CSSet()

void EPIConfigHB8CSSet	(	uint32_t	ui32Base,
		uint32_t	ui32CS,
		uint32_t	ui32Config
	)

Sets the individual chip select configuration for the Host-bus 8 interface.

Parameters

ui32Base	is the EPI module base address.
ui32CS	is the chip select value to configure.
ui32Config	is the configuration settings.

This function is used to configure individual chip select settings for the Host-bus 8 interface mode. EPIConfigHB8Set() must have been setup with the EPI_HB8_CSBAUD flag for the individual chip select configuration option to be available.

The ui32Base parameter is the base address for the EPI hardware module. The ui32CS parameter specifies the chip select to configure and has a valid range of 0-3. The parameter ui32Config is the logical OR of the following:

• Host-bus 8 submode, select one of:
  • EPI_HB8_MODE_ADMUX sets data and address muxed, AD[7:0].
  • EPI_HB8_MODE_ADDEMUX sets up data and address separate, D[7:0].
  • EPI_HB8_MODE_SRAM as EPI_HB8_MODE_ADDEMUX, but uses address switch for multiple reads instead of OEn strobing, D[7:0].
  • EPI_HB8_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO empty, D[7:0]. This is only available for CS0n and CS1n.
• EPI_HB8_WRHIGH sets active high write strobe, otherwise it is active low.
• EPI_HB8_RDHIGH sets active high read strobe, otherwise it is active low.
• Write wait state when EPI_HB8_BAUD is used, select one of:
  • EPI_HB8_WRWAIT_0 sets write wait state to 2 EPI clocks (default).
  • EPI_HB8_WRWAIT_1 sets write wait state to 4 EPI clocks.
  • EPI_HB8_WRWAIT_2 sets write wait state to 6 EPI clocks.
  • EPI_HB8_WRWAIT_3 sets write wait state to 8 EPI clocks.
• Read wait state when EPI_HB8_BAUD is used, select one of:
  • EPI_HB8_RDWAIT_0 sets read wait state to 2 EPI clocks (default).
  • EPI_HB8_RDWAIT_1 sets read wait state to 4 EPI clocks.
  • EPI_HB8_RDWAIT_2 sets read wait state to 6 EPI clocks.
  • EPI_HB8_RDWAIT_3 sets read wait state to 8 EPI clocks.
• EPI_HB8_ALE_HIGH sets the address latch active high (default).
• EPI_HB8_ALE_LOW sets address latch active low.

Returns

None.

References ASSERT, EPI_HB8_CS_MASK, EPI_O_HB8CFG, EPI_O_HB8CFG3, and HWREG.

EPIConfigHB16CSSet()

void EPIConfigHB16CSSet	(	uint32_t	ui32Base,
		uint32_t	ui32CS,
		uint32_t	ui32Config
	)

Sets the individual chip select configuration for the Host-bus 16 interface.

Parameters

ui32Base	is the EPI module base address.
ui32CS	is the chip select value to configure.
ui32Config	is the configuration settings.

This function is used to configure individual chip select settings for the Host-bus 16 interface mode. EPIConfigHB16Set() must have been set up with the EPI_HB16_CSBAUD flag for the individual chip select configuration option to be available.

The ui32Base parameter is the base address for the EPI hardware module. The ui32CS parameter specifies the chip select to configure and has a valid range of 0-3. The parameter ui32Config is the logical OR the following:

• Host-bus 16 submode, select one of:
  • EPI_HB16_MODE_ADMUX sets data and address muxed, AD[15:0].
  • EPI_HB16_MODE_ADDEMUX sets up data and address separate, D[15:0].
  • EPI_HB16_MODE_SRAM same as EPI_HB8_MODE_ADDEMUX, but uses address switch for multiple reads instead of OEn strobing, D[15:0].
  • EPI_HB16_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO empty, D[15:0]. This feature is only available on CS0n and CS1n.
• EPI_HB16_WRHIGH sets active high write strobe, otherwise it is active low.
• EPI_HB16_RDHIGH sets active high read strobe, otherwise it is active low.
• Write wait state when EPI_HB16_BAUD is used, select one of:
  • EPI_HB16_WRWAIT_0 sets write wait state to 2 EPI clocks (default).
  • EPI_HB16_WRWAIT_1 sets write wait state to 4 EPI clocks.
  • EPI_HB16_WRWAIT_2 sets write wait state to 6 EPI clocks.
  • EPI_HB16_WRWAIT_3 sets write wait state to 8 EPI clocks.
• Read wait state when EPI_HB16_BAUD is used, select one of:
  • EPI_HB16_RDWAIT_0 sets read wait state to 2 EPI clocks (default).
  • EPI_HB16_RDWAIT_1 sets read wait state to 4 EPI clocks.
  • EPI_HB16_RDWAIT_2 sets read wait state to 6 EPI clocks.
  • EPI_HB16_RDWAIT_3 sets read wait state to 8 EPI clocks.
• EPI_HB16_ALE_HIGH sets the address latch active high (default).
• EPI_HB16_ALE_LOW sets address latch active low.
• EPI_HB16_BURST_TRAFFIC enables burst traffic. Only valid with EPI_HB16_MODE_ADMUX and a chip select configuration that utilizes an ALE.

Returns

None.

References ASSERT, EPI_HB16_CS_MASK, EPI_O_HB16CFG, EPI_O_HB16CFG3, and HWREG.

EPIConfigHB8TimingSet()

void EPIConfigHB8TimingSet	(	uint32_t	ui32Base,
		uint32_t	ui32CS,
		uint32_t	ui32Config
	)

Sets the individual chip select timing settings for the Host-bus 8 interface.

Parameters

ui32Base	is the EPI module base address.
ui32CS	is the chip select value to configure.
ui32Config	is the configuration settings.

This function is used to set individual chip select timings for the Host-bus 8 interface mode.

The ui32Base parameter is the base address for the EPI hardware module. The ui32CS parameter specifies the chip select to configure and has a valid range of 0-3. The parameter ui32Config is the logical OR of the following:

• Input ready stall delay, select one of:
  • EPI_HB8_IN_READY_DELAY_1 sets the stall on input ready (EPIS032) to start 1 EPI clock after signaled.
  • EPI_HB8_IN_READY_DELAY_2 sets the stall on input ready (EPIS032) to start 2 EPI clocks after signaled.
  • EPI_HB8_IN_READY_DELAY_3 sets the stall on input ready (EPIS032) to start 3 EPI clocks after signaled.
• Host bus transfer delay, select one of:
  • EPI_HB8_CAP_WIDTH_1 defines the inter-transfer capture width to create a delay of 1 EPI clock.
  • EPI_HB8_CAP_WIDTH_2 defines the inter-transfer capture width to create a delay of 2 EPI clocks.
• EPI_HB8_WRWAIT_MINUS_DISABLE disables the additional write wait state reduction.
• EPI_HB8_WRWAIT_MINUS_ENABLE enables a 1 EPI clock write wait state reduction.
• EPI_HB8_RDWAIT_MINUS_DISABLE disables the additional read wait state reduction.
• EPI_HB8_RDWAIT_MINUS_ENABLE enables a 1 EPI clock read wait state reduction.

Returns

None.

References ASSERT, EPI_O_HB8TIME, and HWREG.

EPIConfigHB16TimingSet()

void EPIConfigHB16TimingSet	(	uint32_t	ui32Base,
		uint32_t	ui32CS,
		uint32_t	ui32Config
	)

Sets the individual chip select timing settings for the Host-bus 16 interface.

Parameters

ui32Base	is the EPI module base address.
ui32CS	is the chip select value to configure.
ui32Config	is the configuration settings.

This function is used to set individual chip select timings for the Host-bus 16 interface mode.

The ui32Base parameter is the base address for the EPI hardware module. The ui32CS parameter specifies the chip select to configure and has a valid range of 0-3. The parameter ui32Config is the logical OR of the following:

• Input ready stall delay, select one of:
  • EPI_HB16_IN_READY_DELAY_1 sets the stall on input ready (EPIS032) to start 1 EPI clock after signaled.
  • EPI_HB16_IN_READY_DELAY_2 sets the stall on input ready (EPIS032) to start 2 EPI clocks after signaled.
  • EPI_HB16_IN_READY_DELAY_3 sets the stall on input ready (EPIS032) to start 3 EPI clocks after signaled.
• PSRAM size limitation, select one of:
  • EPI_HB16_PSRAM_NO_LIMIT defines no row size limitation.
  • EPI_HB16_PSRAM_128 defines the PSRAM row size to 128 bytes.
  • EPI_HB16_PSRAM_256 defines the PSRAM row size to 256 bytes.
  • EPI_HB16_PSRAM_512 defines the PSRAM row size to 512 bytes.
  • EPI_HB16_PSRAM_1024 defines the PSRAM row size to 1024 bytes.
  • EPI_HB16_PSRAM_2048 defines the PSRAM row size to 2048 bytes.
  • EPI_HB16_PSRAM_4096 defines the PSRAM row size to 4096 bytes.
  • EPI_HB16_PSRAM_8192 defines the PSRAM row size to 8192 bytes.
• Host bus transfer delay, select one of:
  • EPI_HB16_CAP_WIDTH_1 defines the inter-transfer capture width to create a delay of 1 EPI clock
  • EPI_HB16_CAP_WIDTH_2 defines the inter-transfer capture width to create a delay of 2 EPI clocks.
• Write wait state timing reduction, select one of:
  • EPI_HB16_WRWAIT_MINUS_DISABLE disables the additional write wait state reduction.
  • EPI_HB16_WRWAIT_MINUS_ENABLE enables a 1 EPI clock write wait state reduction.
• Read wait state timing reduction, select one of:
  • EPI_HB16_RDWAIT_MINUS_DISABLE disables the additional read wait state reduction.
  • EPI_HB16_RDWAIT_MINUS_ENABLE enables a 1 EPI clock read wait state reduction.

Returns

None.

References ASSERT, EPI_O_HB16TIME, and HWREG.

EPIPSRAMConfigRegSet()

void EPIPSRAMConfigRegSet	(	uint32_t	ui32Base,
		uint32_t	ui32CS,
		uint32_t	ui32CR
	)

Sets the PSRAM configuration register.

Parameters

ui32Base	is the EPI module base address.
ui32CS	is the chip select target.
ui32CR	is the PSRAM configuration register value.

This function sets the PSRAM's configuration register by using the PSRAM configuration register enable signal. The Host-bus 16 interface mode should be configured prior to calling this function.

The ui32Base parameter is the base address for the EPI hardware module. The ui32CS parameter specifies the chip select to configure and has a valid range of 0-3. The parameter ui32CR value is determined by consulting the PSRAM's data sheet.

Returns

None.

References ASSERT, EPI_HB16CFG_WRCRE, EPI_O_HB16CFG, EPI_O_HB16CFG3, EPI_O_HBPSRAM, and HWREG.

EPIPSRAMConfigRegRead()

void EPIPSRAMConfigRegRead	(	uint32_t	ui32Base,
		uint32_t	ui32CS
	)

Requests a configuration register read from the PSRAM.

Parameters

ui32Base	is the EPI module base address.
ui32CS	is the chip select target.

This function requests a read of the PSRAM's configuration register. The Host-bus 16 interface mode should be configured prior to calling this function. The EPIPSRAMConfigRegGet() and EPIPSRAMConfigRegGetNonBlocking() can be used to retrieve the configuration register value.

The ui32Base parameter is the base address for the EPI hardware module. The ui32CS parameter specifies the chip select to configure and has a valid range of 0-3.

Returns

none.

References ASSERT, EPI_HB16CFG_RDCRE, EPI_O_HB16CFG, EPI_O_HB16CFG3, and HWREG.

EPIPSRAMConfigRegGetNonBlocking()

bool EPIPSRAMConfigRegGetNonBlocking	(	uint32_t	ui32Base,
		uint32_t	ui32CS,
		uint32_t *	pui32CR
	)

Retrieves the contents of the EPI PSRAM configuration register.

Parameters

ui32Base	is the EPI module base address.
ui32CS	is the chip select target.
pui32CR	is the provided storage used to hold the register value.

This function copies the contents of the EPI PSRAM configuration register to the provided storage if the PSRAM read configuration register enable is no longer asserted. Otherwise the provided storage is not modified.

The Host-bus 16 interface mode should be set up and EPIPSRAMConfigRegRead() should be called prior to calling this function.

The ui32Base parameter is the base address for the EPI hardware module. The ui32CS parameter specifies the chip select to configure and has a valid range of 0-3. The pui32CR parameter is a pointer to provided storage used to hold the register value.

Returns

true if the value was copied to the provided storage and false if it was not.

References ASSERT, EPI_HB16CFG_RDCRE, EPI_O_HB16CFG, EPI_O_HB16CFG3, EPI_O_HBPSRAM, and HWREG.

EPIPSRAMConfigRegGet()

uint32_t EPIPSRAMConfigRegGet	(	uint32_t	ui32Base,
		uint32_t	ui32CS
	)

Retrieves the contents of the EPI PSRAM configuration register.

Parameters

ui32Base	is the EPI module base address.
ui32CS	is the chip select target.

This function retrieves the EPI PSRAM configuration register. The register is read once the EPI PSRAM configuration register read enable signal is de-asserted.

The Host-bus 16 interface mode should be set up and EPIPSRAMConfigRegRead() should be called prior to calling this function.

The ui32Base parameter is the base address for the EPI hardware module. The ui32CS parameter specifies the chip select to configure and has a valid range of 0-3.

Returns

none.

References ASSERT, EPI_HB16CFG_RDCRE, EPI_O_HB16CFG, EPI_O_HB16CFG3, EPI_O_HBPSRAM, and HWREG.

EPIConfigGPModeSet()

void EPIConfigGPModeSet	(	uint32_t	ui32Base,
		uint32_t	ui32Config,
		uint32_t	ui32FrameCount,
		uint32_t	ui32MaxWait
	)

Configures the interface for general-purpose mode operation.

Parameters

ui32Base	is the EPI module base address.
ui32Config	is the interface configuration.
ui32FrameCount	is the frame size in clocks, if the frame signal is used (0-15).
ui32MaxWait	is currently not used.

This function is used to configure the interface when used in general-purpose operation as chosen with the function EPIModeSet(). The parameter ui32Config is the logical OR of the following:

• EPI_GPMODE_CLKPIN interface clock as output on a pin.
• EPI_GPMODE_CLKGATE clock is stopped when there is no transaction, otherwise it is free-running.
• EPI_GPMODE_FRAME50 framing signal is 50/50 duty cycle, otherwise it is a pulse.
• EPI_GPMODE_WRITE2CYCLE a two-cycle write is used, otherwise a single-cycle write is used.
• Address bus size, select one of:
  • EPI_GPMODE_ASIZE_NONE sets no address bus.
  • EPI_GPMODE_ASIZE_4 sets an address bus size of 4 bits.
  • EPI_GPMODE_ASIZE_12 sets an address bus size of 12 bits.
  • EPI_GPMODE_ASIZE_20 sets an address bus size of 20 bits.
• Data bus size, select one of:
  • EPI_GPMODE_DSIZE_8 sets a data bus size of 8 bits.
  • EPI_GPMODE_DSIZE_16 sets a data bus size of 16 bits.
  • EPI_GPMODE_DSIZE_24 sets a data bus size of 24 bits.
  • EPI_GPMODE_DSIZE_32 sets a data bus size of 32 bits.

The parameter ui32FrameCount is the number of clocks used to form the framing signal, if the framing signal is used. The behavior depends on whether the frame signal is a pulse or a 50/50 duty cycle.

Returns

None.

References ASSERT, EPI_GPCFG_FRMCNT_M, EPI_GPCFG_FRMCNT_S, EPI_O_GPCFG, and HWREG.

EPIAddressMapSet()

void EPIAddressMapSet	(	uint32_t	ui32Base,
		uint32_t	ui32Map
	)

Configures the address map for the external interface.

Parameters

ui32Base	is the EPI module base address.
ui32Map	is the address mapping configuration.

This function is used to configure the address mapping for the external interface, which then determines the base address of the external memory or device within the processor peripheral and/or memory space.

The parameter ui32Map is the logical OR of the following:

• Peripheral address space size, select one of:
  • EPI_ADDR_PER_SIZE_256B sets the peripheral address space to 256 bytes.
  • EPI_ADDR_PER_SIZE_64KB sets the peripheral address space to 64 Kbytes.
  • EPI_ADDR_PER_SIZE_16MB sets the peripheral address space to 16 Mbytes.
  • EPI_ADDR_PER_SIZE_256MB sets the peripheral address space to 256 Mbytes.
• Peripheral base address, select one of:
  • EPI_ADDR_PER_BASE_NONE sets the peripheral base address to none.
  • EPI_ADDR_PER_BASE_A sets the peripheral base address to 0xA0000000.
  • EPI_ADDR_PER_BASE_C sets the peripheral base address to 0xC0000000.
• RAM address space, select one of:
  • EPI_ADDR_RAM_SIZE_256B sets the RAM address space to 256 bytes.
  • EPI_ADDR_RAM_SIZE_64KB sets the RAM address space to 64 Kbytes.
  • EPI_ADDR_RAM_SIZE_16MB sets the RAM address space to 16 Mbytes.
  • EPI_ADDR_RAM_SIZE_256MB sets the RAM address space to 256 Mbytes.
• RAM base address, select one of:
  • EPI_ADDR_RAM_BASE_NONE sets the RAM space address to none.
  • EPI_ADDR_RAM_BASE_6 sets the RAM space address to 0x60000000.
  • EPI_ADDR_RAM_BASE_8 sets the RAM space address to 0x80000000.
• EPI_ADDR_QUAD_MODE maps CS0n to 0x60000000, CS1n to 0x80000000, CS2n to 0xA0000000, and CS3n to 0xC0000000.
• EPI_ADDR_CODE_SIZE_256B sets an external code size of 256 bytes, range 0x00 to 0xFF.
• EPI_ADDR_CODE_SIZE_64KB sets an external code size of 64 Kbytes, range 0x0000 to 0xFFFF.
• EPI_ADDR_CODE_SIZE_16MB sets an external code size of 16 Mbytes, range 0x000000 to 0xFFFFFF.
• EPI_ADDR_CODE_SIZE_256MB sets an external code size of 256 Mbytes, range 0x0000000 to 0xFFFFFFF.
• EPI_ADDR_CODE_BASE_NONE sets external code base to not mapped.
• EPI_ADDR_CODE_BASE_1 sets external code base to 0x10000000.

Returns

None.

References ASSERT, EPI_O_ADDRMAP, and HWREG.

EPINonBlockingReadConfigure()

void EPINonBlockingReadConfigure	(	uint32_t	ui32Base,
		uint32_t	ui32Channel,
		uint32_t	ui32DataSize,
		uint32_t	ui32Address
	)

Configures a non-blocking read transaction.

Parameters

ui32Base	is the EPI module base address.
ui32Channel	is the read channel (0 or 1).
ui32DataSize	is the size of the data items to read.
ui32Address	is the starting address to read.

This function is used to configure a non-blocking read channel for a transaction. Two channels are available that can be used in a ping-pong method for continuous reading. It is not necessary to use both channels to perform a non-blocking read.

The parameter ui8DataSize is one of EPI_NBCONFIG_SIZE_8, EPI_NBCONFIG_SIZE_16, or EPI_NBCONFIG_SIZE_32 for 8-bit, 16-bit, or 32-bit sized data transfers.

The parameter ui32Address is the starting address for the read, relative to the external device. The start of the device is address 0.

Once configured, the non-blocking read is started by calling EPINonBlockingReadStart(). If the addresses to be read from the device are in a sequence, it is not necessary to call this function multiple times. Until it is changed, the EPI module stores the last address that was used for a non-blocking read (per channel).

Returns

None.

References ASSERT, EPI_O_RADDR0, EPI_O_RSIZE0, EPI_O_RSIZE1, and HWREG.

EPINonBlockingReadStart()

void EPINonBlockingReadStart	(	uint32_t	ui32Base,
		uint32_t	ui32Channel,
		uint32_t	ui32Count
	)

Starts a non-blocking read transaction.

Parameters

ui32Base	is the EPI module base address.
ui32Channel	is the read channel (0 or 1).
ui32Count	is the number of items to read (1-4095).

This function starts a non-blocking read that was previously configured with the function EPINonBlockingReadConfigure(). Once this function is called, the EPI module begins reading data from the external device into the read FIFO. The EPI stops reading when the FIFO fills up and resumes reading when the application drains the FIFO, until the total specified count of data items has been read.

Once a read transaction is completed and the FIFO drained, another transaction can be started from the next address by calling this function again.

Returns

None.

References ASSERT, EPI_O_RPSTD0, EPI_O_RPSTD1, and HWREG.

EPINonBlockingReadStop()

void EPINonBlockingReadStop	(	uint32_t	ui32Base,
		uint32_t	ui32Channel
	)

Stops a non-blocking read transaction.

Parameters

ui32Base	is the EPI module base address.
ui32Channel	is the read channel (0 or 1).

This function cancels a non-blocking read transaction that is already in progress.

Returns

None.

References ASSERT, EPI_O_RPSTD0, EPI_O_RPSTD1, and HWREG.

EPINonBlockingReadCount()

uint32_t EPINonBlockingReadCount	(	uint32_t	ui32Base,
		uint32_t	ui32Channel
	)

Get the count remaining for a non-blocking transaction.

Parameters

ui32Base	is the EPI module base address.
ui32Channel	is the read channel (0 or 1).

This function gets the remaining count of items for a non-blocking read transaction.

Returns

The number of items remaining in the non-blocking read transaction.

References ASSERT, EPI_O_RPSTD0, EPI_O_RPSTD1, and HWREG.

EPINonBlockingReadAvail()

uint32_t EPINonBlockingReadAvail

(

uint32_t

ui32Base

)

Get the count of items available in the read FIFO.

Parameters

ui32Base

is the EPI module base address.

This function gets the number of items that are available to read in the read FIFO. The read FIFO is filled by a non-blocking read transaction which is configured by the functions EPINonBlockingReadConfigure() and EPINonBlockingReadStart().

Returns

The number of items available to read in the read FIFO.

References ASSERT, EPI_O_RFIFOCNT, and HWREG.

EPINonBlockingReadGet32()

uint32_t EPINonBlockingReadGet32	(	uint32_t	ui32Base,
		uint32_t	ui32Count,
		uint32_t *	pui32Buf
	)

Read available data from the read FIFO, as 32-bit data items.

Parameters

ui32Base	is the EPI module base address.
ui32Count	is the maximum count of items to read.
pui32Buf	is the caller supplied buffer where the read data is stored.

This function reads 32-bit data items from the read FIFO and stores the values in a caller-supplied buffer. The function reads and stores data from the FIFO until there is no more data in the FIFO or the maximum count is reached as specified in the parameter ui32Count. The actual count of items is returned.

Returns

The number of items read from the FIFO.

References ASSERT, EPI_O_READFIFO0, EPI_O_RFIFOCNT, and HWREG.

EPINonBlockingReadGet16()

uint32_t EPINonBlockingReadGet16	(	uint32_t	ui32Base,
		uint32_t	ui32Count,
		uint16_t *	pui16Buf
	)

Read available data from the read FIFO, as 16-bit data items.

Parameters

ui32Base	is the EPI module base address.
ui32Count	is the maximum count of items to read.
pui16Buf	is the caller-supplied buffer where the read data is stored.

This function reads 16-bit data items from the read FIFO and stores the values in a caller-supplied buffer. The function reads and stores data from the FIFO until there is no more data in the FIFO or the maximum count is reached as specified in the parameter ui32Count. The actual count of items is returned.

Returns

The number of items read from the FIFO.

References ASSERT, EPI_O_READFIFO0, EPI_O_RFIFOCNT, and HWREG.

EPINonBlockingReadGet8()

uint32_t EPINonBlockingReadGet8	(	uint32_t	ui32Base,
		uint32_t	ui32Count,
		uint8_t *	pui8Buf
	)

Read available data from the read FIFO, as 8-bit data items.

Parameters

ui32Base	is the EPI module base address.
ui32Count	is the maximum count of items to read.
pui8Buf	is the caller-supplied buffer where the read data is stored.

This function reads 8-bit data items from the read FIFO and stores the values in a caller-supplied buffer. The function reads and stores data from the FIFO until there is no more data in the FIFO or the maximum count is reached as specified in the parameter ui32Count. The actual count of items is returned.

Returns

The number of items read from the FIFO.

References ASSERT, EPI_O_READFIFO0, EPI_O_RFIFOCNT, and HWREG.

EPIFIFOConfig()

void EPIFIFOConfig	(	uint32_t	ui32Base,
		uint32_t	ui32Config
	)

Configures the read FIFO.

Parameters

ui32Base	is the EPI module base address.
ui32Config	is the FIFO configuration.

This function configures the FIFO trigger levels and error generation. The parameter ui32Config is the logical OR of the following:

• EPI_FIFO_CONFIG_WTFULLERR enables an error interrupt when a write is attempted and the write FIFO is full
• EPI_FIFO_CONFIG_RSTALLERR enables an error interrupt when a read is stalled due to an interleaved write or other reason
• FIFO TX trigger level, select one of:
  • EPI_FIFO_CONFIG_TX_EMPTY sets the FIFO TX trigger level to empty.
  • EPI_FIFO_CONFIG_TX_1_4 sets the FIFO TX trigger level to 1/4.
  • EPI_FIFO_CONFIG_TX_1_2 sets the FIFO TX trigger level to 1/2.
  • EPI_FIFO_CONFIG_TX_3_4 sets the FIFO TX trigger level to 3/4.
• FIFO RX trigger level, select one of:
  • EPI_FIFO_CONFIG_RX_1_8 sets the FIFO RX trigger level to 1/8.
  • EPI_FIFO_CONFIG_RX_1_4 sets the FIFO RX trigger level to 1/4.
  • EPI_FIFO_CONFIG_RX_1_2 sets the FIFO RX trigger level to 1/2.
  • EPI_FIFO_CONFIG_RX_3_4 sets the FIFO RX trigger level to 3/4.
  • EPI_FIFO_CONFIG_RX_7_8 sets the FIFO RX trigger level to 7/8.
  • EPI_FIFO_CONFIG_RX_FULL sets the FIFO RX trigger level to full.

Returns

None.

References ASSERT, EPI_O_FIFOLVL, and HWREG.

EPIWriteFIFOCountGet()

uint32_t EPIWriteFIFOCountGet

(

uint32_t

ui32Base

)

Reads the number of empty slots in the write transaction FIFO.

Parameters

ui32Base

is the EPI module base address.

This function returns the number of slots available in the transaction FIFO. It can be used in a polling method to avoid attempting a write that would stall.

Returns

The number of empty slots in the transaction FIFO.

References ASSERT, EPI_O_WFIFOCNT, and HWREG.

EPIIntEnable()

void EPIIntEnable	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Enables EPI interrupt sources.

Parameters

ui32Base	is the EPI module base address.
ui32IntFlags	is a bit mask of the interrupt sources to be enabled.

This function enables the specified EPI sources to generate interrupts. The ui32IntFlags parameter can be the logical OR of any of the following values:

• EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level.
• EPI_INT_RXREQ interrupt when read FIFO is above the trigger level.
• EPI_INT_ERR interrupt when an error condition occurs.
• EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes.
• EPI_INT_DMA_RX_DONE interrupt when the read DMA completes.

Returns

Returns None.

References ASSERT, EPI_O_IM, and HWREG.

EPIIntDisable()

void EPIIntDisable	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Disables EPI interrupt sources.

Parameters

ui32Base	is the EPI module base address.
ui32IntFlags	is a bit mask of the interrupt sources to be disabled.

This function disables the specified EPI sources for interrupt generation. The ui32IntFlags parameter can be the logical OR of any of the following values:

• EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level.
• EPI_INT_RXREQ interrupt when read FIFO is above the trigger level.
• EPI_INT_ERR interrupt when an error condition occurs.
• EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes.
• EPI_INT_DMA_RX_DONE interrupt when the read DMA completes.

Returns

Returns None.

References ASSERT, EPI_O_IM, and HWREG.

EPIIntStatus()

uint32_t EPIIntStatus	(	uint32_t	ui32Base,
		bool	bMasked
	)

Gets the EPI interrupt status.

Parameters

ui32Base	is the EPI module base address.
bMasked	is set true to get the masked interrupt status, or false to get the raw interrupt status.

This function returns the EPI interrupt status. It can return either the raw or masked interrupt status.

Returns

Returns the masked or raw EPI interrupt status, as a bit field of any of the following values:

• EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level.
• EPI_INT_RXREQ interrupt when read FIFO is above the trigger level.
• EPI_INT_ERR interrupt when an error condition occurs.
• EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes.
• EPI_INT_DMA_RX_DONE interrupt when the read DMA completes.

References ASSERT, EPI_O_MIS, EPI_O_RIS, and HWREG.

EPIIntErrorStatus()

uint32_t EPIIntErrorStatus

(

uint32_t

ui32Base

)

Gets the EPI error interrupt status.

Parameters

ui32Base

is the EPI module base address.

This function returns the error status of the EPI. If the return value of the function EPIIntStatus() has the flag EPI_INT_ERR set, then this function can be used to determine the cause of the error.

Returns

Returns a bit mask of error flags, which can be the logical OR of any of the following:

• EPI_INT_ERR_WTFULL occurs when a write stalled when the transaction FIFO was full
• EPI_INT_ERR_RSTALL occurs when a read stalled
• EPI_INT_ERR_TIMEOUT occurs when the external clock enable held off a transaction longer than the configured maximum wait time

References ASSERT, EPI_O_EISC, and HWREG.

EPIIntErrorClear()

void EPIIntErrorClear	(	uint32_t	ui32Base,
		uint32_t	ui32ErrFlags
	)

Clears pending EPI error sources.

Parameters

ui32Base	is the EPI module base address.
ui32ErrFlags	is a bit mask of the error sources to be cleared.

This function clears the specified pending EPI errors. The ui32ErrFlags parameter can be the logical OR of any of the following values:

• EPI_INT_ERR_DMAWRIC clears the EPI_INT_DMA_TX_DONE as an interrupt source
• EPI_INT_ERR_DMARDIC clears the EPI_INT_DMA_RX_DONE as an interrupt source
• EPI_INT_ERR_WTFULL occurs when a write stalled when the transaction FIFO was full
• EPI_INT_ERR_RSTALL occurs when a read stalled
• EPI_INT_ERR_TIMEOUT occurs when the external clock enable held off a transaction longer than the configured maximum wait time

Returns

Returns None.

References ASSERT, EPI_O_EISC, and HWREG.

EPIIntRegister()

void EPIIntRegister	(	uint32_t	ui32Base,
		void(*)(void)	pfnHandler
	)

Registers an interrupt handler for the EPI module.

Parameters

ui32Base	is the EPI module base address.
pfnHandler	is a pointer to the function to be called when the interrupt is activated.

This sets and enables the handler to be called when the EPI module generates an interrupt. Specific EPI interrupts must still be enabled with the EPIIntEnable() function.

See also

IntRegister() for important information about registering interrupt handlers.

Returns

None.

References ASSERT.

EPIIntUnregister()

void EPIIntUnregister

(

uint32_t

ui32Base

)

Removes a registered interrupt handler for the EPI module.

Parameters

ui32Base

is the EPI module base address.

This function disables and clears the handler to be called when the EPI interrupt occurs.

See also

IntRegister() for important information about registering interrupt handlers.

Returns

None.

References ASSERT.