This graph shows which files directly or indirectly include this file:

Macros
#define	UDMA_STAT 0x400FF000

#define	UDMA_CFG 0x400FF004

#define	UDMA_CTLBASE 0x400FF008

#define	UDMA_ALTBASE 0x400FF00C

#define	UDMA_WAITSTAT 0x400FF010

#define	UDMA_SWREQ 0x400FF014

#define	UDMA_USEBURSTSET 0x400FF018

#define	UDMA_USEBURSTCLR 0x400FF01C

#define	UDMA_REQMASKSET 0x400FF020

#define	UDMA_REQMASKCLR 0x400FF024

#define	UDMA_ENASET 0x400FF028

#define	UDMA_ENACLR 0x400FF02C

#define	UDMA_ALTSET 0x400FF030

#define	UDMA_ALTCLR 0x400FF034

#define	UDMA_PRIOSET 0x400FF038

#define	UDMA_PRIOCLR 0x400FF03C

#define	UDMA_ERRCLR 0x400FF04C

#define	UDMA_CHASGN 0x400FF500

#define	UDMA_CHMAP0 0x400FF510

#define	UDMA_CHMAP1 0x400FF514

#define	UDMA_CHMAP2 0x400FF518

#define	UDMA_CHMAP3 0x400FF51C

#define	UDMA_STAT_DMACHANS_M 0x001F0000

#define	UDMA_STAT_STATE_M 0x000000F0

#define	UDMA_STAT_STATE_IDLE 0x00000000

#define	UDMA_STAT_STATE_RD_CTRL 0x00000010

#define	UDMA_STAT_STATE_RD_SRCENDP 0x00000020

#define	UDMA_STAT_STATE_RD_DSTENDP 0x00000030

#define	UDMA_STAT_STATE_RD_SRCDAT 0x00000040

#define	UDMA_STAT_STATE_WR_DSTDAT 0x00000050

#define	UDMA_STAT_STATE_WAIT 0x00000060

#define	UDMA_STAT_STATE_WR_CTRL 0x00000070

#define	UDMA_STAT_STATE_STALL 0x00000080

#define	UDMA_STAT_STATE_DONE 0x00000090

#define	UDMA_STAT_STATE_UNDEF 0x000000A0

#define	UDMA_STAT_MASTEN 0x00000001

#define	UDMA_STAT_DMACHANS_S 16

#define	UDMA_CFG_MASTEN 0x00000001

#define	UDMA_CTLBASE_ADDR_M 0xFFFFFC00

#define	UDMA_CTLBASE_ADDR_S 10

#define	UDMA_ALTBASE_ADDR_M 0xFFFFFFFF

#define	UDMA_ALTBASE_ADDR_S 0

#define	UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF

#define	UDMA_SWREQ_M 0xFFFFFFFF

#define	UDMA_USEBURSTSET_SET_M 0xFFFFFFFF

#define	UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF

#define	UDMA_REQMASKSET_SET_M 0xFFFFFFFF

#define	UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF

#define	UDMA_ENASET_SET_M 0xFFFFFFFF

#define	UDMA_ENACLR_CLR_M 0xFFFFFFFF

#define	UDMA_ALTSET_SET_M 0xFFFFFFFF

#define	UDMA_ALTCLR_CLR_M 0xFFFFFFFF

#define	UDMA_PRIOSET_SET_M 0xFFFFFFFF

#define	UDMA_PRIOCLR_CLR_M 0xFFFFFFFF

#define	UDMA_ERRCLR_ERRCLR 0x00000001

#define	UDMA_CHASGN_M 0xFFFFFFFF

#define	UDMA_CHASGN_PRIMARY 0x00000000

#define	UDMA_CHASGN_SECONDARY 0x00000001

#define	UDMA_CHIS_M 0xFFFFFFFF

#define	UDMA_CHMAP0_CH7SEL_M 0xF0000000

#define	UDMA_CHMAP0_CH6SEL_M 0x0F000000

#define	UDMA_CHMAP0_CH5SEL_M 0x00F00000

#define	UDMA_CHMAP0_CH4SEL_M 0x000F0000

#define	UDMA_CHMAP0_CH3SEL_M 0x0000F000

#define	UDMA_CHMAP0_CH2SEL_M 0x00000F00

#define	UDMA_CHMAP0_CH1SEL_M 0x000000F0

#define	UDMA_CHMAP0_CH0SEL_M 0x0000000F

#define	UDMA_CHMAP0_CH7SEL_S 28

#define	UDMA_CHMAP0_CH6SEL_S 24

#define	UDMA_CHMAP0_CH5SEL_S 20

#define	UDMA_CHMAP0_CH4SEL_S 16

#define	UDMA_CHMAP0_CH3SEL_S 12

#define	UDMA_CHMAP0_CH2SEL_S 8

#define	UDMA_CHMAP0_CH1SEL_S 4

#define	UDMA_CHMAP0_CH0SEL_S 0

#define	UDMA_CHMAP1_CH15SEL_M 0xF0000000

#define	UDMA_CHMAP1_CH14SEL_M 0x0F000000

#define	UDMA_CHMAP1_CH13SEL_M 0x00F00000

#define	UDMA_CHMAP1_CH12SEL_M 0x000F0000

#define	UDMA_CHMAP1_CH11SEL_M 0x0000F000

#define	UDMA_CHMAP1_CH10SEL_M 0x00000F00

#define	UDMA_CHMAP1_CH9SEL_M 0x000000F0

#define	UDMA_CHMAP1_CH8SEL_M 0x0000000F

#define	UDMA_CHMAP1_CH15SEL_S 28

#define	UDMA_CHMAP1_CH14SEL_S 24

#define	UDMA_CHMAP1_CH13SEL_S 20

#define	UDMA_CHMAP1_CH12SEL_S 16

#define	UDMA_CHMAP1_CH11SEL_S 12

#define	UDMA_CHMAP1_CH10SEL_S 8

#define	UDMA_CHMAP1_CH9SEL_S 4

#define	UDMA_CHMAP1_CH8SEL_S 0

#define	UDMA_CHMAP2_CH23SEL_M 0xF0000000

#define	UDMA_CHMAP2_CH22SEL_M 0x0F000000

#define	UDMA_CHMAP2_CH21SEL_M 0x00F00000

#define	UDMA_CHMAP2_CH20SEL_M 0x000F0000

#define	UDMA_CHMAP2_CH19SEL_M 0x0000F000

#define	UDMA_CHMAP2_CH18SEL_M 0x00000F00

#define	UDMA_CHMAP2_CH17SEL_M 0x000000F0

#define	UDMA_CHMAP2_CH16SEL_M 0x0000000F

#define	UDMA_CHMAP2_CH23SEL_S 28

#define	UDMA_CHMAP2_CH22SEL_S 24

#define	UDMA_CHMAP2_CH21SEL_S 20

#define	UDMA_CHMAP2_CH20SEL_S 16

#define	UDMA_CHMAP2_CH19SEL_S 12

#define	UDMA_CHMAP2_CH18SEL_S 8

#define	UDMA_CHMAP2_CH17SEL_S 4

#define	UDMA_CHMAP2_CH16SEL_S 0

#define	UDMA_CHMAP3_CH31SEL_M 0xF0000000

#define	UDMA_CHMAP3_CH30SEL_M 0x0F000000

#define	UDMA_CHMAP3_CH29SEL_M 0x00F00000

#define	UDMA_CHMAP3_CH28SEL_M 0x000F0000

#define	UDMA_CHMAP3_CH27SEL_M 0x0000F000

#define	UDMA_CHMAP3_CH26SEL_M 0x00000F00

#define	UDMA_CHMAP3_CH25SEL_M 0x000000F0

#define	UDMA_CHMAP3_CH24SEL_M 0x0000000F

#define	UDMA_CHMAP3_CH31SEL_S 28

#define	UDMA_CHMAP3_CH30SEL_S 24

#define	UDMA_CHMAP3_CH29SEL_S 20

#define	UDMA_CHMAP3_CH28SEL_S 16

#define	UDMA_CHMAP3_CH27SEL_S 12

#define	UDMA_CHMAP3_CH26SEL_S 8

#define	UDMA_CHMAP3_CH25SEL_S 4

#define	UDMA_CHMAP3_CH24SEL_S 0

#define	UDMA_O_SRCENDP 0x00000000

#define	UDMA_O_DSTENDP 0x00000004

#define	UDMA_O_CHCTL 0x00000008

#define	UDMA_SRCENDP_ADDR_M 0xFFFFFFFF

#define	UDMA_SRCENDP_ADDR_S 0

#define	UDMA_DSTENDP_ADDR_M 0xFFFFFFFF

#define	UDMA_DSTENDP_ADDR_S 0

#define	UDMA_CHCTL_DSTINC_M 0xC0000000

#define	UDMA_CHCTL_DSTINC_8 0x00000000

#define	UDMA_CHCTL_DSTINC_16 0x40000000

#define	UDMA_CHCTL_DSTINC_32 0x80000000

#define	UDMA_CHCTL_DSTINC_NONE 0xC0000000

#define	UDMA_CHCTL_DSTSIZE_M 0x30000000

#define	UDMA_CHCTL_DSTSIZE_8 0x00000000

#define	UDMA_CHCTL_DSTSIZE_16 0x10000000

#define	UDMA_CHCTL_DSTSIZE_32 0x20000000

#define	UDMA_CHCTL_SRCINC_M 0x0C000000

#define	UDMA_CHCTL_SRCINC_8 0x00000000

#define	UDMA_CHCTL_SRCINC_16 0x04000000

#define	UDMA_CHCTL_SRCINC_32 0x08000000

#define	UDMA_CHCTL_SRCINC_NONE 0x0C000000

#define	UDMA_CHCTL_SRCSIZE_M 0x03000000

#define	UDMA_CHCTL_SRCSIZE_8 0x00000000

#define	UDMA_CHCTL_SRCSIZE_16 0x01000000

#define	UDMA_CHCTL_SRCSIZE_32 0x02000000

#define	UDMA_CHCTL_DSTPROT0 0x00200000

#define	UDMA_CHCTL_SRCPROT0 0x00040000

#define	UDMA_CHCTL_ARBSIZE_M 0x0003C000

#define	UDMA_CHCTL_ARBSIZE_1 0x00000000

#define	UDMA_CHCTL_ARBSIZE_2 0x00004000

#define	UDMA_CHCTL_ARBSIZE_4 0x00008000

#define	UDMA_CHCTL_ARBSIZE_8 0x0000C000

#define	UDMA_CHCTL_ARBSIZE_16 0x00010000

#define	UDMA_CHCTL_ARBSIZE_32 0x00014000

#define	UDMA_CHCTL_ARBSIZE_64 0x00018000

#define	UDMA_CHCTL_ARBSIZE_128 0x0001C000

#define	UDMA_CHCTL_ARBSIZE_256 0x00020000

#define	UDMA_CHCTL_ARBSIZE_512 0x00024000

#define	UDMA_CHCTL_ARBSIZE_1024 0x00028000

#define	UDMA_CHCTL_XFERSIZE_M 0x00003FF0

#define	UDMA_CHCTL_NXTUSEBURST 0x00000008

#define	UDMA_CHCTL_XFERMODE_M 0x00000007

#define	UDMA_CHCTL_XFERMODE_STOP 0x00000000

#define	UDMA_CHCTL_XFERMODE_BASIC 0x00000001

#define	UDMA_CHCTL_XFERMODE_AUTO 0x00000002

#define	UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003

#define	UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004

#define	UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005

#define	UDMA_CHCTL_XFERMODE_PER_SG 0x00000006

#define	UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007

#define	UDMA_CHCTL_XFERSIZE_S 4

Macro Definition Documentation

§ UDMA_STAT

#define UDMA_STAT 0x400FF000

§ UDMA_CFG

#define UDMA_CFG 0x400FF004

Referenced by uDMADisable(), and uDMAEnable().

§ UDMA_CTLBASE

#define UDMA_CTLBASE 0x400FF008

Referenced by uDMAChannelControlSet(), uDMAChannelModeGet(), uDMAChannelScatterGatherSet(), uDMAChannelSizeGet(), uDMAChannelTransferSet(), uDMAControlBaseGet(), and uDMAControlBaseSet().

§ UDMA_ALTBASE

#define UDMA_ALTBASE 0x400FF00C

Referenced by uDMAControlAlternateBaseGet().

§ UDMA_WAITSTAT

#define UDMA_WAITSTAT 0x400FF010

§ UDMA_SWREQ

#define UDMA_SWREQ 0x400FF014

Referenced by uDMAChannelRequest().

§ UDMA_USEBURSTSET

#define UDMA_USEBURSTSET 0x400FF018

Referenced by uDMAChannelAttributeEnable(), and uDMAChannelAttributeGet().

§ UDMA_USEBURSTCLR

#define UDMA_USEBURSTCLR 0x400FF01C

Referenced by uDMAChannelAttributeDisable().

§ UDMA_REQMASKSET

#define UDMA_REQMASKSET 0x400FF020

Referenced by uDMAChannelAttributeEnable(), and uDMAChannelAttributeGet().

§ UDMA_REQMASKCLR

#define UDMA_REQMASKCLR 0x400FF024

Referenced by uDMAChannelAttributeDisable().

§ UDMA_ENASET

#define UDMA_ENASET 0x400FF028

Referenced by uDMAChannelEnable(), and uDMAChannelIsEnabled().

§ UDMA_ENACLR

#define UDMA_ENACLR 0x400FF02C

Referenced by uDMAChannelDisable().

§ UDMA_ALTSET

#define UDMA_ALTSET 0x400FF030

Referenced by uDMAChannelAttributeEnable(), and uDMAChannelAttributeGet().

§ UDMA_ALTCLR

#define UDMA_ALTCLR 0x400FF034

Referenced by uDMAChannelAttributeDisable(), and uDMAChannelScatterGatherSet().

§ UDMA_PRIOSET

#define UDMA_PRIOSET 0x400FF038

Referenced by uDMAChannelAttributeEnable(), and uDMAChannelAttributeGet().

§ UDMA_PRIOCLR

#define UDMA_PRIOCLR 0x400FF03C

Referenced by uDMAChannelAttributeDisable().

§ UDMA_ERRCLR

#define UDMA_ERRCLR 0x400FF04C

Referenced by uDMAErrorStatusClear(), and uDMAErrorStatusGet().

§ UDMA_CHASGN

#define UDMA_CHASGN 0x400FF500

§ UDMA_CHMAP0

#define UDMA_CHMAP0 0x400FF510

Referenced by uDMAChannelAssign().

§ UDMA_CHMAP1

#define UDMA_CHMAP1 0x400FF514

§ UDMA_CHMAP2

#define UDMA_CHMAP2 0x400FF518

§ UDMA_CHMAP3

#define UDMA_CHMAP3 0x400FF51C

§ UDMA_STAT_DMACHANS_M

#define UDMA_STAT_DMACHANS_M 0x001F0000

§ UDMA_STAT_STATE_M

#define UDMA_STAT_STATE_M 0x000000F0

§ UDMA_STAT_STATE_IDLE

#define UDMA_STAT_STATE_IDLE 0x00000000

§ UDMA_STAT_STATE_RD_CTRL

#define UDMA_STAT_STATE_RD_CTRL 0x00000010

§ UDMA_STAT_STATE_RD_SRCENDP

#define UDMA_STAT_STATE_RD_SRCENDP 0x00000020

§ UDMA_STAT_STATE_RD_DSTENDP

#define UDMA_STAT_STATE_RD_DSTENDP 0x00000030

§ UDMA_STAT_STATE_RD_SRCDAT

#define UDMA_STAT_STATE_RD_SRCDAT 0x00000040

§ UDMA_STAT_STATE_WR_DSTDAT

#define UDMA_STAT_STATE_WR_DSTDAT 0x00000050

§ UDMA_STAT_STATE_WAIT

#define UDMA_STAT_STATE_WAIT 0x00000060

§ UDMA_STAT_STATE_WR_CTRL

#define UDMA_STAT_STATE_WR_CTRL 0x00000070

§ UDMA_STAT_STATE_STALL

#define UDMA_STAT_STATE_STALL 0x00000080

§ UDMA_STAT_STATE_DONE

#define UDMA_STAT_STATE_DONE 0x00000090

§ UDMA_STAT_STATE_UNDEF

#define UDMA_STAT_STATE_UNDEF 0x000000A0

§ UDMA_STAT_MASTEN

#define UDMA_STAT_MASTEN 0x00000001

§ UDMA_STAT_DMACHANS_S

#define UDMA_STAT_DMACHANS_S 16

§ UDMA_CFG_MASTEN

#define UDMA_CFG_MASTEN 0x00000001

Referenced by uDMAEnable().

§ UDMA_CTLBASE_ADDR_M

#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00

§ UDMA_CTLBASE_ADDR_S

#define UDMA_CTLBASE_ADDR_S 10

§ UDMA_ALTBASE_ADDR_M

#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF

§ UDMA_ALTBASE_ADDR_S

#define UDMA_ALTBASE_ADDR_S 0

§ UDMA_WAITSTAT_WAITREQ_M

#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF

§ UDMA_SWREQ_M

#define UDMA_SWREQ_M 0xFFFFFFFF

§ UDMA_USEBURSTSET_SET_M

#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF

§ UDMA_USEBURSTCLR_CLR_M

#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF

§ UDMA_REQMASKSET_SET_M

#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF

§ UDMA_REQMASKCLR_CLR_M

#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF

§ UDMA_ENASET_SET_M

#define UDMA_ENASET_SET_M 0xFFFFFFFF

§ UDMA_ENACLR_CLR_M

#define UDMA_ENACLR_CLR_M 0xFFFFFFFF

§ UDMA_ALTSET_SET_M

#define UDMA_ALTSET_SET_M 0xFFFFFFFF

§ UDMA_ALTCLR_CLR_M

#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF

§ UDMA_PRIOSET_SET_M

#define UDMA_PRIOSET_SET_M 0xFFFFFFFF

§ UDMA_PRIOCLR_CLR_M

#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF

§ UDMA_ERRCLR_ERRCLR

#define UDMA_ERRCLR_ERRCLR 0x00000001

§ UDMA_CHASGN_M

#define UDMA_CHASGN_M 0xFFFFFFFF

§ UDMA_CHASGN_PRIMARY

#define UDMA_CHASGN_PRIMARY 0x00000000

§ UDMA_CHASGN_SECONDARY

#define UDMA_CHASGN_SECONDARY 0x00000001

§ UDMA_CHIS_M

#define UDMA_CHIS_M 0xFFFFFFFF

§ UDMA_CHMAP0_CH7SEL_M

#define UDMA_CHMAP0_CH7SEL_M 0xF0000000

§ UDMA_CHMAP0_CH6SEL_M

#define UDMA_CHMAP0_CH6SEL_M 0x0F000000

§ UDMA_CHMAP0_CH5SEL_M

#define UDMA_CHMAP0_CH5SEL_M 0x00F00000

§ UDMA_CHMAP0_CH4SEL_M

#define UDMA_CHMAP0_CH4SEL_M 0x000F0000

§ UDMA_CHMAP0_CH3SEL_M

#define UDMA_CHMAP0_CH3SEL_M 0x0000F000

§ UDMA_CHMAP0_CH2SEL_M

#define UDMA_CHMAP0_CH2SEL_M 0x00000F00

§ UDMA_CHMAP0_CH1SEL_M

#define UDMA_CHMAP0_CH1SEL_M 0x000000F0

§ UDMA_CHMAP0_CH0SEL_M

#define UDMA_CHMAP0_CH0SEL_M 0x0000000F

§ UDMA_CHMAP0_CH7SEL_S

#define UDMA_CHMAP0_CH7SEL_S 28

§ UDMA_CHMAP0_CH6SEL_S

#define UDMA_CHMAP0_CH6SEL_S 24

§ UDMA_CHMAP0_CH5SEL_S

#define UDMA_CHMAP0_CH5SEL_S 20

§ UDMA_CHMAP0_CH4SEL_S

#define UDMA_CHMAP0_CH4SEL_S 16

§ UDMA_CHMAP0_CH3SEL_S

#define UDMA_CHMAP0_CH3SEL_S 12

§ UDMA_CHMAP0_CH2SEL_S

#define UDMA_CHMAP0_CH2SEL_S 8

§ UDMA_CHMAP0_CH1SEL_S

#define UDMA_CHMAP0_CH1SEL_S 4

§ UDMA_CHMAP0_CH0SEL_S

#define UDMA_CHMAP0_CH0SEL_S 0

§ UDMA_CHMAP1_CH15SEL_M

#define UDMA_CHMAP1_CH15SEL_M 0xF0000000

§ UDMA_CHMAP1_CH14SEL_M

#define UDMA_CHMAP1_CH14SEL_M 0x0F000000

§ UDMA_CHMAP1_CH13SEL_M

#define UDMA_CHMAP1_CH13SEL_M 0x00F00000

§ UDMA_CHMAP1_CH12SEL_M

#define UDMA_CHMAP1_CH12SEL_M 0x000F0000

§ UDMA_CHMAP1_CH11SEL_M

#define UDMA_CHMAP1_CH11SEL_M 0x0000F000

§ UDMA_CHMAP1_CH10SEL_M

#define UDMA_CHMAP1_CH10SEL_M 0x00000F00

§ UDMA_CHMAP1_CH9SEL_M

#define UDMA_CHMAP1_CH9SEL_M 0x000000F0

§ UDMA_CHMAP1_CH8SEL_M

#define UDMA_CHMAP1_CH8SEL_M 0x0000000F

§ UDMA_CHMAP1_CH15SEL_S

#define UDMA_CHMAP1_CH15SEL_S 28

§ UDMA_CHMAP1_CH14SEL_S

#define UDMA_CHMAP1_CH14SEL_S 24

§ UDMA_CHMAP1_CH13SEL_S

#define UDMA_CHMAP1_CH13SEL_S 20

§ UDMA_CHMAP1_CH12SEL_S

#define UDMA_CHMAP1_CH12SEL_S 16

§ UDMA_CHMAP1_CH11SEL_S

#define UDMA_CHMAP1_CH11SEL_S 12

§ UDMA_CHMAP1_CH10SEL_S

#define UDMA_CHMAP1_CH10SEL_S 8

§ UDMA_CHMAP1_CH9SEL_S

#define UDMA_CHMAP1_CH9SEL_S 4

§ UDMA_CHMAP1_CH8SEL_S

#define UDMA_CHMAP1_CH8SEL_S 0

§ UDMA_CHMAP2_CH23SEL_M

#define UDMA_CHMAP2_CH23SEL_M 0xF0000000

§ UDMA_CHMAP2_CH22SEL_M

#define UDMA_CHMAP2_CH22SEL_M 0x0F000000

§ UDMA_CHMAP2_CH21SEL_M

#define UDMA_CHMAP2_CH21SEL_M 0x00F00000

§ UDMA_CHMAP2_CH20SEL_M

#define UDMA_CHMAP2_CH20SEL_M 0x000F0000

§ UDMA_CHMAP2_CH19SEL_M

#define UDMA_CHMAP2_CH19SEL_M 0x0000F000

§ UDMA_CHMAP2_CH18SEL_M

#define UDMA_CHMAP2_CH18SEL_M 0x00000F00

§ UDMA_CHMAP2_CH17SEL_M

#define UDMA_CHMAP2_CH17SEL_M 0x000000F0

§ UDMA_CHMAP2_CH16SEL_M

#define UDMA_CHMAP2_CH16SEL_M 0x0000000F

§ UDMA_CHMAP2_CH23SEL_S

#define UDMA_CHMAP2_CH23SEL_S 28

§ UDMA_CHMAP2_CH22SEL_S

#define UDMA_CHMAP2_CH22SEL_S 24

§ UDMA_CHMAP2_CH21SEL_S

#define UDMA_CHMAP2_CH21SEL_S 20

§ UDMA_CHMAP2_CH20SEL_S

#define UDMA_CHMAP2_CH20SEL_S 16

§ UDMA_CHMAP2_CH19SEL_S

#define UDMA_CHMAP2_CH19SEL_S 12

§ UDMA_CHMAP2_CH18SEL_S

#define UDMA_CHMAP2_CH18SEL_S 8

§ UDMA_CHMAP2_CH17SEL_S

#define UDMA_CHMAP2_CH17SEL_S 4

§ UDMA_CHMAP2_CH16SEL_S

#define UDMA_CHMAP2_CH16SEL_S 0

§ UDMA_CHMAP3_CH31SEL_M

#define UDMA_CHMAP3_CH31SEL_M 0xF0000000

§ UDMA_CHMAP3_CH30SEL_M

#define UDMA_CHMAP3_CH30SEL_M 0x0F000000

§ UDMA_CHMAP3_CH29SEL_M

#define UDMA_CHMAP3_CH29SEL_M 0x00F00000

§ UDMA_CHMAP3_CH28SEL_M

#define UDMA_CHMAP3_CH28SEL_M 0x000F0000

§ UDMA_CHMAP3_CH27SEL_M

#define UDMA_CHMAP3_CH27SEL_M 0x0000F000

§ UDMA_CHMAP3_CH26SEL_M

#define UDMA_CHMAP3_CH26SEL_M 0x00000F00

§ UDMA_CHMAP3_CH25SEL_M

#define UDMA_CHMAP3_CH25SEL_M 0x000000F0

§ UDMA_CHMAP3_CH24SEL_M

#define UDMA_CHMAP3_CH24SEL_M 0x0000000F

§ UDMA_CHMAP3_CH31SEL_S

#define UDMA_CHMAP3_CH31SEL_S 28

§ UDMA_CHMAP3_CH30SEL_S

#define UDMA_CHMAP3_CH30SEL_S 24

§ UDMA_CHMAP3_CH29SEL_S

#define UDMA_CHMAP3_CH29SEL_S 20

§ UDMA_CHMAP3_CH28SEL_S

#define UDMA_CHMAP3_CH28SEL_S 16

§ UDMA_CHMAP3_CH27SEL_S

#define UDMA_CHMAP3_CH27SEL_S 12

§ UDMA_CHMAP3_CH26SEL_S

#define UDMA_CHMAP3_CH26SEL_S 8

§ UDMA_CHMAP3_CH25SEL_S

#define UDMA_CHMAP3_CH25SEL_S 4

§ UDMA_CHMAP3_CH24SEL_S

#define UDMA_CHMAP3_CH24SEL_S 0

§ UDMA_O_SRCENDP

#define UDMA_O_SRCENDP 0x00000000

§ UDMA_O_DSTENDP

#define UDMA_O_DSTENDP 0x00000004

§ UDMA_O_CHCTL

#define UDMA_O_CHCTL 0x00000008

§ UDMA_SRCENDP_ADDR_M

#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF

§ UDMA_SRCENDP_ADDR_S

#define UDMA_SRCENDP_ADDR_S 0

§ UDMA_DSTENDP_ADDR_M

#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF

§ UDMA_DSTENDP_ADDR_S

#define UDMA_DSTENDP_ADDR_S 0

§ UDMA_CHCTL_DSTINC_M

#define UDMA_CHCTL_DSTINC_M 0xC0000000

Referenced by uDMAChannelControlSet(), and uDMAChannelTransferSet().

§ UDMA_CHCTL_DSTINC_8

#define UDMA_CHCTL_DSTINC_8 0x00000000

§ UDMA_CHCTL_DSTINC_16

#define UDMA_CHCTL_DSTINC_16 0x40000000

§ UDMA_CHCTL_DSTINC_32

#define UDMA_CHCTL_DSTINC_32 0x80000000

Referenced by uDMAChannelScatterGatherSet().

§ UDMA_CHCTL_DSTINC_NONE

#define UDMA_CHCTL_DSTINC_NONE 0xC0000000

§ UDMA_CHCTL_DSTSIZE_M

#define UDMA_CHCTL_DSTSIZE_M 0x30000000

Referenced by uDMAChannelControlSet().

§ UDMA_CHCTL_DSTSIZE_8

#define UDMA_CHCTL_DSTSIZE_8 0x00000000

§ UDMA_CHCTL_DSTSIZE_16

#define UDMA_CHCTL_DSTSIZE_16 0x10000000

§ UDMA_CHCTL_DSTSIZE_32

#define UDMA_CHCTL_DSTSIZE_32 0x20000000

Referenced by uDMAChannelScatterGatherSet().

§ UDMA_CHCTL_SRCINC_M

#define UDMA_CHCTL_SRCINC_M 0x0C000000

Referenced by uDMAChannelControlSet(), and uDMAChannelTransferSet().

§ UDMA_CHCTL_SRCINC_8

#define UDMA_CHCTL_SRCINC_8 0x00000000

§ UDMA_CHCTL_SRCINC_16

#define UDMA_CHCTL_SRCINC_16 0x04000000

§ UDMA_CHCTL_SRCINC_32

#define UDMA_CHCTL_SRCINC_32 0x08000000

Referenced by uDMAChannelScatterGatherSet().

§ UDMA_CHCTL_SRCINC_NONE

#define UDMA_CHCTL_SRCINC_NONE 0x0C000000

§ UDMA_CHCTL_SRCSIZE_M

#define UDMA_CHCTL_SRCSIZE_M 0x03000000

Referenced by uDMAChannelControlSet().

§ UDMA_CHCTL_SRCSIZE_8

#define UDMA_CHCTL_SRCSIZE_8 0x00000000

§ UDMA_CHCTL_SRCSIZE_16

#define UDMA_CHCTL_SRCSIZE_16 0x01000000

§ UDMA_CHCTL_SRCSIZE_32

#define UDMA_CHCTL_SRCSIZE_32 0x02000000

Referenced by uDMAChannelScatterGatherSet().

§ UDMA_CHCTL_DSTPROT0

#define UDMA_CHCTL_DSTPROT0 0x00200000

§ UDMA_CHCTL_SRCPROT0

#define UDMA_CHCTL_SRCPROT0 0x00040000

§ UDMA_CHCTL_ARBSIZE_M

#define UDMA_CHCTL_ARBSIZE_M 0x0003C000

Referenced by uDMAChannelControlSet().

§ UDMA_CHCTL_ARBSIZE_1

#define UDMA_CHCTL_ARBSIZE_1 0x00000000

§ UDMA_CHCTL_ARBSIZE_2

#define UDMA_CHCTL_ARBSIZE_2 0x00004000

§ UDMA_CHCTL_ARBSIZE_4

#define UDMA_CHCTL_ARBSIZE_4 0x00008000

Referenced by uDMAChannelScatterGatherSet().

§ UDMA_CHCTL_ARBSIZE_8

#define UDMA_CHCTL_ARBSIZE_8 0x0000C000

§ UDMA_CHCTL_ARBSIZE_16

#define UDMA_CHCTL_ARBSIZE_16 0x00010000

§ UDMA_CHCTL_ARBSIZE_32

#define UDMA_CHCTL_ARBSIZE_32 0x00014000

§ UDMA_CHCTL_ARBSIZE_64

#define UDMA_CHCTL_ARBSIZE_64 0x00018000

§ UDMA_CHCTL_ARBSIZE_128

#define UDMA_CHCTL_ARBSIZE_128 0x0001C000

§ UDMA_CHCTL_ARBSIZE_256

#define UDMA_CHCTL_ARBSIZE_256 0x00020000

§ UDMA_CHCTL_ARBSIZE_512

#define UDMA_CHCTL_ARBSIZE_512 0x00024000

§ UDMA_CHCTL_ARBSIZE_1024

#define UDMA_CHCTL_ARBSIZE_1024 0x00028000

§ UDMA_CHCTL_XFERSIZE_M

#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0

Referenced by uDMAChannelSizeGet(), and uDMAChannelTransferSet().

§ UDMA_CHCTL_NXTUSEBURST

#define UDMA_CHCTL_NXTUSEBURST 0x00000008

Referenced by uDMAChannelControlSet().

§ UDMA_CHCTL_XFERMODE_M

#define UDMA_CHCTL_XFERMODE_M 0x00000007

Referenced by uDMAChannelModeGet(), uDMAChannelSizeGet(), and uDMAChannelTransferSet().

§ UDMA_CHCTL_XFERMODE_STOP

#define UDMA_CHCTL_XFERMODE_STOP 0x00000000

§ UDMA_CHCTL_XFERMODE_BASIC

#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001

§ UDMA_CHCTL_XFERMODE_AUTO

#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002

§ UDMA_CHCTL_XFERMODE_PINGPONG

#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003

§ UDMA_CHCTL_XFERMODE_MEM_SG

#define UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004

Referenced by uDMAChannelScatterGatherSet().

§ UDMA_CHCTL_XFERMODE_MEM_SGA

#define UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005

§ UDMA_CHCTL_XFERMODE_PER_SG

#define UDMA_CHCTL_XFERMODE_PER_SG 0x00000006

Referenced by uDMAChannelScatterGatherSet().

§ UDMA_CHCTL_XFERMODE_PER_SGA

#define UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007

§ UDMA_CHCTL_XFERSIZE_S

#define UDMA_CHCTL_XFERSIZE_S 4

Referenced by uDMAChannelScatterGatherSet().

Macros

Macro Definition Documentation

§ UDMA_STAT

§ UDMA_CFG

§ UDMA_CTLBASE

§ UDMA_ALTBASE

§ UDMA_WAITSTAT

§ UDMA_SWREQ

§ UDMA_USEBURSTSET

§ UDMA_USEBURSTCLR

§ UDMA_REQMASKSET

§ UDMA_REQMASKCLR

§ UDMA_ENASET

§ UDMA_ENACLR

§ UDMA_ALTSET

§ UDMA_ALTCLR

§ UDMA_PRIOSET

§ UDMA_PRIOCLR

§ UDMA_ERRCLR

§ UDMA_CHASGN

§ UDMA_CHMAP0

§ UDMA_CHMAP1

§ UDMA_CHMAP2

§ UDMA_CHMAP3

§ UDMA_STAT_DMACHANS_M

§ UDMA_STAT_STATE_M

§ UDMA_STAT_STATE_IDLE

§ UDMA_STAT_STATE_RD_CTRL

§ UDMA_STAT_STATE_RD_SRCENDP

§ UDMA_STAT_STATE_RD_DSTENDP

§ UDMA_STAT_STATE_RD_SRCDAT

§ UDMA_STAT_STATE_WR_DSTDAT

§ UDMA_STAT_STATE_WAIT

§ UDMA_STAT_STATE_WR_CTRL

§ UDMA_STAT_STATE_STALL

§ UDMA_STAT_STATE_DONE

§ UDMA_STAT_STATE_UNDEF

§ UDMA_STAT_MASTEN

§ UDMA_STAT_DMACHANS_S

§ UDMA_CFG_MASTEN

§ UDMA_CTLBASE_ADDR_M

§ UDMA_CTLBASE_ADDR_S

§ UDMA_ALTBASE_ADDR_M

§ UDMA_ALTBASE_ADDR_S

§ UDMA_WAITSTAT_WAITREQ_M

§ UDMA_SWREQ_M

§ UDMA_USEBURSTSET_SET_M

§ UDMA_USEBURSTCLR_CLR_M

§ UDMA_REQMASKSET_SET_M

§ UDMA_REQMASKCLR_CLR_M

§ UDMA_ENASET_SET_M

§ UDMA_ENACLR_CLR_M

§ UDMA_ALTSET_SET_M

§ UDMA_ALTCLR_CLR_M

§ UDMA_PRIOSET_SET_M

§ UDMA_PRIOCLR_CLR_M

§ UDMA_ERRCLR_ERRCLR

§ UDMA_CHASGN_M

§ UDMA_CHASGN_PRIMARY

§ UDMA_CHASGN_SECONDARY

§ UDMA_CHIS_M

§ UDMA_CHMAP0_CH7SEL_M

§ UDMA_CHMAP0_CH6SEL_M

§ UDMA_CHMAP0_CH5SEL_M

§ UDMA_CHMAP0_CH4SEL_M

§ UDMA_CHMAP0_CH3SEL_M

§ UDMA_CHMAP0_CH2SEL_M

§ UDMA_CHMAP0_CH1SEL_M

§ UDMA_CHMAP0_CH0SEL_M

§ UDMA_CHMAP0_CH7SEL_S

§ UDMA_CHMAP0_CH6SEL_S

§ UDMA_CHMAP0_CH5SEL_S

§ UDMA_CHMAP0_CH4SEL_S

§ UDMA_CHMAP0_CH3SEL_S

§ UDMA_CHMAP0_CH2SEL_S

§ UDMA_CHMAP0_CH1SEL_S

§ UDMA_CHMAP0_CH0SEL_S

§ UDMA_CHMAP1_CH15SEL_M

§ UDMA_CHMAP1_CH14SEL_M

§ UDMA_CHMAP1_CH13SEL_M