dl_uart.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/*!****************************************************************************
 *  @file       dl_uart.h
 *  @brief      UART Driver Library
 *  @defgroup   UART Universal Asynchronous Receiver-Transmitter (UART)
 *
 *  @anchor ti_dl_dl_uart_Overview
 *  # Overview
 *
 *  The Universal Asynchronous Receiver-Transmitter Driver Library allows
 *  full configuration of the MSPM0 UART module.
 *  This module provides common functionality for UART-Main and UART-Extend, but
 *  developers should use the corresponding dl_uart_extend or dl_uart_main APIs
 *  directly.
 *
 *  <hr>
 ******************************************************************************
 */
#ifndef ti_dl_dl_uart__include
#define ti_dl_dl_uart__include

#if defined(ti_dl_dl_uart_main__include) || \
    defined(ti_dl_dl_uart_extend__include) || defined(DOXYGEN__INCLUDE)

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#if defined(__MSPM0_HAS_UART_MAIN__) || defined(__MSPM0_HAS_UART_EXTD__)

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

#define DL_UART_INTERRUPT_DMA_DONE_TX   (UART_CPU_INT_IMASK_DMA_DONE_TX_SET)

#define DL_UART_INTERRUPT_DMA_DONE_RX   (UART_CPU_INT_IMASK_DMA_DONE_RX_SET)

#define DL_UART_INTERRUPT_CTS_DONE              (UART_CPU_INT_IMASK_CTS_SET)

#define DL_UART_INTERRUPT_ADDRESS_MATCH  (UART_CPU_INT_IMASK_ADDR_MATCH_SET)

#define DL_UART_INTERRUPT_LINC0_MATCH         (UART_CPU_INT_IMASK_LINC0_SET)

#define DL_UART_INTERRUPT_EOT_DONE              (UART_CPU_INT_IMASK_EOT_SET)

#define DL_UART_INTERRUPT_TX                  (UART_CPU_INT_IMASK_TXINT_SET)

#define DL_UART_INTERRUPT_RX                  (UART_CPU_INT_IMASK_RXINT_SET)

#define DL_UART_INTERRUPT_LIN_COUNTER_OVERFLOW                                \
                                             (UART_CPU_INT_IMASK_LINOVF_SET)

#define DL_UART_INTERRUPT_LIN_RISING_EDGE                                     \
                                              (UART_CPU_INT_IMASK_LINC1_SET)

#define DL_UART_INTERRUPT_LIN_FALLING_EDGE                                    \
                                              (UART_CPU_INT_IMASK_LINC0_SET)

#define DL_UART_INTERRUPT_RXD_POS_EDGE         (UART_CPU_INT_IMASK_RXPE_SET)

#define DL_UART_INTERRUPT_RXD_NEG_EDGE         (UART_CPU_INT_IMASK_RXNE_SET)

#define DL_UART_INTERRUPT_OVERRUN_ERROR      (UART_CPU_INT_IMASK_OVRERR_SET)

#define DL_UART_INTERRUPT_BREAK_ERROR        (UART_CPU_INT_IMASK_BRKERR_SET)

#define DL_UART_INTERRUPT_PARITY_ERROR       (UART_CPU_INT_IMASK_PARERR_SET)

#define DL_UART_INTERRUPT_FRAMING_ERROR      (UART_CPU_INT_IMASK_FRMERR_SET)

#define DL_UART_INTERRUPT_RX_TIMEOUT_ERROR    (UART_CPU_INT_IMASK_RTOUT_SET)


#define DL_UART_INTERRUPT_NOISE_ERROR          (UART_CPU_INT_IMASK_NERR_SET)


typedef enum {
    DL_UART_IIDX_DMA_DONE_TX = UART_CPU_INT_IIDX_STAT_DMA_DONE_TX,
    DL_UART_IIDX_DMA_DONE_RX = UART_CPU_INT_IIDX_STAT_DMA_DONE_RX,
    DL_UART_IIDX_CTS_DONE = UART_CPU_INT_IIDX_STAT_CTS,
    DL_UART_IIDX_ADDRESS_MATCH = UART_CPU_INT_IIDX_STAT_MODE_9B,
    DL_UART_IIDX_EOT_DONE = UART_CPU_INT_IIDX_STAT_EOT,
    DL_UART_IIDX_TX = UART_CPU_INT_IIDX_STAT_TXIFG,
    DL_UART_IIDX_RX = UART_CPU_INT_IIDX_STAT_RXIFG,
    DL_UART_IIDX_LIN_COUNTER_OVERFLOW = UART_CPU_INT_IIDX_STAT_LINOVF,
    DL_UART_IIDX_LIN_RISING_EDGE = UART_CPU_INT_IIDX_STAT_LINC1,
    DL_UART_IIDX_LIN_FALLING_EDGE = UART_CPU_INT_IIDX_STAT_LINC0,
    DL_UART_IIDX_RXD_POS_EDGE = UART_CPU_INT_IIDX_STAT_RXPE,
    DL_UART_IIDX_RXD_NEG_EDGE = UART_CPU_INT_IIDX_STAT_RXNE,
    DL_UART_IIDX_OVERRUN_ERROR = UART_CPU_INT_IIDX_STAT_OEFG,
    DL_UART_IIDX_BREAK_ERROR = UART_CPU_INT_IIDX_STAT_BEFG,
    DL_UART_IIDX_PARITY_ERROR = UART_CPU_INT_IIDX_STAT_PEFG,
    DL_UART_IIDX_FRAMING_ERROR = UART_CPU_INT_IIDX_STAT_FEFG,
    DL_UART_IIDX_RX_TIMEOUT_ERROR = UART_CPU_INT_IIDX_STAT_RTFG,


    DL_UART_IIDX_NOISE_ERROR = UART_CPU_INT_IIDX_STAT_NERR_EVT,


    DL_UART_IIDX_NO_INTERRUPT = UART_CPU_INT_IIDX_STAT_NO_INTR
} DL_UART_IIDX;

typedef enum {
    DL_UART_DMA_IIDX_RX_TRIGGER = UART_DMA_TRIG_RX_IIDX_STAT_RXIFG,
    DL_UART_DMA_IIDX_RX_TIMEOUT_TRIGGER = UART_DMA_TRIG_RX_IIDX_STAT_RTFG
} DL_UART_DMA_IIDX_RX;

typedef enum {
    DL_UART_DMA_IIDX_TX_TRIGGER = UART_DMA_TRIG_TX_IIDX_STAT_TXIFG
} DL_UART_DMA_IIDX_TX;

#define DL_UART_DMA_INTERRUPT_RX              (UART_DMA_TRIG_RX_IMASK_RXINT_SET)

#define DL_UART_DMA_INTERRUPT_RX_TIMEOUT      (UART_DMA_TRIG_RX_IMASK_RTOUT_SET)

#define DL_UART_DMA_INTERRUPT_TX              (UART_DMA_TRIG_TX_IMASK_TXINT_SET)

#define DL_UART_ERROR_OVERRUN                          (UART_RXDATA_OVRERR_SET)

#define DL_UART_ERROR_BREAK                            (UART_RXDATA_BRKERR_SET)

#define DL_UART_ERROR_PARITY                           (UART_RXDATA_BRKERR_SET)

#define DL_UART_ERROR_FRAMING                          (UART_RXDATA_FRMERR_SET)

typedef enum {
    DL_UART_PULSE_WIDTH_5_NS = UART_GFCTL_AGFSEL_AGLIT_5,
    DL_UART_PULSE_WIDTH_10_NS = UART_GFCTL_AGFSEL_AGLIT_10,
    DL_UART_PULSE_WIDTH_25_NS = UART_GFCTL_AGFSEL_AGLIT_25,
    DL_UART_PULSE_WIDTH_50_NS = UART_GFCTL_AGFSEL_AGLIT_50
} DL_UART_PULSE_WIDTH;

typedef enum {
    DL_UART_OVERSAMPLING_RATE_16X = UART_CTL0_HSE_OVS16,
    DL_UART_OVERSAMPLING_RATE_8X = UART_CTL0_HSE_OVS8,
    DL_UART_OVERSAMPLING_RATE_3X = UART_CTL0_HSE_OVS3
} DL_UART_OVERSAMPLING_RATE;

typedef enum {
    DL_UART_PARITY_EVEN = (UART_LCRH_PEN_ENABLE | UART_LCRH_EPS_EVEN),
    DL_UART_PARITY_ODD = (UART_LCRH_PEN_ENABLE | UART_LCRH_EPS_ODD),
    DL_UART_PARITY_STICK_ONE = (UART_LCRH_PEN_ENABLE | UART_LCRH_SPS_ENABLE | UART_LCRH_EPS_ODD),
    DL_UART_PARITY_STICK_ZERO = (UART_LCRH_PEN_ENABLE | UART_LCRH_SPS_ENABLE | UART_LCRH_EPS_EVEN),
    DL_UART_PARITY_NONE = UART_LCRH_PEN_DISABLE
} DL_UART_PARITY;

typedef enum {
    DL_UART_WORD_LENGTH_5_BITS = UART_LCRH_WLEN_DATABIT5,
    DL_UART_WORD_LENGTH_6_BITS = UART_LCRH_WLEN_DATABIT6,
    DL_UART_WORD_LENGTH_7_BITS = UART_LCRH_WLEN_DATABIT7,
    DL_UART_WORD_LENGTH_8_BITS = UART_LCRH_WLEN_DATABIT8
} DL_UART_WORD_LENGTH;

typedef enum {
    DL_UART_MODE_NORMAL = UART_CTL0_MODE_UART,
    DL_UART_MODE_RS485 = UART_CTL0_MODE_RS485,
    DL_UART_MODE_IDLE_LINE = UART_CTL0_MODE_IDLELINE,
    DL_UART_MODE_ADDR_9_BIT = UART_CTL0_MODE_ADDR9BIT,
    DL_UART_MODE_SMART_CARD = UART_CTL0_MODE_SMART,
    DL_UART_MODE_DALI = UART_CTL0_MODE_DALI
} DL_UART_MODE;

typedef enum {
    DL_UART_DIRECTION_TX = UART_CTL0_TXE_ENABLE,
    DL_UART_DIRECTION_RX = UART_CTL0_RXE_ENABLE,
    DL_UART_DIRECTION_TX_RX = (UART_CTL0_RXE_ENABLE | UART_CTL0_TXE_ENABLE),
    DL_UART_DIRECTION_NONE = (UART_CTL0_RXE_DISABLE | UART_CTL0_TXE_DISABLE)
} DL_UART_DIRECTION;

typedef enum {
    DL_UART_CLOCK_BUSCLK = UART_CLKSEL_BUSCLK_SEL_ENABLE,
    DL_UART_CLOCK_MFCLK = UART_CLKSEL_MFCLK_SEL_ENABLE,
    DL_UART_CLOCK_LFCLK = UART_CLKSEL_LFCLK_SEL_ENABLE
} DL_UART_CLOCK;

typedef enum {
    DL_UART_FLOW_CONTROL_RTS = UART_CTL0_RTSEN_ENABLE,
    DL_UART_FLOW_CONTROL_CTS = UART_CTL0_CTSEN_ENABLE,
    DL_UART_FLOW_CONTROL_RTS_CTS = (UART_CTL0_RTSEN_ENABLE | UART_CTL0_CTSEN_ENABLE),
    DL_UART_FLOW_CONTROL_NONE = (UART_CTL0_CTSEN_DISABLE | UART_CTL0_RTSEN_DISABLE)
} DL_UART_FLOW_CONTROL;

typedef enum {
    DL_UART_RTS_ASSERT = UART_CTL0_RTS_SET,
    DL_UART_RTS_DEASSERT = UART_CTL0_RTS_CLR
} DL_UART_RTS;

typedef enum {
    DL_UART_STOP_BITS_ONE = UART_LCRH_STP2_DISABLE,
    DL_UART_STOP_BITS_TWO = UART_LCRH_STP2_ENABLE
} DL_UART_STOP_BITS;

typedef enum {
    DL_UART_TXD_OUT_LOW = UART_CTL0_TXD_OUT_LOW,
    DL_UART_TXD_OUT_HIGH = UART_CTL0_TXD_OUT_HIGH
} DL_UART_TXD_OUT;

typedef enum {
    DL_UART_TX_FIFO_LEVEL_3_4_EMPTY = UART_IFLS_TXIFLSEL_LVL_3_4,
    DL_UART_TX_FIFO_LEVEL_1_2_EMPTY = UART_IFLS_TXIFLSEL_LVL_1_2,
    DL_UART_TX_FIFO_LEVEL_1_4_EMPTY = UART_IFLS_TXIFLSEL_LVL_1_4,
    DL_UART_TX_FIFO_LEVEL_EMPTY = UART_IFLS_TXIFLSEL_LVL_EMPTY,
    DL_UART_TX_FIFO_LEVEL_ONE_ENTRY = UART_IFLS_TXIFLSEL_LVL_1
} DL_UART_TX_FIFO_LEVEL;

typedef enum {
    DL_UART_RX_FIFO_LEVEL_ONE_ENTRY = UART_IFLS_RXIFLSEL_LVL_1,
    DL_UART_RX_FIFO_LEVEL_FULL = UART_IFLS_RXIFLSEL_LVL_FULL,
    DL_UART_RX_FIFO_LEVEL_3_4_FULL = UART_IFLS_RXIFLSEL_LVL_3_4,
    DL_UART_RX_FIFO_LEVEL_1_2_FULL = UART_IFLS_RXIFLSEL_LVL_1_2,
    DL_UART_RX_FIFO_LEVEL_1_4_FULL = UART_IFLS_RXIFLSEL_LVL_1_4,
} DL_UART_RX_FIFO_LEVEL;

typedef enum {
    DL_UART_IRDA_CLOCK_BAUD_RATE = UART_IRCTL_IRTXCLK_BRCLK,
    DL_UART_IRDA_CLOCK_FUNCTIONAL = UART_IRCTL_IRTXCLK_BITCLK
} DL_UART_IRDA_CLOCK;

typedef enum {
    DL_UART_IRDA_POLARITY_LOW = UART_IRCTL_IRRXPL_LOW,
    DL_UART_IRDA_POLARITY_HIGH = UART_IRCTL_IRRXPL_HIGH
} DL_UART_IRDA_POLARITY;

#define DL_UART_PULSE_WIDTH_3_16_BIT_PERIOD           ((uint32_t) 0x00000000U)

typedef enum {
    DL_UART_CLOCK_DIVIDE_RATIO_1 = UART_CLKDIV_RATIO_DIV_BY_1,
    DL_UART_CLOCK_DIVIDE_RATIO_2 = UART_CLKDIV_RATIO_DIV_BY_2,
    DL_UART_CLOCK_DIVIDE_RATIO_3 = UART_CLKDIV_RATIO_DIV_BY_3,
    DL_UART_CLOCK_DIVIDE_RATIO_4 = UART_CLKDIV_RATIO_DIV_BY_4,
    DL_UART_CLOCK_DIVIDE_RATIO_5 = UART_CLKDIV_RATIO_DIV_BY_5,
    DL_UART_CLOCK_DIVIDE_RATIO_6 = UART_CLKDIV_RATIO_DIV_BY_6,
    DL_UART_CLOCK_DIVIDE_RATIO_7 = UART_CLKDIV_RATIO_DIV_BY_7,
    DL_UART_CLOCK_DIVIDE_RATIO_8 = UART_CLKDIV_RATIO_DIV_BY_8
} DL_UART_CLOCK_DIVIDE_RATIO;

typedef enum {
    DL_UART_CLOCK_DIVIDE2_RATIO_1 = UART_CLKDIV2_RATIO_DIV_BY_1,
    DL_UART_CLOCK_DIVIDE2_RATIO_2 = UART_CLKDIV2_RATIO_DIV_BY_2,
    DL_UART_CLOCK_DIVIDE2_RATIO_3 = UART_CLKDIV2_RATIO_DIV_BY_3,
    DL_UART_CLOCK_DIVIDE2_RATIO_4 = UART_CLKDIV2_RATIO_DIV_BY_4,
    DL_UART_CLOCK_DIVIDE2_RATIO_5 = UART_CLKDIV2_RATIO_DIV_BY_5,
    DL_UART_CLOCK_DIVIDE2_RATIO_6 = UART_CLKDIV2_RATIO_DIV_BY_6,
    DL_UART_CLOCK_DIVIDE2_RATIO_7 = UART_CLKDIV2_RATIO_DIV_BY_7,
    DL_UART_CLOCK_DIVIDE2_RATIO_8 = UART_CLKDIV2_RATIO_DIV_BY_8
} DL_UART_CLOCK_DIVIDE2_RATIO;

/* clang-format on */

typedef struct {
    DL_UART_MODE mode;

    DL_UART_DIRECTION direction;

    DL_UART_FLOW_CONTROL flowControl;

    DL_UART_PARITY parity;

    DL_UART_WORD_LENGTH wordLength;

    DL_UART_STOP_BITS stopBits;

} DL_UART_Config;

typedef struct {
    DL_UART_CLOCK clockSel;

    DL_UART_CLOCK_DIVIDE_RATIO divideRatio;

} DL_UART_ClockConfig;

#ifdef __MSPM0_HAS_UART_MAIN__

typedef struct {
    uint32_t controlWord;

    uint32_t clockSel;

    uint32_t divideRatio;

    uint32_t interruptFifoLevelSelectWord;

    uint32_t ibrd;

    uint32_t fbrd;

    uint32_t lineControlRegisterWord;

    uint32_t glitchFilterControlWord;

    uint32_t interruptMask0;

    uint32_t interruptMask1;

    uint32_t interruptMask2;

    bool backupRdy;
} DL_UART_Main_backupConfig;

#endif /* __MSPM0_HAS_UART_MAIN__ */

#ifdef __MSPM0_HAS_UART_EXTD__

typedef struct {
    uint32_t controlWord;

    uint32_t clockSel;

    uint32_t divideRatio;

    uint32_t lineControlRegisterWord;

    uint32_t interruptFifoLevelSelectWord;

    uint32_t ibrd;

    uint32_t fbrd;

    uint32_t glitchFilterControlWord;

    uint32_t linControlWord;

    uint32_t irdaControlWord;

    uint32_t addressMask;

    uint32_t address;

    uint32_t interruptMask0;

    uint32_t interruptMask1;

    uint32_t interruptMask2;

    bool backupRdy;
} DL_UART_Extend_backupConfig;

#endif /* __MSPM0_HAS_UART_EXTD__ */

void DL_UART_init(UART_Regs *uart, DL_UART_Config *config);

__STATIC_INLINE void DL_UART_enablePower(UART_Regs *uart)
{
    uart->GPRCM.PWREN = (UART_PWREN_KEY_UNLOCK_W | UART_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_UART_disablePower(UART_Regs *uart)
{
    uart->GPRCM.PWREN = (UART_PWREN_KEY_UNLOCK_W | UART_PWREN_ENABLE_DISABLE);
}

__STATIC_INLINE bool DL_UART_isPowerEnabled(UART_Regs *uart)
{
    return ((uart->GPRCM.PWREN & UART_PWREN_ENABLE_MASK) ==
            UART_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_UART_reset(UART_Regs *uart)
{
    uart->GPRCM.RSTCTL =
        (UART_RSTCTL_KEY_UNLOCK_W | UART_RSTCTL_RESETSTKYCLR_CLR |
            UART_RSTCTL_RESETASSERT_ASSERT);
}

__STATIC_INLINE bool DL_UART_isReset(UART_Regs *uart)
{
    return ((uart->GPRCM.STAT & UART_GPRCM_STAT_RESETSTKY_MASK) ==
            UART_GPRCM_STAT_RESETSTKY_RESET);
}

__STATIC_INLINE void DL_UART_enable(UART_Regs *uart)
{
    uart->CTL0 |= UART_CTL0_ENABLE_ENABLE;
}

__STATIC_INLINE bool DL_UART_isEnabled(UART_Regs *uart)
{
    return ((uart->CTL0 & UART_CTL0_ENABLE_MASK) == UART_CTL0_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_UART_disable(UART_Regs *uart)
{
    uart->CTL0 &= ~(UART_CTL0_ENABLE_MASK);
}

void DL_UART_setClockConfig(UART_Regs *uart, DL_UART_ClockConfig *config);

void DL_UART_getClockConfig(UART_Regs *uart, DL_UART_ClockConfig *config);

void DL_UART_configBaudRate(
    UART_Regs *uart, uint32_t clockFreq, uint32_t baudRate);

__STATIC_INLINE void DL_UART_setOversampling(
    UART_Regs *uart, DL_UART_OVERSAMPLING_RATE rate)
{
    DL_Common_updateReg(&uart->CTL0, (uint32_t) rate, UART_CTL0_HSE_MASK);
}

__STATIC_INLINE DL_UART_OVERSAMPLING_RATE DL_UART_getOversampling(
    UART_Regs *uart)
{
    uint32_t rate = uart->CTL0 & UART_CTL0_HSE_MASK;

    return (DL_UART_OVERSAMPLING_RATE)(rate);
}

__STATIC_INLINE void DL_UART_enableLoopbackMode(UART_Regs *uart)
{
    uart->CTL0 |= UART_CTL0_LBE_ENABLE;
}

__STATIC_INLINE bool DL_UART_isLoopbackModeEnabled(UART_Regs *uart)
{
    return ((uart->CTL0 & UART_CTL0_LBE_MASK) == UART_CTL0_LBE_ENABLE);
}

__STATIC_INLINE void DL_UART_disableLoopbackMode(UART_Regs *uart)
{
    uart->CTL0 &= ~(UART_CTL0_LBE_MASK);
}

__STATIC_INLINE void DL_UART_setDirection(
    UART_Regs *uart, DL_UART_DIRECTION direction)
{
    DL_Common_updateReg(&uart->CTL0, (uint32_t) direction,
        UART_CTL0_TXE_MASK | UART_CTL0_RXE_MASK);
}

__STATIC_INLINE DL_UART_DIRECTION DL_UART_getDirection(UART_Regs *uart)
{
    uint32_t direction =
        uart->CTL0 & (UART_CTL0_TXE_MASK | UART_CTL0_RXE_MASK);

    return (DL_UART_DIRECTION)(direction);
}

__STATIC_INLINE void DL_UART_enableMajorityVoting(UART_Regs *uart)
{
    uart->CTL0 |= UART_CTL0_MAJVOTE_ENABLE;
}

__STATIC_INLINE bool DL_UART_isMajorityVotingEnabled(UART_Regs *uart)
{
    return ((uart->CTL0 & UART_CTL0_MAJVOTE_MASK) == UART_CTL0_MAJVOTE_ENABLE);
}

__STATIC_INLINE void DL_UART_disableMajorityVoting(UART_Regs *uart)
{
    uart->CTL0 &= ~(UART_CTL0_MAJVOTE_MASK);
}

__STATIC_INLINE void DL_UART_enableMSBFirst(UART_Regs *uart)
{
    uart->CTL0 |= UART_CTL0_MSBFIRST_ENABLE;
}

__STATIC_INLINE bool DL_UART_isMSBFirstEnabled(UART_Regs *uart)
{
    return (
        (uart->CTL0 & UART_CTL0_MSBFIRST_MASK) == UART_CTL0_MSBFIRST_ENABLE);
}

__STATIC_INLINE void DL_UART_disableMSBFirst(UART_Regs *uart)
{
    uart->CTL0 &= ~(UART_CTL0_MSBFIRST_MASK);
}

__STATIC_INLINE void DL_UART_enableTransmitPinManualControl(UART_Regs *uart)
{
    uart->CTL0 |= UART_CTL0_TXD_OUT_EN_ENABLE;
}

__STATIC_INLINE bool DL_UART_isTransmitPinManualControlEnabled(UART_Regs *uart)
{
    return ((uart->CTL0 & UART_CTL0_TXD_OUT_EN_MASK) ==
            UART_CTL0_TXD_OUT_EN_ENABLE);
}

__STATIC_INLINE void DL_UART_disableTransmitPinManualControl(UART_Regs *uart)
{
    uart->CTL0 &= ~(UART_CTL0_TXD_OUT_EN_MASK);
}

__STATIC_INLINE void DL_UART_setTransmitPinManualOutput(
    UART_Regs *uart, DL_UART_TXD_OUT txdOutVal)
{
    DL_Common_updateReg(&uart->CTL0,
        UART_CTL0_TXD_OUT_EN_ENABLE | (uint32_t) txdOutVal,
        UART_CTL0_TXD_OUT_EN_MASK | UART_CTL0_TXD_OUT_MASK);
}

__STATIC_INLINE DL_UART_TXD_OUT DL_UART_getTransmitPinManualOutput(
    UART_Regs *uart)
{
    uint32_t txdOutVal = uart->CTL0 & UART_CTL0_TXD_OUT_MASK;

    return (DL_UART_TXD_OUT)(txdOutVal);
}

__STATIC_INLINE void DL_UART_enableManchesterEncoding(UART_Regs *uart)
{
    uart->CTL0 |= UART_CTL0_MENC_ENABLE;
}

__STATIC_INLINE void DL_UART_disableManchesterEncoding(UART_Regs *uart)
{
    uart->CTL0 &= ~(UART_CTL0_MENC_MASK);
}

__STATIC_INLINE bool DL_UART_isManchesterEncodingEnabled(UART_Regs *uart)
{
    return ((uart->CTL0 & UART_CTL0_MENC_MASK) == UART_CTL0_MENC_ENABLE);
}

__STATIC_INLINE void DL_UART_setCommunicationMode(
    UART_Regs *uart, DL_UART_MODE mode)
{
    DL_Common_updateReg(&uart->CTL0, (uint32_t) mode, UART_CTL0_MODE_MASK);
}

__STATIC_INLINE DL_UART_MODE DL_UART_getCommunicationMode(UART_Regs *uart)
{
    uint32_t mode = uart->CTL0 & UART_CTL0_MODE_MASK;

    return (DL_UART_MODE)(mode);
}

__STATIC_INLINE void DL_UART_setFlowControl(
    UART_Regs *uart, DL_UART_FLOW_CONTROL config)
{
    DL_Common_updateReg(&uart->CTL0, (uint32_t) config,
        UART_CTL0_RTSEN_MASK | UART_CTL0_CTSEN_MASK);
}

__STATIC_INLINE DL_UART_FLOW_CONTROL DL_UART_getFlowControl(UART_Regs *uart)
{
    uint32_t config =
        uart->CTL0 & (UART_CTL0_RTSEN_MASK | UART_CTL0_CTSEN_MASK);

    return (DL_UART_FLOW_CONTROL)(config);
}

__STATIC_INLINE void DL_UART_setRTSOutput(UART_Regs *uart, DL_UART_RTS val)
{
    DL_Common_updateReg(&uart->CTL0, (uint32_t) val, UART_CTL0_RTS_MASK);
}

__STATIC_INLINE DL_UART_RTS DL_UART_getRTSOutput(UART_Regs *uart)
{
    uint32_t val = uart->CTL0 & UART_CTL0_RTS_MASK;

    return (DL_UART_RTS)(val);
}

__STATIC_INLINE void DL_UART_enableFIFOs(UART_Regs *uart)
{
    uart->CTL0 |= UART_CTL0_FEN_ENABLE;
}

__STATIC_INLINE void DL_UART_disableFIFOs(UART_Regs *uart)
{
    uart->CTL0 &= ~(UART_CTL0_FEN_MASK);
}

__STATIC_INLINE bool DL_UART_isFIFOsEnabled(UART_Regs *uart)
{
    return ((uart->CTL0 & UART_CTL0_FEN_MASK) == UART_CTL0_FEN_ENABLE);
}

__STATIC_INLINE void DL_UART_enableLINSendBreak(UART_Regs *uart)
{
    uart->LCRH |= UART_LCRH_BRK_ENABLE;
}

__STATIC_INLINE void DL_UART_disableLINSendBreak(UART_Regs *uart)
{
    uart->LCRH &= ~(UART_LCRH_BRK_MASK);
}

__STATIC_INLINE bool DL_UART_isLINSendBreakEnabled(UART_Regs *uart)
{
    return ((uart->LCRH & UART_LCRH_BRK_MASK) == UART_LCRH_BRK_ENABLE);
}

__STATIC_INLINE bool DL_UART_isParityEnabled(UART_Regs *uart)
{
    return ((uart->LCRH & UART_LCRH_PEN_MASK) == UART_LCRH_PEN_ENABLE);
}

__STATIC_INLINE void DL_UART_setParityMode(
    UART_Regs *uart, DL_UART_PARITY parity)
{
    DL_Common_updateReg(&uart->LCRH, (uint32_t) parity,
        (UART_LCRH_PEN_MASK | UART_LCRH_EPS_MASK | UART_LCRH_SPS_MASK));
}

__STATIC_INLINE DL_UART_PARITY DL_UART_getParityMode(UART_Regs *uart)
{
    uint32_t parity = uart->LCRH & (UART_LCRH_PEN_MASK | UART_LCRH_EPS_MASK |
                                       UART_LCRH_SPS_MASK);

    return (DL_UART_PARITY)(parity);
}

__STATIC_INLINE void DL_UART_setStopBits(
    UART_Regs *uart, DL_UART_STOP_BITS numStopBits)
{
    DL_Common_updateReg(
        &uart->LCRH, (uint32_t) numStopBits, UART_LCRH_STP2_MASK);
}

__STATIC_INLINE DL_UART_STOP_BITS DL_UART_getStopBits(UART_Regs *uart)
{
    uint32_t numStopBits = uart->LCRH & UART_LCRH_STP2_MASK;

    return (DL_UART_STOP_BITS)(numStopBits);
}

__STATIC_INLINE void DL_UART_setWordLength(
    UART_Regs *uart, DL_UART_WORD_LENGTH wordLength)
{
    DL_Common_updateReg(
        &uart->LCRH, (uint32_t) wordLength, UART_LCRH_WLEN_MASK);
}

__STATIC_INLINE DL_UART_WORD_LENGTH DL_UART_getWordLength(UART_Regs *uart)
{
    uint32_t wordLength = uart->LCRH & UART_LCRH_WLEN_MASK;

    return (DL_UART_WORD_LENGTH)(wordLength);
}

__STATIC_INLINE void DL_UART_enableSendIdlePattern(UART_Regs *uart)
{
    uart->LCRH |= UART_LCRH_SENDIDLE_ENABLE;
}

__STATIC_INLINE void DL_UART_disableSendIdlePattern(UART_Regs *uart)
{
    uart->LCRH &= ~(UART_LCRH_SENDIDLE_MASK);
}

__STATIC_INLINE bool DL_UART_isSendIdlePatternEnabled(UART_Regs *uart)
{
    return (
        (uart->LCRH & UART_LCRH_SENDIDLE_MASK) == UART_LCRH_SENDIDLE_ENABLE);
}

__STATIC_INLINE void DL_UART_setExternalDriverSetup(
    UART_Regs *uart, uint32_t val)
{
    DL_Common_updateReg(&uart->LCRH, val << UART_LCRH_EXTDIR_SETUP_OFS,
        UART_LCRH_EXTDIR_SETUP_MASK);
}

__STATIC_INLINE uint32_t DL_UART_getExternalDriverSetup(UART_Regs *uart)
{
    return ((uart->LCRH &
             UART_LCRH_EXTDIR_SETUP_MASK >> UART_LCRH_EXTDIR_SETUP_OFS));
}

__STATIC_INLINE void DL_UART_setExternalDriverHold(
    UART_Regs *uart, uint32_t val)
{
    DL_Common_updateReg(&uart->LCRH, val << UART_LCRH_EXTDIR_HOLD_OFS,
        UART_LCRH_EXTDIR_HOLD_MASK);
}

__STATIC_INLINE uint32_t DL_UART_getExternalDriverHold(UART_Regs *uart)
{
    return ((
        uart->LCRH & UART_LCRH_EXTDIR_HOLD_MASK >> UART_LCRH_EXTDIR_HOLD_OFS));
}

__STATIC_INLINE bool DL_UART_isBusy(UART_Regs *uart)
{
    return ((uart->STAT & UART_STAT_BUSY_MASK) == UART_STAT_BUSY_SET);
}

__STATIC_INLINE bool DL_UART_isRXFIFOEmpty(UART_Regs *uart)
{
    return ((uart->STAT & UART_STAT_RXFE_MASK) == UART_STAT_RXFE_SET);
}

__STATIC_INLINE bool DL_UART_isRXFIFOFull(UART_Regs *uart)
{
    return ((uart->STAT & UART_STAT_RXFF_MASK) == UART_STAT_RXFF_SET);
}

__STATIC_INLINE bool DL_UART_isTXFIFOEmpty(UART_Regs *uart)
{
    return ((uart->STAT & UART_STAT_TXFE_MASK) == UART_STAT_TXFE_SET);
}

__STATIC_INLINE bool DL_UART_isTXFIFOFull(UART_Regs *uart)
{
    return ((uart->STAT & UART_STAT_TXFF_MASK) == UART_STAT_TXFF_SET);
}

__STATIC_INLINE bool DL_UART_isClearToSend(UART_Regs *uart)
{
    return ((uart->STAT & UART_STAT_CTS_MASK) == UART_STAT_CTS_SET);
}

__STATIC_INLINE bool DL_UART_isIdleModeDetected(UART_Regs *uart)
{
    return ((uart->STAT & UART_STAT_IDLE_MASK) == UART_STAT_IDLE_SET);
}

__STATIC_INLINE void DL_UART_setTXFIFOThreshold(
    UART_Regs *uart, DL_UART_TX_FIFO_LEVEL threshold)
{
    DL_Common_updateReg(
        &uart->IFLS, (uint32_t) threshold, UART_IFLS_TXIFLSEL_MASK);
}

__STATIC_INLINE DL_UART_TX_FIFO_LEVEL DL_UART_getTXFIFOThreshold(
    UART_Regs *uart)
{
    uint32_t threshold = uart->IFLS & UART_IFLS_TXIFLSEL_MASK;

    return (DL_UART_TX_FIFO_LEVEL)(threshold);
}

__STATIC_INLINE void DL_UART_setRXFIFOThreshold(
    UART_Regs *uart, DL_UART_RX_FIFO_LEVEL threshold)
{
    DL_Common_updateReg(
        &uart->IFLS, (uint32_t) threshold, UART_IFLS_RXIFLSEL_MASK);
}

__STATIC_INLINE DL_UART_RX_FIFO_LEVEL DL_UART_getRXFIFOThreshold(
    UART_Regs *uart)
{
    uint32_t threshold = uart->IFLS & UART_IFLS_RXIFLSEL_MASK;

    return (DL_UART_RX_FIFO_LEVEL)(threshold);
}

__STATIC_INLINE void DL_UART_setRXInterruptTimeout(
    UART_Regs *uart, uint32_t timeout)
{
    DL_Common_updateReg(
        &uart->IFLS, timeout << UART_IFLS_RXTOSEL_OFS, UART_IFLS_RXTOSEL_MASK);
}

__STATIC_INLINE uint32_t DL_UART_getRXInterruptTimeout(UART_Regs *uart)
{
    return ((uart->IFLS & UART_IFLS_RXTOSEL_MASK) >> UART_IFLS_RXTOSEL_OFS);
}

__STATIC_INLINE uint32_t DL_UART_getIntegerBaudRateDivisor(UART_Regs *uart)
{
    return (uart->IBRD & UART_IBRD_DIVINT_MASK);
}

__STATIC_INLINE uint32_t DL_UART_getFractionalBaudRateDivisor(UART_Regs *uart)
{
    return (uart->FBRD & UART_FBRD_DIVFRAC_MASK);
}

__STATIC_INLINE void DL_UART_setBaudRateDivisor(
    UART_Regs *uart, uint32_t integerDivisor, uint32_t fractionalDivisor)
{
    DL_Common_updateReg(&uart->IBRD, integerDivisor, UART_IBRD_DIVINT_MASK);
    DL_Common_updateReg(
        &uart->FBRD, fractionalDivisor, UART_FBRD_DIVFRAC_MASK);

    // When updating the baud-rate divisor (UARTIBRD or UARTIFRD),
    // the LCRH register must also be written to (any bit in LCRH can
    // be written to for updating the baud-rate divisor).
    DL_Common_updateReg(
        &uart->LCRH, (uart->LCRH & UART_LCRH_BRK_MASK), UART_LCRH_BRK_MASK);
}

__STATIC_INLINE void DL_UART_setIrDABaudRateDivisor(
    UART_Regs *uart, uint32_t integerDivisor, uint32_t fractionalDivisor, DL_UART_CLOCK_DIVIDE2_RATIO clkDivisor2)
{
    DL_Common_updateReg(&uart->IBRD, (integerDivisor / ((uint32_t)clkDivisor2 + 1)), UART_IBRD_DIVINT_MASK);
    DL_Common_updateReg(
        &uart->FBRD, fractionalDivisor, UART_FBRD_DIVFRAC_MASK);

    // When updating the baud-rate divisor (UARTIBRD or UARTIFRD),
    // the LCRH register must also be written to (any bit in LCRH can
    // be written to for updating the baud-rate divisor).
    DL_Common_updateReg(
        &uart->LCRH, (uart->LCRH & UART_LCRH_BRK_MASK), UART_LCRH_BRK_MASK);
}


__STATIC_INLINE void DL_UART_setDigitalPulseWidth(
    UART_Regs *uart, uint32_t pulseWidth)
{
    DL_Common_updateReg(&uart->GFCTL, pulseWidth, UART_GFCTL_DGFSEL_MASK);
}

__STATIC_INLINE uint32_t DL_UART_getDigitalPulseWidth(UART_Regs *uart)
{
    return (uart->GFCTL & UART_GFCTL_DGFSEL_MASK);
}

__STATIC_INLINE void DL_UART_transmitData(UART_Regs *uart, uint8_t data)
{
    uart->TXDATA = data;
}

__STATIC_INLINE uint8_t DL_UART_receiveData(UART_Regs *uart)
{
    return ((uint8_t)(uart->RXDATA & UART_RXDATA_DATA_MASK));
}

__STATIC_INLINE uint32_t DL_UART_getErrorStatus(
    UART_Regs *uart, uint32_t errorMask)
{
    return (uart->RXDATA & errorMask);
}

__STATIC_INLINE void DL_UART_setLINCounterValue(
    UART_Regs *uart, uint16_t value)
{
    DL_Common_updateReg(&uart->LINCNT, value, UART_LINCNT_VALUE_MASK);
}

__STATIC_INLINE uint16_t DL_UART_getLINCounterValue(UART_Regs *uart)
{
    return ((uint16_t)(uart->LINCNT & UART_LINCNT_VALUE_MASK));
}

__STATIC_INLINE void DL_UART_enableLINCounter(UART_Regs *uart)
{
    uart->LINCTL |= UART_LINCTL_CTRENA_ENABLE;
}

__STATIC_INLINE bool DL_UART_isLINCounterEnabled(UART_Regs *uart)
{
    return (
        (uart->LINCTL & UART_LINCTL_CTRENA_MASK) == UART_LINCTL_CTRENA_ENABLE);
}

__STATIC_INLINE void DL_UART_disableLINCounter(UART_Regs *uart)
{
    uart->LINCTL &= ~(UART_LINCTL_CTRENA_MASK);
}

__STATIC_INLINE void DL_UART_enableLINCounterClearOnFallingEdge(
    UART_Regs *uart)
{
    uart->LINCTL |= UART_LINCTL_ZERONE_ENABLE;
}

__STATIC_INLINE bool DL_UART_isLINCounterClearOnFallingEdge(UART_Regs *uart)
{
    return (
        (uart->LINCTL & UART_LINCTL_ZERONE_MASK) == UART_LINCTL_ZERONE_ENABLE);
}

__STATIC_INLINE void DL_UART_disableLINCounterClearOnFallingEdge(
    UART_Regs *uart)
{
    uart->LINCTL &= ~(UART_LINCTL_ZERONE_MASK);
}

__STATIC_INLINE void DL_UART_enableLINCountWhileLow(UART_Regs *uart)
{
    uart->LINCTL |= UART_LINCTL_CNTRXLOW_ENABLE;
}

__STATIC_INLINE bool DL_UART_isLINCountWhileLowEnabled(UART_Regs *uart)
{
    return ((uart->LINCTL & UART_LINCTL_CNTRXLOW_MASK) ==
            UART_LINCTL_CNTRXLOW_ENABLE);
}

__STATIC_INLINE void DL_UART_disableLINCountWhileLow(UART_Regs *uart)
{
    uart->LINCTL &= ~(UART_LINCTL_CNTRXLOW_MASK);
}

__STATIC_INLINE void DL_UART_enableLINFallingEdgeCapture(UART_Regs *uart)
{
    DL_Common_updateReg(&uart->LINCTL,
        UART_LINCTL_LINC0CAP_ENABLE | UART_LINCTL_LINC0_MATCH_DISABLE,
        UART_LINCTL_LINC0CAP_MASK | UART_LINCTL_LINC0_MATCH_MASK);
}

__STATIC_INLINE bool DL_UART_isLINFallingEdgeCaptureEnabled(UART_Regs *uart)
{
    return ((uart->LINCTL & UART_LINCTL_LINC0CAP_MASK) ==
            UART_LINCTL_LINC0CAP_ENABLE);
}

__STATIC_INLINE void DL_UART_disableLINFallingEdgeCapture(UART_Regs *uart)
{
    uart->LINCTL &= ~(UART_LINCTL_LINC0CAP_MASK);
}

__STATIC_INLINE void DL_UART_enableLINRisingEdgeCapture(UART_Regs *uart)
{
    uart->LINCTL |= UART_LINCTL_LINC1CAP_ENABLE;
}

__STATIC_INLINE bool DL_UART_isLINRisingEdgeCaptureEnabled(UART_Regs *uart)
{
    return ((uart->LINCTL & UART_LINCTL_LINC1CAP_MASK) ==
            UART_LINCTL_LINC1CAP_ENABLE);
}

__STATIC_INLINE void DL_UART_disableLINRisingEdgeCapture(UART_Regs *uart)
{
    uart->LINCTL &= ~(UART_LINCTL_LINC1CAP_MASK);
}

__STATIC_INLINE void DL_UART_enableLINCounterCompareMatch(UART_Regs *uart)
{
    DL_Common_updateReg(&uart->LINCTL,
        UART_LINCTL_LINC0_MATCH_ENABLE | UART_LINCTL_LINC0CAP_DISABLE,
        UART_LINCTL_LINC0CAP_MASK | UART_LINCTL_LINC0_MATCH_MASK);
}

__STATIC_INLINE void DL_UART_enableLINSyncFieldValidationCounterControl(
    UART_Regs *uart)
{
    DL_Common_updateReg(&uart->LINCTL,
        UART_LINCTL_LINC0CAP_ENABLE | UART_LINCTL_LINC1CAP_ENABLE |
            UART_LINCTL_ZERONE_ENABLE | UART_LINCTL_CTRENA_ENABLE,
        UART_LINCTL_LINC0CAP_MASK | UART_LINCTL_LINC1CAP_MASK |
            UART_LINCTL_ZERONE_MASK | UART_LINCTL_CTRENA_MASK);
}

__STATIC_INLINE void DL_UART_enableLINReceptionCountControl(UART_Regs *uart)
{
    DL_Common_updateReg(&uart->LINCTL,
        UART_LINCTL_CNTRXLOW_ENABLE | UART_LINCTL_ZERONE_ENABLE |
            UART_LINCTL_CTRENA_ENABLE,
        UART_LINCTL_CNTRXLOW_MASK | UART_LINCTL_ZERONE_MASK |
            UART_LINCTL_CTRENA_MASK);
}

__STATIC_INLINE bool DL_UART_isLINCounterCompareMatchEnabled(UART_Regs *uart)
{
    return ((uart->LINCTL & UART_LINCTL_LINC0_MATCH_MASK) ==
            UART_LINCTL_LINC0_MATCH_ENABLE);
}

__STATIC_INLINE void DL_UART_disableLINCounterCompareMatch(UART_Regs *uart)
{
    uart->LINCTL &= ~(UART_LINCTL_LINC0_MATCH_MASK);
}

__STATIC_INLINE void DL_UART_setLINCounterCompareValue(
    UART_Regs *uart, uint16_t value)
{
    DL_Common_updateReg(&uart->LINC0, value, UART_LINC0_DATA_MASK);
}

__STATIC_INLINE uint16_t DL_UART_getLINFallingEdgeCaptureValue(UART_Regs *uart)
{
    return ((uint16_t)(uart->LINC0 & UART_LINC0_DATA_MASK));
}

__STATIC_INLINE uint16_t DL_UART_getLINRisingEdgeCaptureValue(UART_Regs *uart)
{
    return ((uint16_t)(uart->LINC1 & UART_LINC1_DATA_MASK));
}

__STATIC_INLINE void DL_UART_enableIrDAMode(UART_Regs *uart)
{
    uart->IRCTL |= UART_IRCTL_IREN_ENABLE;
}

__STATIC_INLINE bool DL_UART_isIrDAModeEnabled(UART_Regs *uart)
{
    return ((uart->IRCTL & UART_IRCTL_IREN_MASK) == UART_IRCTL_IREN_ENABLE);
}

__STATIC_INLINE void DL_UART_disableIrDAMode(UART_Regs *uart)
{
    uart->IRCTL &= ~(UART_IRCTL_IREN_MASK);
}

__STATIC_INLINE void DL_UART_setIrDATXPulseClockSelect(
    UART_Regs *uart, DL_UART_IRDA_CLOCK uartClock)
{
    DL_Common_updateReg(
        &uart->IRCTL, (uint32_t) uartClock, UART_IRCTL_IRTXCLK_MASK);
}

__STATIC_INLINE DL_UART_IRDA_CLOCK DL_UART_getIrDATXPulseClockSelect(
    UART_Regs *uart)
{
    uint32_t uartClock = uart->IRCTL & UART_IRCTL_IRTXCLK_MASK;

    return (DL_UART_IRDA_CLOCK)(uartClock);
}

void DL_UART_configIrDAMode(UART_Regs *uart, DL_UART_IRDA_POLARITY polarity,
    uint32_t pulseLength, DL_UART_IRDA_CLOCK irdaClk);

void DL_UART_setIrDAPulseLength(
    UART_Regs *uart, uint32_t pulseLength, DL_UART_IRDA_CLOCK irdaClk);

__STATIC_INLINE uint32_t DL_UART_getIrDATXPulseLength(UART_Regs *uart)
{
    return (uart->IRCTL & UART_IRCTL_IRTXPL_MASK);
}

__STATIC_INLINE void DL_UART_setIrDARXPulsePolarity(
    UART_Regs *uart, DL_UART_IRDA_POLARITY polarity)
{
    DL_Common_updateReg(
        &uart->IRCTL, (uint32_t) polarity, UART_IRCTL_IRRXPL_MASK);
}

__STATIC_INLINE DL_UART_IRDA_POLARITY DL_UART_getIrDARXPulsePolarity(
    UART_Regs *uart)
{
    uint32_t polarity = uart->IRCTL & UART_IRCTL_IRRXPL_MASK;

    return (DL_UART_IRDA_POLARITY)(polarity);
}

__STATIC_INLINE void DL_UART_setAddressMask(
    UART_Regs *uart, uint32_t addressMask)
{
    DL_Common_updateReg(&uart->AMASK, addressMask, UART_AMASK_VALUE_MASK);
}

__STATIC_INLINE uint32_t DL_UART_getAddressMask(UART_Regs *uart)
{
    return (uart->AMASK & UART_AMASK_VALUE_MASK);
}

__STATIC_INLINE void DL_UART_setAddress(UART_Regs *uart, uint32_t address)
{
    DL_Common_updateReg(&uart->ADDR, address, UART_ADDR_VALUE_MASK);
}

__STATIC_INLINE uint32_t DL_UART_getAddress(UART_Regs *uart)
{
    return (uart->ADDR & UART_ADDR_VALUE_MASK);
}

__STATIC_INLINE void DL_UART_enableInterrupt(
    UART_Regs *uart, uint32_t interruptMask)
{
    uart->CPU_INT.IMASK |= interruptMask;
}

__STATIC_INLINE void DL_UART_disableInterrupt(
    UART_Regs *uart, uint32_t interruptMask)
{
    uart->CPU_INT.IMASK &= ~(interruptMask);
}

__STATIC_INLINE uint32_t DL_UART_getEnabledInterrupts(
    UART_Regs *uart, uint32_t interruptMask)
{
    return (uart->CPU_INT.IMASK & interruptMask);
}

__STATIC_INLINE uint32_t DL_UART_getEnabledInterruptStatus(
    UART_Regs *uart, uint32_t interruptMask)
{
    return (uart->CPU_INT.MIS & interruptMask);
}

__STATIC_INLINE uint32_t DL_UART_getRawInterruptStatus(
    UART_Regs *uart, uint32_t interruptMask)
{
    return (uart->CPU_INT.RIS & interruptMask);
}

__STATIC_INLINE DL_UART_IIDX DL_UART_getPendingInterrupt(UART_Regs *uart)
{
    return (DL_UART_IIDX)(uart->CPU_INT.IIDX);
}

__STATIC_INLINE void DL_UART_clearInterruptStatus(
    UART_Regs *uart, uint32_t interruptMask)
{
    uart->CPU_INT.ICLR = interruptMask;
}

__STATIC_INLINE void DL_UART_changeConfig(UART_Regs *uart)
{
    DL_UART_disable(uart);
    while (DL_UART_isBusy(uart)) {
        ;
    }
    DL_UART_disableFIFOs(uart);
}

__STATIC_INLINE void DL_UART_enableAnalogGlitchFilter(UART_Regs *uart)
{
    uart->GFCTL |= UART_GFCTL_AGFEN_ENABLE;
}

__STATIC_INLINE void DL_UART_disableAnalogGlitchFilter(UART_Regs *uart)
{
    uart->GFCTL &= ~(UART_GFCTL_AGFEN_MASK);
}

__STATIC_INLINE bool DL_UART_isAnalogGlitchFilterEnabled(UART_Regs *uart)
{
    return ((uart->GFCTL & UART_GFCTL_AGFEN_MASK) == UART_GFCTL_AGFEN_ENABLE);
}

__STATIC_INLINE void DL_UART_enableGlitchFilterChaining(UART_Regs *uart)
{
    uart->GFCTL |= UART_GFCTL_CHAIN_ENABLED;
}

__STATIC_INLINE void DL_UART_disableGlitchFilterChaining(UART_Regs *uart)
{
    uart->GFCTL &= ~(UART_GFCTL_CHAIN_MASK);
}

__STATIC_INLINE bool DL_UART_isGlitchFilterChainingEnabled(UART_Regs *uart)
{
    return ((uart->GFCTL & UART_GFCTL_CHAIN_MASK) == UART_GFCTL_CHAIN_ENABLED);
}

__STATIC_INLINE void DL_UART_setAnalogPulseWidth(
    UART_Regs *uart, DL_UART_PULSE_WIDTH pulseWidth)
{
    DL_Common_updateReg(
        &uart->GFCTL, (uint32_t) pulseWidth, UART_GFCTL_AGFSEL_MASK);
}

__STATIC_INLINE DL_UART_PULSE_WIDTH DL_UART_getAnalogPulseWidth(
    UART_Regs *uart)
{
    uint32_t pulseWidth = uart->GFCTL & UART_GFCTL_AGFSEL_MASK;

    return (DL_UART_PULSE_WIDTH)(pulseWidth);
}

void DL_UART_transmitDataBlocking(UART_Regs *uart, uint8_t data);

uint8_t DL_UART_receiveDataBlocking(UART_Regs *uart);

bool DL_UART_transmitDataCheck(UART_Regs *uart, uint8_t data);

bool DL_UART_receiveDataCheck(UART_Regs *uart, uint8_t *buffer);

uint32_t DL_UART_drainRXFIFO(
    UART_Regs *uart, uint8_t *buffer, uint32_t maxCount);

uint32_t DL_UART_fillTXFIFO(UART_Regs *uart, uint8_t *buffer, uint32_t count);

__STATIC_INLINE void DL_UART_enableDMAReceiveEvent(
    UART_Regs *uart, uint32_t interrupt)
{
    uart->DMA_TRIG_RX.IMASK = interrupt;
}

__STATIC_INLINE void DL_UART_enableDMATransmitEvent(UART_Regs *uart)
{
    uart->DMA_TRIG_TX.IMASK = UART_DMA_TRIG_TX_IMASK_TXINT_SET;
}

__STATIC_INLINE void DL_UART_disableDMAReceiveEvent(
    UART_Regs *uart, uint32_t interrupt)
{
    uart->DMA_TRIG_RX.IMASK &= ~(interrupt);
}

__STATIC_INLINE void DL_UART_disableDMATransmitEvent(UART_Regs *uart)
{
    uart->DMA_TRIG_TX.IMASK = UART_DMA_TRIG_TX_IMASK_TXINT_CLR;
}

__STATIC_INLINE uint32_t DL_UART_getEnabledDMAReceiveEvent(
    UART_Regs *uart, uint32_t interruptMask)
{
    return (uart->DMA_TRIG_RX.IMASK & interruptMask);
}

__STATIC_INLINE uint32_t DL_UART_getEnabledDMATransmitEvent(UART_Regs *uart)
{
    return (uart->DMA_TRIG_TX.IMASK & UART_DMA_TRIG_TX_IMASK_TXINT_MASK);
}

__STATIC_INLINE uint32_t DL_UART_getEnabledDMAReceiveEventStatus(
    UART_Regs *uart, uint32_t interruptMask)
{
    return (uart->DMA_TRIG_RX.MIS & interruptMask);
}

__STATIC_INLINE uint32_t DL_UART_getEnabledDMATransmitEventStatus(
    UART_Regs *uart)
{
    return (uart->DMA_TRIG_TX.MIS & UART_DMA_TRIG_TX_MIS_TXINT_MASK);
}

__STATIC_INLINE uint32_t DL_UART_getRawDMAReceiveEventStatus(
    UART_Regs *uart, uint32_t interruptMask)
{
    return (uart->DMA_TRIG_RX.RIS & interruptMask);
}

__STATIC_INLINE uint32_t DL_UART_getRawDMATransmitEventStatus(UART_Regs *uart)
{
    return (uart->DMA_TRIG_TX.RIS & UART_DMA_TRIG_TX_RIS_TXINT_MASK);
}

__STATIC_INLINE DL_UART_DMA_IIDX_RX DL_UART_getPendingDMAReceiveEvent(
    UART_Regs *uart)
{
    return (DL_UART_DMA_IIDX_RX)(uart->DMA_TRIG_RX.IIDX);
}

__STATIC_INLINE DL_UART_DMA_IIDX_TX DL_UART_getPendingDMATransmitEvent(
    UART_Regs *uart)
{
    return (DL_UART_DMA_IIDX_TX)(uart->DMA_TRIG_TX.IIDX);
}

__STATIC_INLINE void DL_UART_clearDMAReceiveEventStatus(
    UART_Regs *uart, uint32_t interruptMask)
{
    uart->DMA_TRIG_RX.ICLR = interruptMask;
}

__STATIC_INLINE void DL_UART_clearDMATransmitEventStatus(UART_Regs *uart)
{
    uart->DMA_TRIG_TX.ICLR = UART_DMA_TRIG_TX_ICLR_TXINT_CLR;
}

__STATIC_INLINE void DL_UART_setClockDivider2(
    UART_Regs *uart, DL_UART_CLOCK_DIVIDE2_RATIO ratio)
{
    uart->CLKDIV2 = (uint32_t) ratio;
}

__STATIC_INLINE DL_UART_CLOCK_DIVIDE2_RATIO DL_UART_getClockDivider2(
    UART_Regs *uart)
{
    uint32_t ratio = uart->CLKDIV2;
    return (DL_UART_CLOCK_DIVIDE2_RATIO) ratio;
}
#ifdef __MSPM0_HAS_UART_MAIN__

bool DL_UART_Main_saveConfiguration(
    UART_Regs *uart, DL_UART_Main_backupConfig *ptr);

bool DL_UART_Main_restoreConfiguration(
    UART_Regs *uart, DL_UART_Main_backupConfig *ptr);

#endif /* __MSPM0_HAS_UART_MAIN__ */

#ifdef __MSPM0_HAS_UART_EXTD__

bool DL_UART_Extend_saveConfiguration(
    UART_Regs *uart, DL_UART_Extend_backupConfig *ptr);

bool DL_UART_Extend_restoreConfiguration(
    UART_Regs *uart, DL_UART_Extend_backupConfig *ptr);

#endif /* __MSPM0_HAS_UART_EXTD__ */

#ifdef __cplusplus
}
#endif

#endif /* __MSPM0_HAS_UART_MAIN__ || __MSPM0_HAS_UART_EXTD__ */

#else
#warning \
    "TI highly recommends accessing uart with dl_uart_main, dl_uart_extend.h only."
#endif /* ti_dl_dl_uart_main__include ti_dl_dl_uart_extend__include */

#endif /* ti_dl_dl_uart__include */