dl_timer.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/*!****************************************************************************
 *  @file       dl_timer.h
 *  @brief      Common General Purpose Timer (TIMx) Driver Library
 *  @defgroup   TIMX Common General Purpose Timer (TIMx)
 *
 *  @anchor ti_dl_dl_timer__Overview
 *  # Overview
 *  GPTimer module has different variations and have been defined as TimerG
 *  and TimerA. This file contains APIs which are common between
 *  different variations.
 *  <hr>
 *  @anchor ti_devices_msp_DL_TIMER_Usage
 *  # Usage
 *  It is not recommended to include this header file in the application.
 *  In order to access TimerG and TimerA functionality include
 *  to appropriate timer header file at the application level. Accessing the
 *  functionality via the corresponding header file will allow user to
 *  determine the functionality supported by the each Timer variant.
 *
 *  To access TimerG functionality:
 *  @code
 *  // Import TIMG definitions
 *  #include <ti/driverlib/dl_timerg.h>
 *  @endcode
 *
 *  To access TimerA functionality:
 *  @code
 *  // Import TIMA definitions
 *  #include <ti/driverlib/dl_timera.h>
 *  @endcode
 *
 *  <hr>
 ******************************************************************************
 */
#ifndef ti_dl_dl_timer__include
#define ti_dl_dl_timer__include

#if defined(ti_dl_dl_timera__include) || defined(ti_dl_dl_timerg__include) || \
    defined(DOXYGEN__INCLUDE)

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#if defined(__MSPM0_HAS_TIMER_A__) || defined(__MSPM0_HAS_TIMER_G__)

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

#define DL_TIMER_CC0_OUTPUT                     (GPTIMER_CCPD_C0CCP0_OUTPUT)

#define DL_TIMER_CC0_INPUT                      (GPTIMER_CCPD_C0CCP0_INPUT)

#define DL_TIMER_CC1_OUTPUT                     (GPTIMER_CCPD_C0CCP1_OUTPUT)

#define DL_TIMER_CC1_INPUT                      (GPTIMER_CCPD_C0CCP1_INPUT)

#define DL_TIMER_CC2_OUTPUT                     (GPTIMER_CCPD_C0CCP2_OUTPUT)

#define DL_TIMER_CC2_INPUT                      (GPTIMER_CCPD_C0CCP2_INPUT)

#define DL_TIMER_CC3_OUTPUT                     (GPTIMER_CCPD_C0CCP3_OUTPUT)

#define DL_TIMER_CC3_INPUT                      (GPTIMER_CCPD_C0CCP3_INPUT)

#define DL_TIMER_CC_MODE_COMPARE                  (GPTIMER_CCCTL_01_COC_COMPARE)

#define DL_TIMER_CC_MODE_CAPTURE                 (GPTIMER_CCCTL_01_COC_CAPTURE)

#define DL_TIMER_CC_ZCOND_NONE                         (((uint32_t)0x00000000U))

#define DL_TIMER_CC_ZCOND_TRIG_RISE        (GPTIMER_CCCTL_01_ZCOND_CC_TRIG_RISE)

#define DL_TIMER_CC_ZCOND_TRIG_FALL        (GPTIMER_CCCTL_01_ZCOND_CC_TRIG_FALL)

#define DL_TIMER_CC_ZCOND_TRIG_EDGE        (GPTIMER_CCCTL_01_ZCOND_CC_TRIG_EDGE)

#define DL_TIMER_CC_LCOND_NONE                         ((uint32_t)0x00000000U)

#define DL_TIMER_CC_LCOND_TRIG_RISE       (GPTIMER_CCCTL_01_LCOND_CC_TRIG_RISE)

#define DL_TIMER_CC_LCOND_TRIG_FALL       (GPTIMER_CCCTL_01_LCOND_CC_TRIG_FALL)

#define DL_TIMER_CC_LCOND_TRIG_EDGE       (GPTIMER_CCCTL_01_LCOND_CC_TRIG_EDGE)

#define DL_TIMER_CC_ACOND_TIMCLK                 (GPTIMER_CCCTL_01_ACOND_TIMCLK)

#define DL_TIMER_CC_ACOND_TRIG_RISE       (GPTIMER_CCCTL_01_ACOND_CC_TRIG_RISE)

#define DL_TIMER_CC_ACOND_TRIG_FALL       (GPTIMER_CCCTL_01_ACOND_CC_TRIG_FALL)

#define DL_TIMER_CC_ACOND_TRIG_EDGE       (GPTIMER_CCCTL_01_ACOND_CC_TRIG_EDGE)

#define DL_TIMER_CC_ACOND_TRIG_HIGH       (GPTIMER_CCCTL_01_ACOND_CC_TRIG_HIGH)

#define DL_TIMER_CC_CCOND_NOCAPTURE       (GPTIMER_CCCTL_01_CCOND_NOCAPTURE)

#define DL_TIMER_CC_CCOND_TRIG_RISE       (GPTIMER_CCCTL_01_CCOND_CC_TRIG_RISE)

#define DL_TIMER_CC_CCOND_TRIG_FALL       (GPTIMER_CCCTL_01_CCOND_CC_TRIG_FALL)

#define DL_TIMER_CC_CCOND_TRIG_EDGE       (GPTIMER_CCCTL_01_CCOND_CC_TRIG_EDGE)

#define DL_TIMER_CC_OCTL_INIT_VAL_LOW              (GPTIMER_OCTL_01_CCPIV_LOW)

#define DL_TIMER_CC_OCTL_INIT_VAL_HIGH             (GPTIMER_OCTL_01_CCPIV_HIGH)

#define DL_TIMER_CC_OCTL_INV_OUT_ENABLED        (GPTIMER_OCTL_01_CCPOINV_INV)

#define DL_TIMER_CC_OCTL_INV_OUT_DISABLED       (GPTIMER_OCTL_01_CCPOINV_NOINV)

#define DL_TIMER_CC_OCTL_SRC_FUNCVAL       (GPTIMER_OCTL_01_CCPO_FUNCVAL)

#define DL_TIMER_CC_OCTL_SRC_LOAD          (GPTIMER_OCTL_01_CCPO_LOAD)

#define DL_TIMER_CC_OCTL_SRC_CMPVAL        (GPTIMER_OCTL_01_CCPO_CMPVAL)

#define DL_TIMER_CC_OCTL_SRC_ZERO          (GPTIMER_OCTL_01_CCPO_ZERO)

#define DL_TIMER_CC_OCTL_SRC_CAPCOND       (GPTIMER_OCTL_01_CCPO_CAPCOND)

#define DL_TIMER_CC_OCTL_SRC_FAULTCOND       (GPTIMER_OCTL_01_CCPO_FAULTCOND)

#define DL_TIMER_CC_OCTL_SRC_CC0_MIRR_ALL  (GPTIMER_OCTL_01_CCPO_CC0_MIRROR_ALL)

#define DL_TIMER_CC_OCTL_SRC_CC1_MIRR_ALL  (GPTIMER_OCTL_01_CCPO_CC1_MIRROR_ALL)

#define DL_TIMER_CC_OCTL_SRC_DEAD_BAND           (GPTIMER_OCTL_01_CCPO_DEADBAND)

#define DL_TIMER_CC_OCTL_SRC_CNTDIR                (GPTIMER_OCTL_01_CCPO_CNTDIR)

#define DL_TIMER_CC_FEXACT_DISABLED           (GPTIMER_CCACT_01_FEXACT_DISABLED)

#define DL_TIMER_CC_FEXACT_HIGH               (GPTIMER_CCACT_01_FEXACT_CCP_HIGH)

#define DL_TIMER_CC_FEXACT_LOW                 (GPTIMER_CCACT_01_FEXACT_CCP_LOW)

#define DL_TIMER_CC_FEXACT_TOGGLE           (GPTIMER_CCACT_01_FEXACT_CCP_TOGGLE)


#define DL_TIMER_CC_FEXACT_HIGHZ           (GPTIMER_CCACT_01_FEXACT_CCP_HIGHZ)


#define DL_TIMER_CC_FENACT_DISABLED           (GPTIMER_CCACT_01_FENACT_DISABLED)

#define DL_TIMER_CC_FENACT_CCP_HIGH           (GPTIMER_CCACT_01_FENACT_CCP_HIGH)

#define DL_TIMER_CC_FENACT_CCP_LOW             (GPTIMER_CCACT_01_FENACT_CCP_LOW)

#define DL_TIMER_CC_FENACT_CCP_TOGGLE      \
                                            (GPTIMER_CCACT_01_FENACT_CCP_TOGGLE)

#define DL_TIMER_CC_FENACT_HIGHZ           (GPTIMER_CCACT_01_FENACT_CCP_HIGHZ)


#define DL_TIMER_CC_CUACT_DISABLED         (GPTIMER_CCACT_01_CUACT_DISABLED)

#define DL_TIMER_CC_CUACT_CCP_HIGH         (GPTIMER_CCACT_01_CUACT_CCP_HIGH)

#define DL_TIMER_CC_CUACT_CCP_LOW          (GPTIMER_CCACT_01_CUACT_CCP_LOW)

#define DL_TIMER_CC_CUACT_CCP_TOGGLE       (GPTIMER_CCACT_01_CUACT_CCP_TOGGLE)

#define DL_TIMER_CC_CDACT_DISABLED         (GPTIMER_CCACT_01_CDACT_DISABLED)

#define DL_TIMER_CC_CDACT_CCP_HIGH         (GPTIMER_CCACT_01_CDACT_CCP_HIGH)

#define DL_TIMER_CC_CDACT_CCP_LOW          (GPTIMER_CCACT_01_CDACT_CCP_LOW)

#define DL_TIMER_CC_CDACT_CCP_TOGGLE       (GPTIMER_CCACT_01_CDACT_CCP_TOGGLE)

#define DL_TIMER_CC_LACT_DISABLED         (GPTIMER_CCACT_01_LACT_DISABLED)

#define DL_TIMER_CC_LACT_CCP_HIGH         (GPTIMER_CCACT_01_LACT_CCP_HIGH)

#define DL_TIMER_CC_LACT_CCP_LOW          (GPTIMER_CCACT_01_LACT_CCP_LOW)

#define DL_TIMER_CC_LACT_CCP_TOGGLE       (GPTIMER_CCACT_01_LACT_CCP_TOGGLE)

#define DL_TIMER_CC_ZACT_DISABLED         (GPTIMER_CCACT_01_ZACT_DISABLED)

#define DL_TIMER_CC_ZACT_CCP_HIGH         (GPTIMER_CCACT_01_ZACT_CCP_HIGH)

#define DL_TIMER_CC_ZACT_CCP_LOW          (GPTIMER_CCACT_01_ZACT_CCP_LOW)

#define DL_TIMER_CC_ZACT_CCP_TOGGLE       (GPTIMER_CCACT_01_ZACT_CCP_TOGGLE)

#define DL_TIMER_CC_INPUT_INV_NOINVERT (GPTIMER_IFCTL_01_INV_NOINVERT)

#define DL_TIMER_CC_INPUT_INV_INVERT   (GPTIMER_IFCTL_01_INV_INVERT)

#define DL_TIMER_CC_IN_SEL_CCPX      (GPTIMER_IFCTL_01_ISEL_CCPX_INPUT)

#define DL_TIMER_CC_IN_SEL_CCPX_PAIR  (GPTIMER_IFCTL_01_ISEL_CCPX_INPUT_PAIR)

#define DL_TIMER_CC_IN_SEL_CCP0      (GPTIMER_IFCTL_01_ISEL_CCP0_INPUT)

#define DL_TIMER_CC_IN_SEL_TRIG      (GPTIMER_IFCTL_01_ISEL_TRIG_INPUT)


#define DL_TIMER_CC_IN_SEL_CCP_XOR      (GPTIMER_IFCTL_01_ISEL_CCP_XOR)

#define DL_TIMER_CC_IN_SEL_FSUB0      (GPTIMER_IFCTL_01_ISEL_CCP_FSUB0)

#define DL_TIMER_CC_IN_SEL_FSUB1      (GPTIMER_IFCTL_01_ISEL_CCP_FSUB1)

#define DL_TIMER_CC_IN_SEL_COMP0      (GPTIMER_IFCTL_01_ISEL_CCP_COMP0)

#define DL_TIMER_CC_IN_SEL_COMP1      (GPTIMER_IFCTL_01_ISEL_CCP_COMP1)

#define DL_TIMER_CC_IN_SEL_COMP2      (GPTIMER_IFCTL_01_ISEL_CCP_COMP2)



#define DL_TIMER_FAULT_SOURCE_COMP0_DISABLE                                   \
        (GPTIMER_FSCTL_FAC0EN_DISABLE | (GPTIMER_FCTL_FSENAC0_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_COMP0_SENSE_LOW                                 \
        (GPTIMER_FSCTL_FAC0EN_ENABLE | (GPTIMER_FCTL_FSENAC0_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_COMP0_SENSE_HIGH                                \
        (GPTIMER_FSCTL_FAC0EN_ENABLE | (GPTIMER_FCTL_FSENAC0_HIGHACTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_COMP1_DISABLE                                   \
        (GPTIMER_FSCTL_FAC1EN_DISABLE | (GPTIMER_FCTL_FSENAC1_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_COMP1_SENSE_LOW                                 \
        (GPTIMER_FSCTL_FAC1EN_ENABLE | (GPTIMER_FCTL_FSENAC1_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_COMP1_SENSE_HIGH                                \
        (GPTIMER_FSCTL_FAC1EN_ENABLE | (GPTIMER_FCTL_FSENAC1_HIGHACTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_COMP2_DISABLE                                   \
        (GPTIMER_FSCTL_FAC2EN_DISABLE | (GPTIMER_FCTL_FSENAC2_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_COMP2_SENSE_LOW                                 \
        (GPTIMER_FSCTL_FAC2EN_ENABLE | (GPTIMER_FCTL_FSENAC2_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_COMP2_SENSE_HIGH                                \
        (GPTIMER_FSCTL_FAC2EN_ENABLE | (GPTIMER_FCTL_FSENAC2_HIGHACTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_EXTERNAL_0_DISABLE                              \
        (GPTIMER_FSCTL_FEX0EN_DISABLE | (GPTIMER_FCTL_FSENEXT0_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_EXTERNAL_0_SENSE_LOW                            \
        (GPTIMER_FSCTL_FEX0EN_ENABLE | (GPTIMER_FCTL_FSENEXT0_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_EXTERNAL_0_SENSE_HIGH                           \
        (GPTIMER_FSCTL_FEX0EN_ENABLE | (GPTIMER_FCTL_FSENEXT0_HIGHACTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_EXTERNAL_1_DISABLE                              \
        (GPTIMER_FSCTL_FEX1EN_DISABLE | (GPTIMER_FCTL_FSENEXT1_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_EXTERNAL_1_SENSE_LOW                            \
        (GPTIMER_FSCTL_FEX1EN_ENABLE | (GPTIMER_FCTL_FSENEXT1_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_EXTERNAL_1_SENSE_HIGH                           \
        (GPTIMER_FSCTL_FEX1EN_ENABLE | (GPTIMER_FCTL_FSENEXT1_HIGHACTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_EXTERNAL_2_DISABLE                              \
        (GPTIMER_FSCTL_FEX2EN_DISABLE | (GPTIMER_FCTL_FSENEXT2_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_EXTERNAL_2_SENSE_LOW                            \
        (GPTIMER_FSCTL_FEX2EN_ENABLE | (GPTIMER_FCTL_FSENEXT2_LOWCTIVE << 16))

#define DL_TIMER_FAULT_SOURCE_EXTERNAL_2_SENSE_HIGH                           \
        (GPTIMER_FSCTL_FEX2EN_ENABLE | (GPTIMER_FCTL_FSENEXT2_HIGHACTIVE << 16))

#define DL_TIMER_FAULT_CONFIG_TFIM_DISABLED         (GPTIMER_FCTL_TFIM_DISABLED)

#define DL_TIMER_FAULT_CONFIG_TFIM_ENABLED           (GPTIMER_FCTL_TFIM_ENABLED)

#define DL_TIMER_FAULT_CONFIG_FL_NO_LATCH  (GPTIMER_FCTL_FL_NO_LATCH)

#define DL_TIMER_FAULT_CONFIG_FL_LATCH_SW_CLR    (GPTIMER_FCTL_FL_LATCH_SW_CLR)

#define DL_TIMER_FAULT_CONFIG_FL_LATCH_Z_CLR   (GPTIMER_FCTL_FL_LATCH_Z_CLR)

#define DL_TIMER_FAULT_CONFIG_FL_LATCH_LD_CLR    (GPTIMER_FCTL_FL_LATCH_LD_CLR)

#define DL_TIMER_FAULT_CONFIG_FI_INDEPENDENT  (GPTIMER_FCTL_FI_INDEPENDENT)

#define DL_TIMER_FAULT_CONFIG_FI_DEPENDENT    (GPTIMER_FCTL_FI_DEPENDENT)

#define DL_TIMER_FAULT_CONFIG_FIEN_DISABLED  (GPTIMER_FCTL_FIEN_DISABLED)

#define DL_TIMER_FAULT_CONFIG_FIEN_ENABLED   (GPTIMER_FCTL_FIEN_ENABLED)

#define DL_TIMER_FAULT_FILTER_BYPASS     (GPTIMER_FIFCTL_FILTEN_BYPASS)

#define DL_TIMER_FAULT_FILTER_FILTERED   (GPTIMER_FIFCTL_FILTEN_FILTERED)

#define DL_TIMER_FAULT_FILTER_CPV_CONSEC_PER  (GPTIMER_FIFCTL_CPV_CONSEC_PER)

#define DL_TIMER_FAULT_FILTER_CPV_VOTING      (GPTIMER_FIFCTL_CPV_VOTING)


#define DL_TIMER_FAULT_FILTER_FP_PER_3   (GPTIMER_FIFCTL_FP_PER_3)

#define DL_TIMER_FAULT_FILTER_FP_PER_5   (GPTIMER_FIFCTL_FP_PER_5)

#define DL_TIMER_FAULT_FILTER_FP_PER_8   (GPTIMER_FIFCTL_FP_PER_8)

#define DL_TIMER_CC_INPUT_FILT_CPV_CONSEC_PER (GPTIMER_IFCTL_01_CPV_CONSECUTIVE)

#define DL_TIMER_CC_INPUT_FILT_CPV_VOTING          (GPTIMER_IFCTL_01_CPV_VOTING)


#define DL_TIMER_CC_INPUT_FILT_FP_PER_3                 (GPTIMER_IFCTL_01_FP__3)

#define DL_TIMER_CC_INPUT_FILT_FP_PER_5                 (GPTIMER_IFCTL_01_FP__5)

#define DL_TIMER_CC_INPUT_FILT_FP_PER_8                 (GPTIMER_IFCTL_01_FP__8)

#define DL_TIMER_INTERRUPT_ZERO_EVENT                      (GPTIMER_CPU_INT_IMASK_Z_SET)

#define DL_TIMER_INTERRUPT_LOAD_EVENT                      (GPTIMER_CPU_INT_IMASK_L_SET)

#define DL_TIMER_INTERRUPT_CC0_DN_EVENT                 (GPTIMER_CPU_INT_IMASK_CCD0_SET)

#define DL_TIMER_INTERRUPT_CC1_DN_EVENT                 (GPTIMER_CPU_INT_IMASK_CCD1_SET)

#define DL_TIMER_INTERRUPT_CC0_UP_EVENT                 (GPTIMER_CPU_INT_IMASK_CCU0_SET)

#define DL_TIMER_INTERRUPT_CC1_UP_EVENT                 (GPTIMER_CPU_INT_IMASK_CCU1_SET)

#define DL_TIMER_INTERRUPT_OVERFLOW_EVENT                (GPTIMER_CPU_INT_IMASK_TOV_SET)

#define DL_TIMER_INTERRUPT_DC_EVENT                       (GPTIMER_CPU_INT_IMASK_DC_SET)


#define DL_TIMER_INTERRUPT_QEIERR_EVENT               (GPTIMER_CPU_INT_IMASK_QEIERR_SET)


#define DL_TIMER_EVENT_ZERO_EVENT                          (GPTIMER_GEN_EVENT0_IMASK_Z_SET)

#define DL_TIMER_EVENT_LOAD_EVENT                          (GPTIMER_GEN_EVENT0_IMASK_L_SET)

#define DL_TIMER_EVENT_CC0_DN_EVENT                     (GPTIMER_GEN_EVENT0_IMASK_CCD0_SET)

#define DL_TIMER_EVENT_CC1_DN_EVENT                     (GPTIMER_GEN_EVENT0_IMASK_CCD1_SET)

#define DL_TIMER_EVENT_CC0_UP_EVENT                     (GPTIMER_GEN_EVENT0_IMASK_CCU0_SET)

#define DL_TIMER_EVENT_CC1_UP_EVENT                     (GPTIMER_GEN_EVENT0_IMASK_CCU1_SET)

#define DL_TIMER_EVENT_OVERFLOW_EVENT                    (GPTIMER_GEN_EVENT0_IMASK_TOV_SET)

#define DL_TIMER_EVENT_DC_EVENT                           (GPTIMER_GEN_EVENT0_IMASK_DC_SET)


#define DL_TIMER_EVENT_QEIERR_EVENT                   (GPTIMER_GEN_EVENT0_IMASK_QEIERR_SET)


#define DL_TIMER_CCP0_DIS_OUT_ADV_FORCE_LOW (GPTIMER_ODIS_C0CCP0_CCP_OUTPUT_LOW)

#define DL_TIMER_CCP0_DIS_OUT_ADV_SET_BY_OCTL \
                                           (GPTIMER_ODIS_C0CCP0_CCP_OUTPUT_OCTL)

#define DL_TIMER_CCP1_DIS_OUT_ADV_FORCE_LOW (GPTIMER_ODIS_C0CCP1_CCP_OUTPUT_LOW)

#define DL_TIMER_CCP1_DIS_OUT_ADV_SET_BY_OCTL \
                                           (GPTIMER_ODIS_C0CCP1_CCP_OUTPUT_OCTL)

#define DL_TIMER_CCP2_DIS_OUT_ADV_FORCE_LOW (GPTIMER_ODIS_C0CCP2_CCP_OUTPUT_LOW)

#define DL_TIMER_CCP2_DIS_OUT_ADV_SET_BY_OCTL \
                                           (GPTIMER_ODIS_C0CCP2_CCP_OUTPUT_OCTL)

#define DL_TIMER_CCP3_DIS_OUT_ADV_FORCE_LOW (GPTIMER_ODIS_C0CCP3_CCP_OUTPUT_LOW)

#define DL_TIMER_CCP3_DIS_OUT_ADV_SET_BY_OCTL \
                                           (GPTIMER_ODIS_C0CCP3_CCP_OUTPUT_OCTL)

/* clang-format on */

typedef enum {
    DL_TIMER_CLOCK_BUSCLK = GPTIMER_CLKSEL_BUSCLK_SEL_ENABLE,
    DL_TIMER_CLOCK_MFCLK = GPTIMER_CLKSEL_MFCLK_SEL_ENABLE,
    DL_TIMER_CLOCK_LFCLK = GPTIMER_CLKSEL_LFCLK_SEL_ENABLE,
    DL_TIMER_CLOCK_DISABLE = GPTIMER_CLKSEL_LFCLK_SEL_DISABLE,
} DL_TIMER_CLOCK;

typedef enum {
    DL_TIMER_CLOCK_DIVIDE_1 = GPTIMER_CLKDIV_RATIO_DIV_BY_1,
    DL_TIMER_CLOCK_DIVIDE_2 = GPTIMER_CLKDIV_RATIO_DIV_BY_2,
    DL_TIMER_CLOCK_DIVIDE_3 = GPTIMER_CLKDIV_RATIO_DIV_BY_3,
    DL_TIMER_CLOCK_DIVIDE_4 = GPTIMER_CLKDIV_RATIO_DIV_BY_4,
    DL_TIMER_CLOCK_DIVIDE_5 = GPTIMER_CLKDIV_RATIO_DIV_BY_5,
    DL_TIMER_CLOCK_DIVIDE_6 = GPTIMER_CLKDIV_RATIO_DIV_BY_6,
    DL_TIMER_CLOCK_DIVIDE_7 = GPTIMER_CLKDIV_RATIO_DIV_BY_7,
    DL_TIMER_CLOCK_DIVIDE_8 = GPTIMER_CLKDIV_RATIO_DIV_BY_8,
} DL_TIMER_CLOCK_DIVIDE;

typedef enum {
    DL_TIMER_CCP_DIS_OUT_LOW = GPTIMER_ODIS_C0CCP0_CCP_OUTPUT_LOW,
    DL_TIMER_CCP_DIS_OUT_SET_BY_OCTL = GPTIMER_ODIS_C0CCP0_CCP_OUTPUT_OCTL,
} DL_TIMER_CCP_DIS_OUT;

typedef enum {
    DL_TIMER_CC_0_INDEX = 0,
    DL_TIMER_CC_1_INDEX = 1,
    DL_TIMER_CC_2_INDEX = 2,
    DL_TIMER_CC_3_INDEX = 3,

    DL_TIMER_CC_4_INDEX = 4,
    DL_TIMER_CC_5_INDEX = 5,

} DL_TIMER_CC_INDEX;

typedef enum {
    DL_TIMER_EXT_TRIG_SEL_TRIG_0 = GPTIMER_TSEL_ETSEL_TRIG0,
    DL_TIMER_EXT_TRIG_SEL_TRIG_1 = GPTIMER_TSEL_ETSEL_TRIG1,
    DL_TIMER_EXT_TRIG_SEL_TRIG_2 = GPTIMER_TSEL_ETSEL_TRIG2,
    DL_TIMER_EXT_TRIG_SEL_TRIG_3 = GPTIMER_TSEL_ETSEL_TRIG3,
    DL_TIMER_EXT_TRIG_SEL_TRIG_4 = GPTIMER_TSEL_ETSEL_TRIG4,
    DL_TIMER_EXT_TRIG_SEL_TRIG_5 = GPTIMER_TSEL_ETSEL_TRIG5,
    DL_TIMER_EXT_TRIG_SEL_TRIG_6 = GPTIMER_TSEL_ETSEL_TRIG6,
    DL_TIMER_EXT_TRIG_SEL_TRIG_7 = GPTIMER_TSEL_ETSEL_TRIG7,
    DL_TIMER_EXT_TRIG_SEL_TRIG_8 = GPTIMER_TSEL_ETSEL_TRIG8,
    DL_TIMER_EXT_TRIG_SEL_TRIG_9 = GPTIMER_TSEL_ETSEL_TRIG9,
    DL_TIMER_EXT_TRIG_SEL_TRIG_10 = GPTIMER_TSEL_ETSEL_TRIG10,
    DL_TIMER_EXT_TRIG_SEL_TRIG_11 = GPTIMER_TSEL_ETSEL_TRIG11,
    DL_TIMER_EXT_TRIG_SEL_TRIG_12 = GPTIMER_TSEL_ETSEL_TRIG12,
    DL_TIMER_EXT_TRIG_SEL_TRIG_13 = GPTIMER_TSEL_ETSEL_TRIG13,
    DL_TIMER_EXT_TRIG_SEL_TRIG_14 = GPTIMER_TSEL_ETSEL_TRIG14,
    DL_TIMER_EXT_TRIG_SEL_TRIG_15 = GPTIMER_TSEL_ETSEL_TRIG15,
    DL_TIMER_EXT_TRIG_SEL_TRIG_SUB_0 = GPTIMER_TSEL_ETSEL_TRIG_SUB0,
    DL_TIMER_EXT_TRIG_SEL_TRIG_SUB_1 = GPTIMER_TSEL_ETSEL_TRIG_SUB1,
} DL_TIMER_EXT_TRIG_SEL;

typedef enum {
    DL_TIMER_TIMER_MODE_ONE_SHOT =
        (GPTIMER_CTRCTL_CM_DOWN | GPTIMER_CTRCTL_REPEAT_REPEAT_0),
    DL_TIMER_TIMER_MODE_PERIODIC =
        (GPTIMER_CTRCTL_CM_DOWN | GPTIMER_CTRCTL_REPEAT_REPEAT_1),
    DL_TIMER_TIMER_MODE_ONE_SHOT_UP =
        (GPTIMER_CTRCTL_CM_UP | GPTIMER_CTRCTL_REPEAT_REPEAT_0),
    DL_TIMER_TIMER_MODE_PERIODIC_UP =
        (GPTIMER_CTRCTL_CM_UP | GPTIMER_CTRCTL_REPEAT_REPEAT_1),
    DL_TIMER_TIMER_MODE_ONE_SHOT_UP_DOWN =
        (GPTIMER_CTRCTL_CM_UP_DOWN | GPTIMER_CTRCTL_REPEAT_REPEAT_0),
    DL_TIMER_TIMER_MODE_PERIODIC_UP_DOWN =
        (GPTIMER_CTRCTL_CM_UP_DOWN | GPTIMER_CTRCTL_REPEAT_REPEAT_1),
} DL_TIMER_TIMER_MODE;

typedef enum {
    DL_TIMER_CAPTURE_MODE_EDGE_TIME,
    DL_TIMER_CAPTURE_MODE_PERIOD_CAPTURE,
    DL_TIMER_CAPTURE_MODE_PULSE_WIDTH,
    DL_TIMER_CAPTURE_MODE_EDGE_TIME_UP,
    DL_TIMER_CAPTURE_MODE_PERIOD_CAPTURE_UP,
    DL_TIMER_CAPTURE_MODE_PULSE_WIDTH_UP,
} DL_TIMER_CAPTURE_MODE;

typedef enum {
    DL_TIMER_CAPTURE_COMBINED_MODE_PULSE_WIDTH_AND_PERIOD,
    DL_TIMER_CAPTURE_COMBINED_MODE_PULSE_WIDTH_AND_PERIOD_UP,
} DL_TIMER_CAPTURE_COMBINED_MODE;

typedef enum {
    DL_TIMER_COMPARE_MODE_EDGE_COUNT,
    DL_TIMER_COMPARE_MODE_EDGE_COUNT_UP,
    DL_TIMER_COMPARE_MODE_EDGE_COUNT_UP_DOWN,
} DL_TIMER_COMPARE_MODE;

typedef enum {
    DL_TIMER_COUNT_MODE_DOWN = GPTIMER_CTRCTL_CM_DOWN,
    DL_TIMER_COUNT_MODE_UP_DOWN = GPTIMER_CTRCTL_CM_UP_DOWN,
    DL_TIMER_COUNT_MODE_UP = GPTIMER_CTRCTL_CM_UP,
} DL_TIMER_COUNT_MODE;

typedef enum {
    DL_TIMER_START = GPTIMER_CTRCTL_EN_ENABLED,
    DL_TIMER_STOP = GPTIMER_CTRCTL_EN_DISABLED,
} DL_TIMER;

typedef enum {

    DL_TIMER_INTERM_INT_ENABLED = GPTIMER_CCCTL_01_COC_COMPARE,
    DL_TIMER_INTERM_INT_DISABLED = GPTIMER_CCCTL_01_COC_CAPTURE,

} DL_TIMER_INTERM_INT;

typedef enum {
    DL_TIMER_CAPTURE_EDGE_DETECTION_MODE_RISING =
        GPTIMER_CCCTL_01_CCOND_CC_TRIG_RISE,
    DL_TIMER_CAPTURE_EDGE_DETECTION_MODE_FALLING =
        GPTIMER_CCCTL_01_CCOND_CC_TRIG_FALL,
} DL_TIMER_CAPTURE_EDGE_DETECTION_MODE;

typedef enum {
    DL_TIMER_COMPARE_EDGE_DETECTION_MODE_RISING =
        GPTIMER_CCCTL_01_ACOND_CC_TRIG_RISE,
    DL_TIMER_COMPARE_EDGE_DETECTION_MODE_FALLING =
        GPTIMER_CCCTL_01_ACOND_CC_TRIG_FALL,
    DL_TIMER_COMPARE_EDGE_DETECTION_MODE_EDGE =
        GPTIMER_CCCTL_01_ACOND_CC_TRIG_EDGE,
} DL_TIMER_COMPARE_EDGE_DETECTION_MODE;

typedef enum {
    DL_TIMER_PWM_MODE_EDGE_ALIGN = GPTIMER_CTRCTL_CM_DOWN,
    DL_TIMER_PWM_MODE_EDGE_ALIGN_UP = GPTIMER_CTRCTL_CM_UP,
    DL_TIMER_PWM_MODE_CENTER_ALIGN = GPTIMER_CTRCTL_CM_UP_DOWN,
} DL_TIMER_PWM_MODE;

typedef enum {
    DL_TIMER_DEAD_BAND_MODE_0 = GPTIMER_DBCTL_M1_ENABLE_DISABLED,
    DL_TIMER_DEAD_BAND_MODE_1 = GPTIMER_DBCTL_M1_ENABLE_ENABLED,
} DL_TIMER_DEAD_BAND_MODE;

typedef enum {
    DL_TIMER_FAULT_ENTRY_CCP_DISABLED = GPTIMER_CCACT_01_FENACT_DISABLED,
    DL_TIMER_FAULT_ENTRY_CCP_HIGH = GPTIMER_CCACT_01_FENACT_CCP_HIGH,
    DL_TIMER_FAULT_ENTRY_CCP_LOW = GPTIMER_CCACT_01_FENACT_CCP_LOW,
    DL_TIMER_FAULT_ENTRY_CCP_TOGGLE = GPTIMER_CCACT_01_FENACT_CCP_TOGGLE,

    DL_TIMER_FAULT_ENTRY_CCP_HIGHZ = GPTIMER_CCACT_01_FENACT_CCP_HIGHZ,

} DL_TIMER_FAULT_ENTRY_CCP;

typedef enum {
    DL_TIMER_FAULT_EXIT_CCP_DISABLED = GPTIMER_CCACT_01_FEXACT_DISABLED,
    DL_TIMER_FAULT_EXIT_CCP_HIGH = GPTIMER_CCACT_01_FEXACT_CCP_HIGH,
    DL_TIMER_FAULT_EXIT_CCP_LOW = GPTIMER_CCACT_01_FEXACT_CCP_LOW,
    DL_TIMER_FAULT_EXIT_CCP_TOGGLE = GPTIMER_CCACT_01_FEXACT_CCP_TOGGLE,

    DL_TIMER_FAULT_EXIT_CCP_HIGHZ = GPTIMER_CCACT_01_FEXACT_CCP_HIGHZ,

} DL_TIMER_FAULT_EXIT_CCP;

typedef enum {
    DL_TIMER_FAULT_EXIT_CTR_RESUME = GPTIMER_CTRCTL_FRB_RESUME,
    DL_TIMER_FAULT_EXIT_CTR_CVAE_ACTION = GPTIMER_CTRCTL_FRB_CVAE_ACTION,
} DL_TIMER_FAULT_EXIT_CTR;

typedef enum {
    DL_TIMER_FAULT_ENTRY_CTR_CONT_COUNT = GPTIMER_CTRCTL_FB_CONT_COUNT,
    DL_TIMER_FAULT_ENTRY_CTR_SUSP_COUNT = GPTIMER_CTRCTL_FB_SUSP_COUNT,
} DL_TIMER_FAULT_ENTRY_CTR;

typedef enum {
    DL_TIMER_CROSS_TRIG_SRC_FSUB0 = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_FSUB0,
    DL_TIMER_CROSS_TRIG_SRC_FSUB1 = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_FSUB1,
    DL_TIMER_CROSS_TRIG_SRC_ZERO = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_Z,
    DL_TIMER_CROSS_TRIG_SRC_LOAD = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_L,
    DL_TIMER_CROSS_TRIG_SRC_CCD0 = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_CCD0,
    DL_TIMER_CROSS_TRIG_SRC_CCD1 = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_CCD1,
    DL_TIMER_CROSS_TRIG_SRC_CCD2 = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_CCD2,
    DL_TIMER_CROSS_TRIG_SRC_CCD3 = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_CCD3,
    DL_TIMER_CROSS_TRIG_SRC_CCU0 = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_CCU0,
    DL_TIMER_CROSS_TRIG_SRC_CCU1 = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_CCU1,
    DL_TIMER_CROSS_TRIG_SRC_CCU2 = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_CCU2,
    DL_TIMER_CROSS_TRIG_SRC_CCU3 = GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_CCU3,

} DL_TIMER_CROSS_TRIG_SRC;

typedef enum {
    DL_TIMER_CROSS_TRIGGER_INPUT_ENABLED = GPTIMER_CTTRIGCTL_EVTCTEN_ENABLE,
    DL_TIMER_CROSS_TRIGGER_INPUT_DISABLED = GPTIMER_CTTRIGCTL_EVTCTEN_DISABLED,
} DL_TIMER_CROSS_TRIGGER_INPUT;

typedef enum {
    DL_TIMER_CROSS_TRIGGER_MODE_ENABLED = GPTIMER_CTTRIGCTL_CTEN_ENABLE,
    DL_TIMER_CROSS_TRIGGER_MODE_DISABLED = GPTIMER_CTTRIGCTL_CTEN_DISABLED,
} DL_TIMER_CROSS_TRIGGER_MODE;

typedef enum {
    DL_TIMER_IIDX_ZERO = GPTIMER_CPU_INT_IIDX_STAT_Z,
    DL_TIMER_IIDX_LOAD = GPTIMER_CPU_INT_IIDX_STAT_L,
    DL_TIMER_IIDX_CC0_DN = GPTIMER_CPU_INT_IIDX_STAT_CCD0,
    DL_TIMER_IIDX_CC1_DN = GPTIMER_CPU_INT_IIDX_STAT_CCD1,
    DL_TIMER_IIDX_CC2_DN = GPTIMER_CPU_INT_IIDX_STAT_CCD2,
    DL_TIMER_IIDX_CC3_DN = GPTIMER_CPU_INT_IIDX_STAT_CCD3,
    DL_TIMER_IIDX_CC0_UP = GPTIMER_CPU_INT_IIDX_STAT_CCU0,
    DL_TIMER_IIDX_CC1_UP = GPTIMER_CPU_INT_IIDX_STAT_CCU1,
    DL_TIMER_IIDX_CC2_UP = GPTIMER_CPU_INT_IIDX_STAT_CCU2,
    DL_TIMER_IIDX_CC3_UP = GPTIMER_CPU_INT_IIDX_STAT_CCU3,

    DL_TIMER_IIDX_CC4_DN = GPTIMER_CPU_INT_IIDX_STAT_CCD4,
    DL_TIMER_IIDX_CC5_DN = GPTIMER_CPU_INT_IIDX_STAT_CCD5,
    DL_TIMER_IIDX_CC4_UP = GPTIMER_CPU_INT_IIDX_STAT_CCU4,
    DL_TIMER_IIDX_CC5_UP = GPTIMER_CPU_INT_IIDX_STAT_CCU5,

    DL_TIMER_IIDX_FAULT = GPTIMER_CPU_INT_IIDX_STAT_F,
    DL_TIMER_IIDX_OVERFLOW = GPTIMER_CPU_INT_IIDX_STAT_TOV,
    DL_TIMER_IIDX_REPEAT_COUNT = GPTIMER_CPU_INT_IIDX_STAT_REPC,
    DL_TIMER_IIDX_DIR_CHANGE = GPTIMER_CPU_INT_IIDX_STAT_DC,
} DL_TIMER_IIDX;

typedef enum {
    DL_TIMER_PUBLISHER_INDEX_0 = 0,
    DL_TIMER_PUBLISHER_INDEX_1 = 1
} DL_TIMER_PUBLISHER_INDEX;

typedef enum {
    DL_TIMER_SUBSCRIBER_INDEX_0 = 0,
    DL_TIMER_SUBSCRIBER_INDEX_1 = 1
} DL_TIMER_SUBSCRIBER_INDEX;

typedef enum {
    DL_TIMER_EVENT_ROUTE_1 = 0,
    DL_TIMER_EVENT_ROUTE_2 = 12
} DL_TIMER_EVENT_ROUTE;

typedef enum {
    DL_TIMER_INPUT_CHAN_0,
    DL_TIMER_INPUT_CHAN_1,
    DL_TIMER_INPUT_CHAN_2,
    DL_TIMER_INPUT_CHAN_3,
} DL_TIMER_INPUT_CHAN;

typedef enum {
    DL_TIMER_DEBUG_RES_RESUME = GPTIMER_CTRCTL_DRB_RESUME,
    DL_TIMER_DEBUG_RES_CVAE_ACTION = GPTIMER_CTRCTL_DRB_CVAE_ACTION,
} DL_TIMER_DEBUG_RES;

typedef enum {
    DL_TIMER_CZC_CCCTL0_ZCOND = GPTIMER_CTRCTL_CZC_CCCTL0_ZCOND,
    DL_TIMER_CZC_CCCTL1_ZCOND = GPTIMER_CTRCTL_CZC_CCCTL1_ZCOND,
    DL_TIMER_CZC_CCCTL2_ZCOND = GPTIMER_CTRCTL_CZC_CCCTL2_ZCOND,
    DL_TIMER_CZC_CCCTL3_ZCOND = GPTIMER_CTRCTL_CZC_CCCTL3_ZCOND,
    DL_TIMER_CZC_QEI_2INP = GPTIMER_CTRCTL_CZC_QEI_2INP,
    DL_TIMER_CZC_QEI_3INP = GPTIMER_CTRCTL_CZC_QEI_3INP,
} DL_TIMER_CZC;

typedef enum {
    DL_TIMER_CAC_CCCTL0_ACOND = GPTIMER_CTRCTL_CAC_CCCTL0_ACOND,
    DL_TIMER_CAC_CCCTL1_ACOND = GPTIMER_CTRCTL_CAC_CCCTL1_ACOND,
    DL_TIMER_CAC_CCCTL2_ACOND = GPTIMER_CTRCTL_CAC_CCCTL2_ACOND,
    DL_TIMER_CAC_CCCTL3_ACOND = GPTIMER_CTRCTL_CAC_CCCTL3_ACOND,
    DL_TIMER_CAC_QEI_2INP = GPTIMER_CTRCTL_CAC_QEI_2INP,
    DL_TIMER_CAC_QEI_3INP = GPTIMER_CTRCTL_CAC_QEI_3INP,
} DL_TIMER_CAC;

typedef enum {
    DL_TIMER_CLC_CCCTL0_LCOND = GPTIMER_CTRCTL_CLC_CCCTL0_LCOND,
    DL_TIMER_CLC_CCCTL1_LCOND = GPTIMER_CTRCTL_CLC_CCCTL1_LCOND,
    DL_TIMER_CLC_CCCTL2_LCOND = GPTIMER_CTRCTL_CLC_CCCTL2_LCOND,
    DL_TIMER_CLC_CCCTL3_LCOND = GPTIMER_CTRCTL_CLC_CCCTL3_LCOND,
    DL_TIMER_CLC_QEI_2INP = GPTIMER_CTRCTL_CLC_QEI_2INP,
    DL_TIMER_CLC_QEI_3INP = GPTIMER_CTRCTL_CLC_QEI_3INP,
} DL_TIMER_CLC;

typedef enum {
    DL_TIMER_COUNT_AFTER_EN_LOAD_VAL = GPTIMER_CTRCTL_CVAE_LDVAL,
    DL_TIMER_COUNT_AFTER_EN_NO_CHANGE = GPTIMER_CTRCTL_CVAE_NOCHANGE,
    DL_TIMER_COUNT_AFTER_EN_ZERO = GPTIMER_CTRCTL_CVAE_ZEROVAL,

} DL_TIMER_COUNT_AFTER_EN;

typedef enum {
    DL_TIMER_REPEAT_MODE_DISABLED = GPTIMER_CTRCTL_REPEAT_REPEAT_0,
    DL_TIMER_REPEAT_MODE_ENABLED = GPTIMER_CTRCTL_REPEAT_REPEAT_1,
    DL_TIMER_REPEAT_MODE_ENABLED_DEBUG = GPTIMER_CTRCTL_REPEAT_REPEAT_3,
} DL_TIMER_REPEAT_MODE;

typedef enum {
    DL_TIMER_CC_UPDATE_METHOD_IMMEDIATE = (GPTIMER_CCCTL_01_CCUPD_IMMEDIATELY),
    DL_TIMER_CC_UPDATE_METHOD_ZERO_EVT = (GPTIMER_CCCTL_01_CCUPD_ZERO_EVT),
    DL_TIMER_CC_UPDATE_METHOD_COMP_DN_EVT =
        (GPTIMER_CCCTL_01_CCUPD_COMPARE_DOWN_EVT),
    DL_TIMER_CC_UPDATE_METHOD_COMP_UP_EVT =
        (GPTIMER_CCCTL_01_CCUPD_COMPARE_UP_EVT),
    DL_TIMER_CC_UPDATE_METHOD_ZERO_OR_LOAD_EVT =
        (GPTIMER_CCCTL_01_CCUPD_ZERO_LOAD_EVT),
    DL_TIMER_CC_UPDATE_METHOD_ZERO_RC_EVT =
        (GPTIMER_CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT),
    DL_TIMER_CC_UPDATE_METHOD_TRIG_EVT = (GPTIMER_CCCTL_01_CCUPD_TRIG),
} DL_TIMER_CC_UPDATE_METHOD;

typedef enum {
    DL_TIMER_SEC_COMP_DOWN_EVT_SEL_CC0 = (GPTIMER_CCCTL_01_CC2SELD_SEL_CCD0),
    DL_TIMER_SEC_COMP_DOWN_EVT_SEL_CC1 = (GPTIMER_CCCTL_01_CC2SELD_SEL_CCD1),
    DL_TIMER_SEC_COMP_DOWN_EVT_SEL_CC2 = (GPTIMER_CCCTL_01_CC2SELD_SEL_CCD2),
    DL_TIMER_SEC_COMP_DOWN_EVT_SEL_CC3 = (GPTIMER_CCCTL_01_CC2SELD_SEL_CCD3),
    DL_TIMER_SEC_COMP_DOWN_EVT_SEL_CC4 = (GPTIMER_CCCTL_01_CC2SELD_SEL_CCD4),
    DL_TIMER_SEC_COMP_DOWN_EVT_SEL_CC5 = (GPTIMER_CCCTL_01_CC2SELD_SEL_CCD5),
} DL_TIMER_SEC_COMP_DOWN_EVT;

typedef enum {
    DL_TIMER_SEC_COMP_UP_EVT_SEL_CC0 = (GPTIMER_CCCTL_01_CC2SELU_SEL_CCU0),
    DL_TIMER_SEC_COMP_UP_EVT_SEL_CC1 = (GPTIMER_CCCTL_01_CC2SELU_SEL_CCU1),
    DL_TIMER_SEC_COMP_UP_EVT_SEL_CC2 = (GPTIMER_CCCTL_01_CC2SELU_SEL_CCU2),
    DL_TIMER_SEC_COMP_UP_EVT_SEL_CC3 = (GPTIMER_CCCTL_01_CC2SELU_SEL_CCU3),
    DL_TIMER_SEC_COMP_UP_EVT_SEL_CC4 = (GPTIMER_CCCTL_01_CC2SELU_SEL_CCU4),
    DL_TIMER_SEC_COMP_UP_EVT_SEL_CC5 = (GPTIMER_CCCTL_01_CC2SELU_SEL_CCU5),
} DL_TIMER_SEC_COMP_UP_EVT;

typedef enum {
    DL_TIMER_SEC_COMP_UP_ACT_SEL_DISABLE = GPTIMER_CCACT_01_CC2UACT_DISABLED,
    DL_TIMER_SEC_COMP_UP_ACT_SEL_HIGH = GPTIMER_CCACT_01_CC2UACT_CCP_HIGH,
    DL_TIMER_SEC_COMP_UP_ACT_SEL_LOW = GPTIMER_CCACT_01_CC2UACT_CCP_LOW,
    DL_TIMER_SEC_COMP_UP_ACT_SEL_TOGGLE = GPTIMER_CCACT_01_CC2UACT_CCP_TOGGLE,
} DL_TIMER_SEC_COMP_UP_ACT_SEL;

typedef enum {
    DL_TIMER_SEC_COMP_DOWN_ACT_SEL_DISABLE = GPTIMER_CCACT_01_CC2DACT_DISABLED,
    DL_TIMER_SEC_COMP_DOWN_ACT_SEL_HIGH = GPTIMER_CCACT_01_CC2DACT_CCP_HIGH,
    DL_TIMER_SEC_COMP_DOWN_ACT_SEL_LOW = GPTIMER_CCACT_01_CC2DACT_CCP_LOW,
    DL_TIMER_SEC_COMP_DOWN_ACT_SEL_TOGGLE =
        GPTIMER_CCACT_01_CC2DACT_CCP_TOGGLE,
} DL_TIMER_SEC_COMP_DOWN_ACT_SEL;

typedef enum {
    DL_TIMER_SUPP_COMP_EVT_RC_DISABLED = (GPTIMER_CCCTL_01_SCERCNEZ_DISABLED),
    DL_TIMER_SUPP_COMP_EVT_RC_ENABLED = (GPTIMER_CCCTL_01_SCERCNEZ_ENABLED),
} DL_TIMER_SUPP_COMP_EVT_RC;

typedef enum {
    DL_TIMER_FORCE_OUT_DISABLED = (GPTIMER_CCACT_01_SWFRCACT_DISABLED),
    DL_TIMER_FORCE_OUT_HIGH = (GPTIMER_CCACT_01_SWFRCACT_CCP_HIGH),
    DL_TIMER_FORCE_OUT_LOW = (GPTIMER_CCACT_01_SWFRCACT_CCP_LOW),

} DL_TIMER_FORCE_OUT;

typedef enum {
    DL_TIMER_FORCE_CMPL_OUT_DISABLED =
        (GPTIMER_CCACT_01_SWFRCACT_CMPL_DISABLED),
    DL_TIMER_FORCE_CMPL_OUT_HIGH = (GPTIMER_CCACT_01_SWFRCACT_CMPL_CCP_HIGH),
    DL_TIMER_FORCE_CMPL_OUT_LOW = (GPTIMER_CCACT_01_SWFRCACT_CMPL_CCP_LOW),

} DL_TIMER_FORCE_CMPL_OUT;

typedef enum {
    DL_TIMER_CORE_HALT_IMMEDIATE =
        (GPTIMER_PDBGCTL_FREE_STOP | GPTIMER_PDBGCTL_SOFT_IMMEDIATE),
    DL_TIMER_CORE_HALT_DELAYED =
        (GPTIMER_PDBGCTL_FREE_STOP | GPTIMER_PDBGCTL_SOFT_DELAYED),
    DL_TIMER_CORE_HALT_FREE_RUN =
        (GPTIMER_PDBGCTL_FREE_RUN | GPTIMER_PDBGCTL_SOFT_DELAYED),
} DL_TIMER_CORE_HALT;

typedef struct {
    DL_TIMER_CLOCK clockSel;
    DL_TIMER_CLOCK_DIVIDE divideRatio;
    uint8_t prescale;
} DL_Timer_ClockConfig;

typedef struct {
    DL_TIMER_TIMER_MODE timerMode;
    uint32_t period;
    DL_TIMER startTimer;
    DL_TIMER_INTERM_INT genIntermInt;
    uint16_t counterVal;
} DL_Timer_TimerConfig;

typedef struct {
    DL_TIMER_CAPTURE_MODE captureMode;
    uint32_t period;
    DL_TIMER startTimer;
    DL_TIMER_CAPTURE_EDGE_DETECTION_MODE edgeCaptMode;
    DL_TIMER_INPUT_CHAN inputChan;
    uint32_t inputInvMode;
} DL_Timer_CaptureConfig;

typedef struct {
    DL_TIMER_CAPTURE_MODE captureMode;
    uint16_t period;
    DL_TIMER startTimer;
} DL_Timer_CaptureTriggerConfig;

typedef struct {
    DL_TIMER_CAPTURE_COMBINED_MODE captureMode;
    uint32_t period;
    DL_TIMER startTimer;
    DL_TIMER_INPUT_CHAN inputChan;
    uint32_t inputInvMode;
} DL_Timer_CaptureCombinedConfig;

typedef struct {
    DL_TIMER_COMPARE_MODE compareMode;
    uint16_t count;
    DL_TIMER_COMPARE_EDGE_DETECTION_MODE edgeDetectMode;
    DL_TIMER_INPUT_CHAN inputChan;
    uint32_t inputInvMode;
    DL_TIMER startTimer;
} DL_Timer_CompareConfig;

typedef struct {
    DL_TIMER_COMPARE_MODE compareMode;
    uint16_t count;
    DL_TIMER_COMPARE_EDGE_DETECTION_MODE edgeDetectMode;
    DL_TIMER startTimer;
} DL_Timer_CompareTriggerConfig;

typedef struct {
    uint32_t period;
    DL_TIMER_PWM_MODE pwmMode;
    DL_TIMER startTimer;
} DL_Timer_PWMConfig;

typedef struct {
    uint32_t sub0PortConf;
    uint32_t sub1PortConf;
    uint32_t pub0PortConf;
    uint32_t pub1PortConf;
    uint32_t clkDivConf;
    uint32_t clockPscConf;
    uint32_t clkSelConf;
    uint32_t countClkConf;
    uint32_t intEvnt0Conf;
    uint32_t intEvnt1Conf;
    uint32_t intEvnt2Conf;
    uint32_t ccpDirConf;
    uint32_t outDisConf;
    uint32_t crossTrigCtl;
    uint32_t tSelConf;
    uint32_t crossTrigConf;
    uint32_t cntVal;
    uint32_t cntCtlConf;
    uint32_t loadVal;
    uint32_t cc0Val;
    uint32_t cc1Val;
    uint32_t cc0Ctl;
    uint32_t cc1Ctl;
    uint32_t cc0OutCtl;
    uint32_t cc1OutCtl;
    uint32_t cc0ActCtl;
    uint32_t cc1ActCtl;
    uint32_t in0FiltCtl;
    uint32_t in1FiltCtl;
    bool backupRdy;
} DL_Timer_backupConfig;

typedef enum {
    DL_TIMER_QEI_MODE_2_INPUT =
        (GPTIMER_CTRCTL_CLC_QEI_2INP | GPTIMER_CTRCTL_CAC_QEI_2INP |
            GPTIMER_CTRCTL_CZC_QEI_2INP),
    DL_TIMER_QEI_MODE_3_INPUT =
        (GPTIMER_CTRCTL_CLC_QEI_3INP | GPTIMER_CTRCTL_CAC_QEI_3INP |
            GPTIMER_CTRCTL_CZC_QEI_3INP),
} DL_TIMER_QEI_MODE;

typedef enum {
    DL_TIMER_QEI_DIR_DOWN = GPTIMER_QDIR_DIR_DOWN,
    DL_TIMER_QEI_DIR_UP = GPTIMER_QDIR_DIR_UP,
} DL_TIMER_QEI_DIRECTION;

__STATIC_INLINE void DL_Timer_enablePower(GPTIMER_Regs *gptimer)
{
    gptimer->GPRCM.PWREN =
        (GPTIMER_PWREN_KEY_UNLOCK_W | GPTIMER_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_Timer_disablePower(GPTIMER_Regs *gptimer)
{
    gptimer->GPRCM.PWREN =
        (GPTIMER_PWREN_KEY_UNLOCK_W | GPTIMER_PWREN_ENABLE_DISABLE);
}

__STATIC_INLINE bool DL_Timer_isPowerEnabled(GPTIMER_Regs *gptimer)
{
    return ((gptimer->GPRCM.PWREN & GPTIMER_PWREN_ENABLE_MASK) ==
            GPTIMER_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_Timer_reset(GPTIMER_Regs *gptimer)
{
    gptimer->GPRCM.RSTCTL =
        (GPTIMER_RSTCTL_KEY_UNLOCK_W | GPTIMER_RSTCTL_RESETSTKYCLR_CLR |
            GPTIMER_RSTCTL_RESETASSERT_ASSERT);
}

__STATIC_INLINE bool DL_Timer_isReset(GPTIMER_Regs *gptimer)
{
    return ((gptimer->GPRCM.STAT & GPTIMER_STAT_RESETSTKY_MASK) ==
            GPTIMER_STAT_RESETSTKY_RESET);
}

__STATIC_INLINE void DL_Timer_setCCPDirection(
    GPTIMER_Regs *gptimer, uint32_t ccpConfig)
{
    gptimer->COMMONREGS.CCPD = (ccpConfig);
}

__STATIC_INLINE uint32_t DL_Timer_getCCPDirection(GPTIMER_Regs *gptimer)
{
    return (gptimer->COMMONREGS.CCPD);
}

__STATIC_INLINE void DL_Timer_setCCPOutputDisabled(GPTIMER_Regs *gptimer,
    DL_TIMER_CCP_DIS_OUT ccp0Config, DL_TIMER_CCP_DIS_OUT ccp1Config)
{
    DL_Common_updateReg(&gptimer->COMMONREGS.ODIS,
        (((uint32_t) ccp0Config) |
            ((uint32_t) ccp1Config << GPTIMER_ODIS_C0CCP1_OFS)),
        (GPTIMER_ODIS_C0CCP0_MASK | GPTIMER_ODIS_C0CCP1_MASK));
}

__STATIC_INLINE void DL_Timer_setCCPOutputDisabledAdv(
    GPTIMER_Regs *gptimer, uint32_t ccpOdisConfig)
{
    DL_Common_updateReg(&gptimer->COMMONREGS.ODIS, (ccpOdisConfig),
        (GPTIMER_ODIS_C0CCP0_MASK | GPTIMER_ODIS_C0CCP1_MASK |
            GPTIMER_ODIS_C0CCP2_MASK | GPTIMER_ODIS_C0CCP3_MASK));
}

void DL_Timer_setClockConfig(
    GPTIMER_Regs *gptimer, DL_Timer_ClockConfig *config);

void DL_Timer_getClockConfig(
    GPTIMER_Regs *gptimer, DL_Timer_ClockConfig *config);

__STATIC_INLINE void DL_Timer_enableClock(GPTIMER_Regs *gptimer)
{
    gptimer->COMMONREGS.CCLKCTL = (GPTIMER_CCLKCTL_CLKEN_ENABLED);
}

__STATIC_INLINE void DL_Timer_disableClock(GPTIMER_Regs *gptimer)
{
    gptimer->COMMONREGS.CCLKCTL = (GPTIMER_CCLKCTL_CLKEN_DISABLED);
}

__STATIC_INLINE bool DL_Timer_isClockEnabled(GPTIMER_Regs *gptimer)
{
    return ((gptimer->COMMONREGS.CCLKCTL & GPTIMER_CCLKCTL_CLKEN_MASK) ==
            GPTIMER_CCLKCTL_CLKEN_ENABLED);
}

__STATIC_INLINE void DL_Timer_configCrossTrigger(GPTIMER_Regs *gptimer,
    DL_TIMER_CROSS_TRIG_SRC ctSource,
    DL_TIMER_CROSS_TRIGGER_INPUT enInTrigCond,
    DL_TIMER_CROSS_TRIGGER_MODE enCrossTrig)
{
    gptimer->COMMONREGS.CTTRIGCTL =
        (uint32_t)((uint32_t) ctSource | (uint32_t) enInTrigCond |
                   (uint32_t) enCrossTrig);
}

__STATIC_INLINE void DL_Timer_configCrossTriggerSrc(
    GPTIMER_Regs *gptimer, DL_TIMER_CROSS_TRIG_SRC ctSource)
{
    DL_Common_updateReg(&gptimer->COMMONREGS.CTTRIGCTL, (uint32_t) ctSource,
        GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_MASK);
}

__STATIC_INLINE void DL_Timer_configCrossTriggerInputCond(
    GPTIMER_Regs *gptimer, DL_TIMER_CROSS_TRIGGER_INPUT enInTrigCond)
{
    DL_Common_updateReg(&gptimer->COMMONREGS.CTTRIGCTL,
        (uint32_t) enInTrigCond, GPTIMER_CTTRIGCTL_EVTCTEN_MASK);
}

__STATIC_INLINE void DL_Timer_configCrossTriggerEnable(
    GPTIMER_Regs *gptimer, DL_TIMER_CROSS_TRIGGER_MODE enCrossTrig)
{
    DL_Common_updateReg(&gptimer->COMMONREGS.CTTRIGCTL, (uint32_t) enCrossTrig,
        GPTIMER_CTTRIGCTL_CTEN_MASK);
}

__STATIC_INLINE uint32_t DL_Timer_getCrossTriggerConfig(GPTIMER_Regs *gptimer)
{
    return (gptimer->COMMONREGS.CTTRIGCTL);
}

__STATIC_INLINE DL_TIMER_CROSS_TRIG_SRC DL_Timer_getCrossTriggerSrc(
    GPTIMER_Regs *gptimer)
{
    uint32_t ctSource =
        gptimer->COMMONREGS.CTTRIGCTL & GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_MASK;

    return (DL_TIMER_CROSS_TRIG_SRC)(ctSource);
}

__STATIC_INLINE DL_TIMER_CROSS_TRIGGER_INPUT DL_Timer_getCrossTriggerInputCond(
    GPTIMER_Regs *gptimer)
{
    uint32_t triggerCondition =
        gptimer->COMMONREGS.CTTRIGCTL & GPTIMER_CTTRIGCTL_EVTCTEN_MASK;

    return (DL_TIMER_CROSS_TRIGGER_INPUT)(triggerCondition);
}

__STATIC_INLINE DL_TIMER_CROSS_TRIGGER_MODE DL_Timer_getCrossTriggerEnable(
    GPTIMER_Regs *gptimer)
{
    uint32_t mode =
        gptimer->COMMONREGS.CTTRIGCTL & GPTIMER_CTTRIGCTL_CTEN_MASK;

    return (DL_TIMER_CROSS_TRIGGER_MODE)(mode);
}

__STATIC_INLINE void DL_Timer_generateCrossTrigger(GPTIMER_Regs *gptimer)
{
    gptimer->COMMONREGS.CTTRIG = GPTIMER_CTTRIG_TRIG_GENERATE;
}

__STATIC_INLINE void DL_Timer_enableShadowFeatures(GPTIMER_Regs *gptimer)
{
    gptimer->COMMONREGS.GCTL |= GPTIMER_GCTL_SHDWLDEN_ENABLE;
}

__STATIC_INLINE void DL_Timer_disableShadowFeatures(GPTIMER_Regs *gptimer)
{
    gptimer->COMMONREGS.GCTL &= ~(GPTIMER_GCTL_SHDWLDEN_ENABLE);
}

__STATIC_INLINE void DL_Timer_setLoadValue(
    GPTIMER_Regs *gptimer, uint32_t value)
{
    gptimer->COUNTERREGS.LOAD = value;
}

__STATIC_INLINE uint32_t DL_Timer_getLoadValue(GPTIMER_Regs *gptimer)
{
    return (gptimer->COUNTERREGS.LOAD & GPTIMER_LOAD_LD_MAXIMUM);
}

__STATIC_INLINE uint32_t DL_Timer_getTimerCount(GPTIMER_Regs *gptimer)
{
    return (gptimer->COUNTERREGS.CTR & GPTIMER_CTR_CCTR_MASK);
}

__STATIC_INLINE void DL_Timer_setTimerCount(
    GPTIMER_Regs *gptimer, uint32_t value)
{
    gptimer->COUNTERREGS.CTR = value;
}

__STATIC_INLINE void DL_Timer_enableLZEventSuppression(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.CTRCTL |= (GPTIMER_CTRCTL_SLZERCNEZ_ENABLED);
}

__STATIC_INLINE void DL_Timer_disableLZEventSuppression(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.CTRCTL &= ~(GPTIMER_CTRCTL_SLZERCNEZ_ENABLED);
}

__STATIC_INLINE bool DL_Timer_isLZEventSuppressionEnabled(
    GPTIMER_Regs *gptimer)
{
    return (GPTIMER_CTRCTL_SLZERCNEZ_ENABLED ==
            (gptimer->COUNTERREGS.CTRCTL & GPTIMER_CTRCTL_SLZERCNEZ_MASK));
}

__STATIC_INLINE void DL_Timer_setDebugReleaseBehavior(
    GPTIMER_Regs *gptimer, DL_TIMER_DEBUG_RES debResB)
{
    DL_Common_updateReg(&gptimer->COUNTERREGS.CTRCTL, (uint32_t) debResB,
        GPTIMER_CTRCTL_DRB_MASK);
}

__STATIC_INLINE DL_TIMER_DEBUG_RES DL_Timer_getDebugReleaseBehavior(
    GPTIMER_Regs *gptimer)
{
    uint32_t debResB = gptimer->COUNTERREGS.CTRCTL & GPTIMER_CTRCTL_DRB_MASK;

    return ((DL_TIMER_DEBUG_RES)(debResB));
}

__STATIC_INLINE void DL_Timer_setCounterControl(GPTIMER_Regs *gptimer,
    DL_TIMER_CZC zeroCtl, DL_TIMER_CAC advCtl, DL_TIMER_CLC loadCtl)
{
    DL_Common_updateReg(&gptimer->COUNTERREGS.CTRCTL,
        ((uint32_t) zeroCtl | (uint32_t) advCtl | (uint32_t) loadCtl),
        (GPTIMER_CTRCTL_CZC_MASK | GPTIMER_CTRCTL_CAC_MASK |
            GPTIMER_CTRCTL_CLC_MASK));
}

__STATIC_INLINE DL_TIMER_CZC DL_Timer_getCounterZeroControl(
    GPTIMER_Regs *gptimer)
{
    uint32_t zeroCtl = gptimer->COUNTERREGS.CTRCTL & GPTIMER_CTRCTL_CZC_MASK;

    return ((DL_TIMER_CZC)(zeroCtl));
}

__STATIC_INLINE DL_TIMER_CAC DL_Timer_getCounterAdvanceControl(
    GPTIMER_Regs *gptimer)
{
    uint32_t advCtl = gptimer->COUNTERREGS.CTRCTL & GPTIMER_CTRCTL_CAC_MASK;

    return ((DL_TIMER_CAC)(advCtl));
}

__STATIC_INLINE DL_TIMER_CLC DL_Timer_getCounterLoadControl(
    GPTIMER_Regs *gptimer)
{
    uint32_t loadCtl = gptimer->COUNTERREGS.CTRCTL & GPTIMER_CTRCTL_CLC_MASK;

    return ((DL_TIMER_CLC)(loadCtl));
}

__STATIC_INLINE void DL_Timer_setCounterMode(
    GPTIMER_Regs *gptimer, DL_TIMER_COUNT_MODE countMode)
{
    DL_Common_updateReg(&gptimer->COUNTERREGS.CTRCTL, ((uint32_t) countMode),
        (GPTIMER_CTRCTL_CM_MASK));
}

__STATIC_INLINE DL_TIMER_COUNT_MODE DL_Timer_getCounterMode(
    GPTIMER_Regs *gptimer)
{
    uint32_t cmMode = (gptimer->COUNTERREGS.CTRCTL & GPTIMER_CTRCTL_CM_MASK);
    return ((DL_TIMER_COUNT_MODE) cmMode);
}

__STATIC_INLINE void DL_Timer_setCounterValueAfterEnable(
    GPTIMER_Regs *gptimer, DL_TIMER_COUNT_AFTER_EN cvae)
{
    DL_Common_updateReg(&gptimer->COUNTERREGS.CTRCTL, (uint32_t) cvae,
        GPTIMER_CTRCTL_CVAE_MASK);
}

__STATIC_INLINE DL_TIMER_COUNT_AFTER_EN DL_Timer_getCounterValueAfterEnable(
    GPTIMER_Regs *gptimer)
{
    uint32_t cvae = gptimer->COUNTERREGS.CTRCTL & GPTIMER_CTRCTL_CVAE_MASK;

    return ((DL_TIMER_COUNT_AFTER_EN)(cvae));
}

__STATIC_INLINE void DL_Timer_setCounterRepeatMode(
    GPTIMER_Regs *gptimer, DL_TIMER_REPEAT_MODE repeatMode)
{
    DL_Common_updateReg(&gptimer->COUNTERREGS.CTRCTL, (uint32_t) repeatMode,
        GPTIMER_CTRCTL_REPEAT_MASK);
}

__STATIC_INLINE DL_TIMER_REPEAT_MODE DL_Timer_getCounterRepeatMode(
    GPTIMER_Regs *gptimer)
{
    uint32_t repeatMode =
        gptimer->COUNTERREGS.CTRCTL & GPTIMER_CTRCTL_REPEAT_MASK;

    return ((DL_TIMER_REPEAT_MODE)(repeatMode));
}

void DL_Timer_initTimerMode(
    GPTIMER_Regs *gptimer, DL_Timer_TimerConfig *config);

void DL_Timer_initCaptureMode(
    GPTIMER_Regs *gptimer, DL_Timer_CaptureConfig *config);

void DL_Timer_initCaptureTriggerMode(
    GPTIMER_Regs *gptimer, DL_Timer_CaptureTriggerConfig *config);

void DL_Timer_initCaptureCombinedMode(
    GPTIMER_Regs *gptimer, DL_Timer_CaptureCombinedConfig *config);

void DL_Timer_initCompareMode(
    GPTIMER_Regs *gptimer, DL_Timer_CompareConfig *config);

void DL_Timer_initCompareTriggerMode(
    GPTIMER_Regs *gptimer, DL_Timer_CompareTriggerConfig *config);

void DL_Timer_initPWMMode(GPTIMER_Regs *gptimer, DL_Timer_PWMConfig *config);

__STATIC_INLINE void DL_Timer_resetCounterMode(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.CTRCTL = GPTIMER_CTRCTL_EN_DISABLED;
}

void DL_Timer_setCaptureCompareValue(
    GPTIMER_Regs *gptimer, uint32_t value, DL_TIMER_CC_INDEX ccIndex);

uint32_t DL_Timer_getCaptureCompareValue(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_setCaptureCompareCtl(GPTIMER_Regs *gptimer, uint32_t ccMode,
    uint32_t ccCondMask, DL_TIMER_CC_INDEX ccIndex);

uint32_t DL_Timer_getCaptureCompareCtl(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_setSecondCompSrcDn(GPTIMER_Regs *gptimer,
    DL_TIMER_SEC_COMP_DOWN_EVT secCompDn, DL_TIMER_CC_INDEX ccIndex);

DL_TIMER_SEC_COMP_DOWN_EVT DL_Timer_getSecondCompSrcDn(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_setSecondCompSrcUp(GPTIMER_Regs *gptimer,
    DL_TIMER_SEC_COMP_UP_EVT secCompUp, DL_TIMER_CC_INDEX ccIndex);

DL_TIMER_SEC_COMP_UP_EVT DL_Timer_getSecondCompSrcUp(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_enableSuppressionOfCompEvent(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_disableSuppressionOfCompEvent(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_setCaptCompUpdateMethod(GPTIMER_Regs *gptimer,
    DL_TIMER_CC_UPDATE_METHOD ccUpdtMode, DL_TIMER_CC_INDEX ccIndex);

DL_TIMER_CC_UPDATE_METHOD DL_Timer_getCaptCompUpdateMethod(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_setCaptureCompareOutCtl(GPTIMER_Regs *gptimer, uint32_t ccpIV,
    uint32_t ccpOInv, uint32_t ccpO, DL_TIMER_CC_INDEX ccIndex);

uint32_t DL_Timer_getCaptureCompareOutCtl(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_setCaptureCompareAction(
    GPTIMER_Regs *gptimer, uint32_t actionsMask, DL_TIMER_CC_INDEX ccIndex);

uint32_t DL_Timer_getCaptureCompareAction(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_setSecondCompActionDn(GPTIMER_Regs *gptimer,
    DL_TIMER_SEC_COMP_DOWN_ACT_SEL secCompDnAct, DL_TIMER_CC_INDEX ccIndex);
DL_TIMER_SEC_COMP_DOWN_ACT_SEL DL_Timer_getSecondCompActionDn(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_setSecondCompActionUp(GPTIMER_Regs *gptimer,
    DL_TIMER_SEC_COMP_UP_ACT_SEL secCompUpAct, DL_TIMER_CC_INDEX ccIndex);

DL_TIMER_SEC_COMP_UP_ACT_SEL DL_Timer_getSecondCompActionUp(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_overrideCCPOut(GPTIMER_Regs *gptimer, DL_TIMER_FORCE_OUT out,
    DL_TIMER_FORCE_CMPL_OUT outComp, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_setCaptureCompareInput(GPTIMER_Regs *gptimer, uint32_t inv,
    uint32_t isel, DL_TIMER_CC_INDEX ccIndex);

uint32_t DL_Timer_getCaptureCompareInput(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_setCaptureCompareInputFilter(GPTIMER_Regs *gptimer, uint32_t cpv,
    uint32_t fp, DL_TIMER_CC_INDEX ccIndex);

uint32_t DL_Timer_getCaptureCompareInputFilter(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_enableCaptureCompareInputFilter(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

void DL_Timer_disableCaptureCompareInputFilter(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

bool DL_Timer_isCaptureCompareInputFilterEnabled(
    GPTIMER_Regs *gptimer, DL_TIMER_CC_INDEX ccIndex);

__STATIC_INLINE void DL_Timer_setDeadBand(GPTIMER_Regs *gptimer,
    uint16_t falldelay, uint16_t risedelay, uint32_t mode)
{
    gptimer->COUNTERREGS.DBCTL =
        (((uint32_t) falldelay << GPTIMER_DBCTL_FALLDELAY_OFS) |
            (uint32_t) risedelay | mode);
}

__STATIC_INLINE uint16_t DL_Timer_getDeadBandFallDelay(GPTIMER_Regs *gptimer)
{
    uint32_t temp =
        (gptimer->COUNTERREGS.DBCTL & GPTIMER_DBCTL_FALLDELAY_MASK) >>
        GPTIMER_DBCTL_FALLDELAY_OFS;

    return ((uint16_t) temp);
}

__STATIC_INLINE uint16_t DL_Timer_getDeadBandRiseDelay(GPTIMER_Regs *gptimer)
{
    return (uint16_t)(
        (gptimer->COUNTERREGS.DBCTL) & (GPTIMER_DBCTL_RISEDELAY_MASK));
}

__STATIC_INLINE void DL_Timer_setExternalTriggerEvent(
    GPTIMER_Regs *gptimer, DL_TIMER_EXT_TRIG_SEL trigSel)
{
    DL_Common_updateReg(&gptimer->COUNTERREGS.TSEL, (uint32_t) trigSel,
        GPTIMER_TSEL_ETSEL_MASK);
}

__STATIC_INLINE DL_TIMER_EXT_TRIG_SEL DL_Timer_getExternalTriggerEvent(
    GPTIMER_Regs *gptimer)
{
    uint32_t trigSel = gptimer->COUNTERREGS.TSEL & GPTIMER_TSEL_ETSEL_MASK;

    return (DL_TIMER_EXT_TRIG_SEL)(trigSel);
}

__STATIC_INLINE void DL_Timer_enableExternalTrigger(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.TSEL |= (GPTIMER_TSEL_TE_ENABLED);
}

__STATIC_INLINE void DL_Timer_disableExternalTrigger(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.TSEL &= ~(GPTIMER_TSEL_TE_ENABLED);
}

__STATIC_INLINE bool DL_Timer_isExternalTriggerEnabled(GPTIMER_Regs *gptimer)
{
    return ((gptimer->COUNTERREGS.TSEL & GPTIMER_TSEL_TE_MASK) ==
            GPTIMER_TSEL_TE_ENABLED);
}

__STATIC_INLINE void DL_Timer_setRepeatCounter(
    GPTIMER_Regs *gptimer, uint8_t repeatCount)
{
    gptimer->COUNTERREGS.RCLD = (repeatCount);
}

__STATIC_INLINE uint8_t DL_Timer_getRepeatCounter(GPTIMER_Regs *gptimer)
{
    return ((uint8_t)(gptimer->COUNTERREGS.RC & GPTIMER_RC_RC_MASK));
}

__STATIC_INLINE void DL_Timer_enablePhaseLoad(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.CTRCTL |= (GPTIMER_CTRCTL_PLEN_ENABLED);
}

__STATIC_INLINE void DL_Timer_disablePhaseLoad(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.CTRCTL &= ~(GPTIMER_CTRCTL_PLEN_ENABLED);
}

__STATIC_INLINE bool DL_Timer_isPhaseLoadEnabled(GPTIMER_Regs *gptimer)
{
    return (GPTIMER_CTRCTL_PLEN_ENABLED ==
            (gptimer->COUNTERREGS.CTRCTL & GPTIMER_CTRCTL_PLEN_MASK));
}

__STATIC_INLINE void DL_Timer_setPhaseLoadValue(
    GPTIMER_Regs *gptimer, uint16_t value)
{
    gptimer->COUNTERREGS.PL = (value);
}

__STATIC_INLINE uint16_t DL_Timer_getPhaseLoadValue(GPTIMER_Regs *gptimer)
{
    return ((uint16_t)(gptimer->COUNTERREGS.PL & GPTIMER_PL_PHASE_MASK));
}

__STATIC_INLINE void DL_Timer_startCounter(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.CTRCTL |= (GPTIMER_CTRCTL_EN_ENABLED);
}

__STATIC_INLINE void DL_Timer_stopCounter(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.CTRCTL &= ~(GPTIMER_CTRCTL_EN_ENABLED);
}

__STATIC_INLINE bool DL_Timer_isRunning(GPTIMER_Regs *gptimer)
{
    return ((gptimer->COUNTERREGS.CTRCTL & GPTIMER_CTRCTL_EN_MASK) ==
            GPTIMER_CTRCTL_EN_ENABLED);
}

__STATIC_INLINE void DL_Timer_configQEI(GPTIMER_Regs *gptimer,
    DL_TIMER_QEI_MODE mode, uint32_t invert, DL_TIMER_CC_INDEX ccIndex)
{
    gptimer->COUNTERREGS.CCCTL_01[ccIndex] =
        GPTIMER_CCCTL_01_CCOND_CC_TRIG_RISE | GPTIMER_CCCTL_01_COC_CAPTURE;
    gptimer->COUNTERREGS.IFCTL_01[ccIndex] =
        GPTIMER_IFCTL_01_ISEL_CCPX_INPUT | invert;
    gptimer->COUNTERREGS.CTRCTL =
        (uint32_t) mode | GPTIMER_CTRCTL_CVAE_NOCHANGE |
        GPTIMER_CTRCTL_CM_UP_DOWN | GPTIMER_CTRCTL_REPEAT_REPEAT_1 |
        GPTIMER_CTRCTL_EN_ENABLED;
}

__STATIC_INLINE DL_TIMER_QEI_DIRECTION DL_Timer_getQEIDirection(
    GPTIMER_Regs *gptimer)
{
    uint32_t qeiDirection = gptimer->COUNTERREGS.QDIR & GPTIMER_QDIR_DIR_MASK;

    return (DL_TIMER_QEI_DIRECTION)(qeiDirection);
}

__STATIC_INLINE void DL_Timer_setFaultConfig(
    GPTIMER_Regs *gptimer, uint32_t faultConfMask)
{
    DL_Common_updateReg(&gptimer->COUNTERREGS.FCTL, faultConfMask,
        (GPTIMER_FCTL_TFIM_MASK | GPTIMER_FCTL_FL_MASK | GPTIMER_FCTL_FI_MASK |
            GPTIMER_FCTL_FIEN_MASK));
}

__STATIC_INLINE uint32_t DL_Timer_getFaultConfig(GPTIMER_Regs *gptimer)
{
    return (gptimer->COUNTERREGS.FCTL &
            (GPTIMER_FCTL_FIEN_MASK | GPTIMER_FCTL_FI_MASK |
                GPTIMER_FCTL_FL_MASK | GPTIMER_FCTL_TFIM_MASK));
}

__STATIC_INLINE void DL_Timer_enableFaultInput(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.FCTL |= (GPTIMER_FCTL_FIEN_ENABLED);
}

__STATIC_INLINE void DL_Timer_disableFaultInput(GPTIMER_Regs *gptimer)
{
    gptimer->COUNTERREGS.FCTL &= ~(GPTIMER_FCTL_FIEN_ENABLED);
}

__STATIC_INLINE bool DL_Timer_isFaultInputEnabled(GPTIMER_Regs *gptimer)
{
    return (GPTIMER_FCTL_FIEN_ENABLED ==
            (gptimer->COUNTERREGS.FCTL & GPTIMER_FCTL_FIEN_MASK));
}

__STATIC_INLINE void DL_Timer_enableClockFaultDetection(GPTIMER_Regs *gptimer)
{
    gptimer->COMMONREGS.FSCTL |= (GPTIMER_FSCTL_FCEN_DISABLE);
}

__STATIC_INLINE void DL_Timer_disableClockFaultDetection(GPTIMER_Regs *gptimer)
{
    gptimer->COMMONREGS.FSCTL &= ~(GPTIMER_FSCTL_FCEN_DISABLE);
}

__STATIC_INLINE bool DL_Timer_isClockFaultDetectionEnabled(
    GPTIMER_Regs *gptimer)
{
    return (GPTIMER_FSCTL_FCEN_ENABLE ==
            (gptimer->COMMONREGS.FSCTL & GPTIMER_FSCTL_FCEN_MASK));
}

void DL_Timer_setFaultSourceConfig(GPTIMER_Regs *gptimer, uint32_t source);

uint32_t DL_Timer_getFaultSourceConfig(GPTIMER_Regs *gptimer);

__STATIC_INLINE void DL_Timer_setFaultInputFilterConfig(
    GPTIMER_Regs *gptimer, uint32_t filten, uint32_t cpv, uint32_t fp)
{
    gptimer->COUNTERREGS.FIFCTL = (filten | cpv | fp);
}

__STATIC_INLINE uint32_t DL_Timer_getFaultInputFilterConfig(
    GPTIMER_Regs *gptimer)
{
    return (gptimer->COUNTERREGS.FIFCTL);
}

__STATIC_INLINE void DL_Timer_configFaultOutputAction(GPTIMER_Regs *gptimer,
    DL_TIMER_FAULT_ENTRY_CCP faultEntry, DL_TIMER_FAULT_EXIT_CCP faultExit,
    DL_TIMER_CC_INDEX ccIndex)
{
    DL_Common_updateReg(&gptimer->COUNTERREGS.CCACT_01[ccIndex],
        ((uint32_t) faultEntry | (uint32_t) faultExit),
        (GPTIMER_CCACT_01_FEXACT_MASK | GPTIMER_CCACT_01_FENACT_MASK));
}

__STATIC_INLINE void DL_Timer_configFaultCounter(GPTIMER_Regs *gptimer,
    DL_TIMER_FAULT_ENTRY_CTR faultEntry, DL_TIMER_FAULT_EXIT_CTR faultExit)
{
    DL_Common_updateReg(&gptimer->COUNTERREGS.CTRCTL,
        ((uint32_t) faultEntry | (uint32_t) faultExit),
        (GPTIMER_CTRCTL_FRB_MASK | GPTIMER_CTRCTL_FB_MASK));
}

__STATIC_INLINE void DL_Timer_enableInterrupt(
    GPTIMER_Regs *gptimer, uint32_t interruptMask)
{
    gptimer->CPU_INT.IMASK |= interruptMask;
}

__STATIC_INLINE void DL_Timer_disableInterrupt(
    GPTIMER_Regs *gptimer, uint32_t interruptMask)
{
    gptimer->CPU_INT.IMASK &= ~(interruptMask);
}

__STATIC_INLINE uint32_t DL_Timer_getEnabledInterrupts(
    GPTIMER_Regs *gptimer, uint32_t interruptMask)
{
    return (gptimer->CPU_INT.IMASK & interruptMask);
}

__STATIC_INLINE uint32_t DL_Timer_getEnabledInterruptStatus(
    GPTIMER_Regs *gptimer, uint32_t interruptMask)
{
    return (gptimer->CPU_INT.MIS & interruptMask);
}

__STATIC_INLINE uint32_t DL_Timer_getRawInterruptStatus(
    GPTIMER_Regs *gptimer, uint32_t interruptMask)
{
    return (gptimer->CPU_INT.RIS & interruptMask);
}

__STATIC_INLINE DL_TIMER_IIDX DL_Timer_getPendingInterrupt(
    GPTIMER_Regs *gptimer)
{
    return ((DL_TIMER_IIDX) gptimer->CPU_INT.IIDX);
}

__STATIC_INLINE void DL_Timer_clearInterruptStatus(
    GPTIMER_Regs *gptimer, uint32_t interruptMask)
{
    gptimer->CPU_INT.ICLR = interruptMask;
}

__STATIC_INLINE void DL_Timer_setPublisherChanID(
    GPTIMER_Regs *gptimer, DL_TIMER_PUBLISHER_INDEX index, uint8_t chanID)
{
    volatile uint32_t *pReg = &gptimer->FPUB_0;

    *(pReg + (uint32_t) index) = (chanID & GPTIMER_FPUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_Timer_getPublisherChanID(
    GPTIMER_Regs *gptimer, DL_TIMER_PUBLISHER_INDEX index)
{
    volatile uint32_t *pReg = &gptimer->FPUB_0;

    return (
        (uint8_t)(*(pReg + (uint32_t) index) & GPTIMER_FPUB_0_CHANID_MASK));
}

__STATIC_INLINE void DL_Timer_setSubscriberChanID(
    GPTIMER_Regs *gptimer, DL_TIMER_SUBSCRIBER_INDEX index, uint8_t chanID)
{
    volatile uint32_t *pReg = &gptimer->FSUB_0;

    *(pReg + (uint32_t) index) = (chanID & GPTIMER_FSUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_Timer_getSubscriberChanID(
    GPTIMER_Regs *gptimer, DL_TIMER_SUBSCRIBER_INDEX index)
{
    volatile uint32_t *pReg = &gptimer->FSUB_0;

    return (
        (uint8_t)(*(pReg + (uint32_t) index) & GPTIMER_FSUB_0_CHANID_MASK));
}

__STATIC_INLINE void DL_Timer_enableEvent(
    GPTIMER_Regs *gptimer, DL_TIMER_EVENT_ROUTE index, uint32_t eventMask)
{
    volatile uint32_t *pReg = (volatile uint32_t *) &gptimer->GEN_EVENT0.IMASK;

    *(pReg + (uint32_t) index) |= (eventMask);
}

__STATIC_INLINE void DL_Timer_disableEvent(
    GPTIMER_Regs *gptimer, DL_TIMER_EVENT_ROUTE index, uint32_t eventMask)
{
    volatile uint32_t *pReg = (volatile uint32_t *) &gptimer->GEN_EVENT0.IMASK;

    *(pReg + (uint32_t) index) &= ~(eventMask);
}

__STATIC_INLINE uint32_t DL_Timer_getEnabledEvents(
    GPTIMER_Regs *gptimer, DL_TIMER_EVENT_ROUTE index, uint32_t eventMask)
{
    volatile uint32_t *pReg = (volatile uint32_t *) &gptimer->GEN_EVENT0.IMASK;

    return ((*(pReg + (uint32_t) index) & eventMask));
}

__STATIC_INLINE uint32_t DL_Timer_getEnabledEventStatus(
    GPTIMER_Regs *gptimer, DL_TIMER_EVENT_ROUTE index, uint32_t eventMask)
{
    const volatile uint32_t *pReg =
        (const volatile uint32_t *) &gptimer->GEN_EVENT0.MIS;

    return ((*(pReg + (uint32_t) index) & eventMask));
}

__STATIC_INLINE uint32_t DL_Timer_getRawEventsStatus(
    GPTIMER_Regs *gptimer, DL_TIMER_EVENT_ROUTE index, uint32_t eventMask)
{
    const volatile uint32_t *pReg =
        (const volatile uint32_t *) &gptimer->GEN_EVENT0.RIS;

    return ((*(pReg + (uint32_t) index) & eventMask));
}

__STATIC_INLINE void DL_Timer_clearEventsStatus(
    GPTIMER_Regs *gptimer, DL_TIMER_EVENT_ROUTE index, uint32_t eventMask)
{
    volatile uint32_t *pReg = (volatile uint32_t *) &gptimer->GEN_EVENT0.ICLR;

    *(pReg + (uint32_t) index) |= (eventMask);
}

bool DL_Timer_saveConfiguration(
    GPTIMER_Regs *gptimer, DL_Timer_backupConfig *ptr);

bool DL_Timer_restoreConfiguration(
    GPTIMER_Regs *gptimer, DL_Timer_backupConfig *ptr, bool restoreCounter);

__STATIC_INLINE void DL_Timer_setCoreHaltBehavior(
    GPTIMER_Regs *gptimer, DL_TIMER_CORE_HALT haltMode)
{
    gptimer->PDBGCTL = ((uint32_t) haltMode & (GPTIMER_PDBGCTL_FREE_MASK |
                                                  GPTIMER_PDBGCTL_SOFT_MASK));
}

__STATIC_INLINE DL_TIMER_CORE_HALT DL_Timer_getCoreHaltBehavior(
    GPTIMER_Regs *gptimer)
{
    uint32_t haltMode = (gptimer->PDBGCTL & (GPTIMER_PDBGCTL_FREE_MASK |
                                                GPTIMER_PDBGCTL_SOFT_MASK));

    return (DL_TIMER_CORE_HALT)(haltMode);
}

#ifdef __cplusplus
}
#endif

#endif /* __MSPM0_HAS_TIMER_A__ || __MSPM0_HAS_TIMER_G__ */

#else
#warning \
    "TI highly recommends accessing timer with dl_timera and dl_timerg only."
#endif /* ti_dl_dl_timera__include ti_dl_dl_timerg__include*/

#endif /* ti_dl_dl_timer__include */