dl_comp.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/*!****************************************************************************
 *  @file       dl_comp.h
 *  @brief      Comparator (COMP)
 *  @defgroup   COMP Comparator (COMP)
 *
 *  @anchor ti_dl_dl_comp_Overview
 *  # Overview
 *
 *  The COMP DriverLib allows full configuration of the MSPM0 comparator module.
 *  The comparator module (COMP) is an analog voltage comparator with general
 *  comparator functionality.
 *
 *  <hr>
 ******************************************************************************/
#ifndef ti_dl_m0p_dl_comp__include
#define ti_dl_m0p_dl_comp__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#ifdef __MSPM0_HAS_COMP__

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

#define DL_COMP_INTERRUPT_OUTPUT_READY               (COMP_CPU_INT_IMASK_OUTRDYIFG_SET)

#define DL_COMP_INTERRUPT_OUTPUT_EDGE                  (COMP_CPU_INT_IMASK_COMPIFG_SET)

#define DL_COMP_INTERRUPT_OUTPUT_EDGE_INV           (COMP_CPU_INT_IMASK_COMPINVIFG_SET)

#define DL_COMP_EVENT_OUTPUT_READY               (COMP_GEN_EVENT_IMASK_OUTRDYIFG_SET)

#define DL_COMP_EVENT_OUTPUT_EDGE                  (COMP_GEN_EVENT_IMASK_COMPIFG_SET)

#define DL_COMP_EVENT_OUTPUT_EDGE_INV           (COMP_GEN_EVENT_IMASK_COMPINVIFG_SET)

/* clang-format on */

typedef enum {
    DL_COMP_IIDX_NO_INTERRUPT = COMP_CPU_INT_IIDX_STAT_NO_INTR,
    DL_COMP_IIDX_OUTPUT_READY = COMP_CPU_INT_IIDX_STAT_OUTRDYIFG,
    DL_COMP_IIDX_OUTPUT_EDGE = COMP_CPU_INT_IIDX_STAT_COMPIFG,
    DL_COMP_IIDX_OUTPUT_EDGE_INV = COMP_CPU_INT_IIDX_STAT_COMPINVIFG,
} DL_COMP_IIDX;

typedef enum {
    DL_COMP_MODE_FAST = COMP_CTL1_MODE_FAST,
    DL_COMP_MODE_ULP = COMP_CTL1_MODE_ULP,
} DL_COMP_MODE;

typedef enum {
    DL_COMP_OUTPUT_INT_EDGE_RISING = COMP_CTL1_IES_RISING,
    DL_COMP_OUTPUT_INT_EDGE_FALLING = COMP_CTL1_IES_FALLING,
} DL_COMP_OUTPUT_INT_EDGE;

typedef enum {
    DL_COMP_HYSTERESIS_NONE = COMP_CTL1_HYST_NO_HYS,
    DL_COMP_HYSTERESIS_10 = COMP_CTL1_HYST_LOW_HYS,
    DL_COMP_HYSTERESIS_20 = COMP_CTL1_HYST_MED_HYS,
    DL_COMP_HYSTERESIS_30 = COMP_CTL1_HYST_HIGH_HYS,
} DL_COMP_HYSTERESIS;

typedef enum {
    DL_COMP_POLARITY_NON_INV = COMP_CTL1_OUTPOL_NON_INV,
    DL_COMP_POLARITY_INV = COMP_CTL1_OUTPOL_INV,
} DL_COMP_POLARITY;

typedef enum {
    DL_COMP_FILTER_DELAY_70 = COMP_CTL1_FLTDLY_DLY_0,
    DL_COMP_FILTER_DELAY_500 = COMP_CTL1_FLTDLY_DLY_1,
    DL_COMP_FILTER_DELAY_1200 = COMP_CTL1_FLTDLY_DLY_2,
    DL_COMP_FILTER_DELAY_2700 = COMP_CTL1_FLTDLY_DLY_3,
} DL_COMP_FILTER_DELAY;

typedef enum {
    DL_COMP_IPSEL_CHANNEL_0 = COMP_CTL0_IPSEL_CH_0,
    DL_COMP_IPSEL_CHANNEL_1 = COMP_CTL0_IPSEL_CH_1,
    DL_COMP_IPSEL_CHANNEL_2 = COMP_CTL0_IPSEL_CH_2,
    DL_COMP_IPSEL_CHANNEL_3 = COMP_CTL0_IPSEL_CH_3,
    DL_COMP_IPSEL_CHANNEL_4 = COMP_CTL0_IPSEL_CH_4,
    DL_COMP_IPSEL_CHANNEL_5 = COMP_CTL0_IPSEL_CH_5,
    DL_COMP_IPSEL_CHANNEL_6 = COMP_CTL0_IPSEL_CH_6,
    DL_COMP_IPSEL_CHANNEL_7 = COMP_CTL0_IPSEL_CH_7,
} DL_COMP_IPSEL_CHANNEL;

typedef enum {
    DL_COMP_IMSEL_CHANNEL_0 = COMP_CTL0_IMSEL_CH_0,
    DL_COMP_IMSEL_CHANNEL_1 = COMP_CTL0_IMSEL_CH_1,
    DL_COMP_IMSEL_CHANNEL_2 = COMP_CTL0_IMSEL_CH_2,
    DL_COMP_IMSEL_CHANNEL_3 = COMP_CTL0_IMSEL_CH_3,
    DL_COMP_IMSEL_CHANNEL_4 = COMP_CTL0_IMSEL_CH_4,
    DL_COMP_IMSEL_CHANNEL_5 = COMP_CTL0_IMSEL_CH_5,
    DL_COMP_IMSEL_CHANNEL_6 = COMP_CTL0_IMSEL_CH_6,
    DL_COMP_IMSEL_CHANNEL_7 = COMP_CTL0_IMSEL_CH_7,
} DL_COMP_IMSEL_CHANNEL;

typedef enum {
    DL_COMP_ENABLE_CHANNEL_NONE =
        (COMP_CTL0_IPEN_DISABLE | COMP_CTL0_IMEN_DISABLE),
    DL_COMP_ENABLE_CHANNEL_POS = COMP_CTL0_IPEN_ENABLE,
    DL_COMP_ENABLE_CHANNEL_NEG = COMP_CTL0_IMEN_ENABLE,
    DL_COMP_ENABLE_CHANNEL_POS_NEG =
        (COMP_CTL0_IPEN_ENABLE | COMP_CTL0_IMEN_ENABLE),
} DL_COMP_ENABLE_CHANNEL;

typedef enum {
    DL_COMP_REF_MODE_STATIC = COMP_CTL2_REFMODE_STATIC,
    DL_COMP_REF_MODE_SAMPLED = COMP_CTL2_REFMODE_SAMPLED,
} DL_COMP_REF_MODE;

typedef enum {
    DL_COMP_REF_SOURCE_NONE = COMP_CTL2_REFSRC_OFF,
    DL_COMP_REF_SOURCE_VDDA_DAC = COMP_CTL2_REFSRC_VDDA_DAC,
    DL_COMP_REF_SOURCE_VREF_DAC = COMP_CTL2_REFSRC_VREF_DAC,
    DL_COMP_REF_SOURCE_VREF = COMP_CTL2_REFSRC_VREF,

} DL_COMP_REF_SOURCE;

typedef enum {
    DL_COMP_REF_TERMINAL_SELECT_POS = COMP_CTL2_REFSEL_POSITIVE,
    DL_COMP_REF_TERMINAL_SELECT_NEG = COMP_CTL2_REFSEL_NEGATIVE,
} DL_COMP_REF_TERMINAL_SELECT;

typedef enum {
    DL_COMP_BLANKING_SOURCE_DISABLE = COMP_CTL2_BLANKSRC_DISABLE,
    DL_COMP_BLANKING_SOURCE_1 = COMP_CTL2_BLANKSRC_BLANKSRC1,
    DL_COMP_BLANKING_SOURCE_2 = COMP_CTL2_BLANKSRC_BLANKSRC2,
    DL_COMP_BLANKING_SOURCE_3 = COMP_CTL2_BLANKSRC_BLANKSRC3,
    DL_COMP_BLANKING_SOURCE_4 = COMP_CTL2_BLANKSRC_BLANKSRC4,
    DL_COMP_BLANKING_SOURCE_5 = COMP_CTL2_BLANKSRC_BLANKSRC5,
    DL_COMP_BLANKING_SOURCE_6 = COMP_CTL2_BLANKSRC_BLANKSRC6,
} DL_COMP_BLANKING_SOURCE;

typedef enum {
    DL_COMP_DAC_CONTROL_COMP_OUT = COMP_CTL2_DACCTL_COMPOUT_SEL,
    DL_COMP_DAC_CONTROL_SW = COMP_CTL2_DACCTL_DACSW_SEL,
} DL_COMP_DAC_CONTROL;

typedef enum {
    DL_COMP_DAC_INPUT_DACCODE0 = COMP_CTL2_DACSW_DACCODE0_SEL,
    DL_COMP_DAC_INPUT_DACCODE1 = COMP_CTL2_DACSW_DACCODE1_SEL,
} DL_COMP_DAC_INPUT;

typedef enum {
    DL_COMP_OUTPUT_HIGH = COMP_STAT_OUT_LOW,
    DL_COMP_OUTPUT_LOW = COMP_STAT_OUT_HIGH,
} DL_COMP_OUTPUT;

typedef enum {
    DL_COMP_SUBSCRIBER_INDEX_0 = 0,
    DL_COMP_SUBSCRIBER_INDEX_1 = 1
} DL_COMP_SUBSCRIBER_INDEX;

typedef struct {
    DL_COMP_MODE mode;
    DL_COMP_ENABLE_CHANNEL channelEnable;
    DL_COMP_IPSEL_CHANNEL posChannel;
    DL_COMP_IMSEL_CHANNEL negChannel;
    DL_COMP_POLARITY polarity;
    DL_COMP_HYSTERESIS hysteresis;
} DL_COMP_Config;

typedef struct {
    DL_COMP_REF_MODE mode;
    DL_COMP_REF_SOURCE source;
    DL_COMP_REF_TERMINAL_SELECT terminalSelect;
    DL_COMP_DAC_CONTROL controlSelect;
    DL_COMP_DAC_INPUT inputSelect;
} DL_COMP_RefVoltageConfig;

__STATIC_INLINE void DL_COMP_enablePower(COMP_Regs *comp)
{
    comp->GPRCM.PWREN = (COMP_PWREN_KEY_UNLOCK_W | COMP_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_COMP_disablePower(COMP_Regs *comp)
{
    comp->GPRCM.PWREN = (COMP_PWREN_KEY_UNLOCK_W | COMP_PWREN_ENABLE_DISABLE);
}

__STATIC_INLINE bool DL_COMP_isPowerEnabled(COMP_Regs *comp)
{
    return ((comp->GPRCM.PWREN & COMP_PWREN_ENABLE_MASK) ==
            COMP_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_COMP_reset(COMP_Regs *comp)
{
    comp->GPRCM.RSTCTL =
        (COMP_RSTCTL_KEY_UNLOCK_W | COMP_RSTCTL_RESETSTKYCLR_CLR |
            COMP_RSTCTL_RESETASSERT_ASSERT);
}

__STATIC_INLINE bool DL_COMP_isReset(COMP_Regs *comp)
{
    return ((comp->GPRCM.STAT & COMP_GPRCM_STAT_RESETSTKY_MASK) ==
            COMP_GPRCM_STAT_RESETSTKY_RESET);
}

__STATIC_INLINE void DL_COMP_init(COMP_Regs *comp, DL_COMP_Config *config)
{
    DL_Common_updateReg(&comp->CTL0,
        (uint32_t) config->posChannel | (uint32_t) config->negChannel |
            (uint32_t) config->channelEnable,
        COMP_CTL0_IMSEL_MASK | COMP_CTL0_IPSEL_MASK | COMP_CTL0_IPEN_MASK |
            COMP_CTL0_IMEN_MASK);

    DL_Common_updateReg(&comp->CTL1,
        (uint32_t) config->mode | (uint32_t) config->polarity |
            (uint32_t) config->hysteresis,
        COMP_CTL1_MODE_MASK | COMP_CTL1_HYST_MASK | COMP_CTL1_OUTPOL_MASK);
}

__STATIC_INLINE void DL_COMP_refVoltageInit(
    COMP_Regs *comp, DL_COMP_RefVoltageConfig *config)
{
    DL_Common_updateReg(&comp->CTL2,
        (uint32_t) config->mode | (uint32_t) config->source |
            (uint32_t) config->terminalSelect |
            (uint32_t) config->controlSelect | (uint32_t) config->inputSelect,
        COMP_CTL2_REFMODE_MASK | COMP_CTL2_REFSRC_MASK |
            COMP_CTL2_REFSEL_MASK | COMP_CTL2_DACCTL_MASK |
            COMP_CTL2_DACSW_MASK);
}

__STATIC_INLINE void DL_COMP_enable(COMP_Regs *comp)
{
    comp->CTL1 |= COMP_CTL1_ENABLE_ON;
}

__STATIC_INLINE bool DL_COMP_isEnabled(COMP_Regs *comp)
{
    return ((comp->CTL1 & COMP_CTL1_ENABLE_MASK) == COMP_CTL1_ENABLE_ON);
}

__STATIC_INLINE void DL_COMP_disable(COMP_Regs *comp)
{
    comp->CTL1 &= ~(COMP_CTL1_ENABLE_MASK);
}

__STATIC_INLINE void DL_COMP_setCompMode(COMP_Regs *comp, DL_COMP_MODE mode)
{
    DL_Common_updateReg(&comp->CTL1, (uint32_t) mode, COMP_CTL1_MODE_MASK);
}

__STATIC_INLINE DL_COMP_MODE DL_COMP_getCompMode(COMP_Regs *comp)
{
    uint32_t mode = (comp->CTL1 & COMP_CTL1_MODE_MASK);

    return (DL_COMP_MODE)(mode);
}

__STATIC_INLINE void DL_COMP_enableExchangeInputs(COMP_Regs *comp)
{
    comp->CTL1 |= COMP_CTL1_EXCH_EXC;
}

__STATIC_INLINE bool DL_COMP_isExchangeInputsEnabled(COMP_Regs *comp)
{
    return ((comp->CTL1 & COMP_CTL1_EXCH_MASK) == COMP_CTL1_EXCH_EXC);
}

__STATIC_INLINE void DL_COMP_disableExchangeInputs(COMP_Regs *comp)
{
    comp->CTL1 &= ~(COMP_CTL1_EXCH_MASK);
}

__STATIC_INLINE void DL_COMP_enableShortInputTerminals(COMP_Regs *comp)
{
    comp->CTL1 |= COMP_CTL1_SHORT_SHT;
}

__STATIC_INLINE bool DL_COMP_isInputTerminalsShorted(COMP_Regs *comp)
{
    return ((comp->CTL1 & COMP_CTL1_SHORT_MASK) == COMP_CTL1_SHORT_SHT);
}

__STATIC_INLINE void DL_COMP_disableShortInputTerminals(COMP_Regs *comp)
{
    comp->CTL1 &= ~(COMP_CTL1_SHORT_MASK);
}

__STATIC_INLINE void DL_COMP_setOutputInterruptEdge(
    COMP_Regs *comp, DL_COMP_OUTPUT_INT_EDGE edge)
{
    DL_Common_updateReg(&comp->CTL1, (uint32_t) edge, COMP_CTL1_IES_MASK);
}

__STATIC_INLINE DL_COMP_OUTPUT_INT_EDGE DL_COMP_getOutputInterruptEdge(
    COMP_Regs *comp)
{
    uint32_t interruptEdge = (comp->CTL1 & COMP_CTL1_IES_MASK);

    return (DL_COMP_OUTPUT_INT_EDGE)(interruptEdge);
}

__STATIC_INLINE void DL_COMP_setHysteresis(
    COMP_Regs *comp, DL_COMP_HYSTERESIS voltage)
{
    DL_Common_updateReg(&comp->CTL1, (uint32_t) voltage, COMP_CTL1_HYST_MASK);
}

__STATIC_INLINE DL_COMP_HYSTERESIS DL_COMP_getHysteresis(COMP_Regs *comp)
{
    uint32_t hysteresis = (comp->CTL1 & COMP_CTL1_HYST_MASK);

    return (DL_COMP_HYSTERESIS)(hysteresis);
}

__STATIC_INLINE void DL_COMP_setOutputPolarity(
    COMP_Regs *comp, DL_COMP_POLARITY polarity)
{
    DL_Common_updateReg(
        &comp->CTL1, (uint32_t) polarity, COMP_CTL1_OUTPOL_MASK);
}

__STATIC_INLINE DL_COMP_POLARITY DL_COMP_getOutputPolarity(COMP_Regs *comp)
{
    uint32_t polarity = (comp->CTL1 & COMP_CTL1_OUTPOL_MASK);

    return (DL_COMP_POLARITY)(polarity);
}

__STATIC_INLINE void DL_COMP_enableOutputFilter(
    COMP_Regs *comp, DL_COMP_FILTER_DELAY delay)
{
    comp->CTL1 |= (COMP_CTL1_FLTEN_ENABLE | (uint32_t) delay);
}

__STATIC_INLINE bool DL_COMP_isOutputFilterEnabled(COMP_Regs *comp)
{
    return ((comp->CTL1 & COMP_CTL1_FLTEN_MASK) == COMP_CTL1_FLTEN_ENABLE);
}

__STATIC_INLINE void DL_COMP_disableOutputFilter(COMP_Regs *comp)
{
    comp->CTL1 &= ~(COMP_CTL1_FLTEN_MASK);
}

__STATIC_INLINE DL_COMP_FILTER_DELAY DL_COMP_getOutputFilterDelay(
    COMP_Regs *comp)
{
    uint32_t delay = (comp->CTL1 & COMP_CTL1_FLTDLY_MASK);

    return (DL_COMP_FILTER_DELAY)(delay);
}

__STATIC_INLINE void DL_COMP_enableWindowComparator(COMP_Regs *comp)
{
    comp->CTL1 |= COMP_CTL1_WINCOMPEN_ON;
}

__STATIC_INLINE bool DL_COMP_isWindowComparatorEnabled(COMP_Regs *comp)
{
    return ((comp->CTL1 & COMP_CTL1_WINCOMPEN_MASK) == COMP_CTL1_WINCOMPEN_ON);
}

__STATIC_INLINE void DL_COMP_disableWindowComparator(COMP_Regs *comp)
{
    comp->CTL1 &= ~(COMP_CTL1_WINCOMPEN_MASK);
}

__STATIC_INLINE void DL_COMP_setEnabledInputChannels(
    COMP_Regs *comp, DL_COMP_ENABLE_CHANNEL channels)
{
    DL_Common_updateReg(&comp->CTL0, (uint32_t) channels,
        (COMP_CTL0_IMEN_MASK | COMP_CTL0_IPEN_MASK));
}

__STATIC_INLINE DL_COMP_ENABLE_CHANNEL DL_COMP_getEnabledInputChannels(
    COMP_Regs *comp)
{
    uint32_t channel =
        (comp->CTL0 & (COMP_CTL0_IMEN_MASK | COMP_CTL0_IPEN_MASK));

    return (DL_COMP_ENABLE_CHANNEL)(channel);
}

__STATIC_INLINE void DL_COMP_setPositiveChannelInput(
    COMP_Regs *comp, DL_COMP_IPSEL_CHANNEL input)
{
    DL_Common_updateReg(&comp->CTL0, (uint32_t) input, COMP_CTL0_IPSEL_MASK);
}

__STATIC_INLINE DL_COMP_IPSEL_CHANNEL DL_COMP_getPositiveChannelInput(
    COMP_Regs *comp)
{
    uint32_t channel = (comp->CTL0 & COMP_CTL0_IPSEL_MASK);

    return (DL_COMP_IPSEL_CHANNEL)(channel);
}

__STATIC_INLINE void DL_COMP_setNegativeChannelInput(
    COMP_Regs *comp, DL_COMP_IMSEL_CHANNEL input)
{
    DL_Common_updateReg(&comp->CTL0, (uint32_t) input, COMP_CTL0_IMSEL_MASK);
}

__STATIC_INLINE DL_COMP_IMSEL_CHANNEL DL_COMP_getNegativeChannelInput(
    COMP_Regs *comp)
{
    uint32_t channel = (comp->CTL0 & COMP_CTL0_IMSEL_MASK);

    return (DL_COMP_IMSEL_CHANNEL)(channel);
}

__STATIC_INLINE void DL_COMP_setReferenceMode(
    COMP_Regs *comp, DL_COMP_REF_MODE mode)
{
    DL_Common_updateReg(&comp->CTL2, (uint32_t) mode, COMP_CTL2_REFMODE_MASK);
}

__STATIC_INLINE DL_COMP_REF_MODE DL_COMP_getReferenceMode(COMP_Regs *comp)
{
    uint32_t mode = (comp->CTL2 & COMP_CTL2_REFMODE_MASK);

    return (DL_COMP_REF_MODE)(mode);
}

__STATIC_INLINE void DL_COMP_setReferenceSource(
    COMP_Regs *comp, DL_COMP_REF_SOURCE source)
{
    DL_Common_updateReg(&comp->CTL2, (uint32_t) source, COMP_CTL2_REFSRC_MASK);
}

__STATIC_INLINE DL_COMP_REF_SOURCE DL_COMP_getReferenceSource(COMP_Regs *comp)
{
    uint32_t source = (comp->CTL2 & COMP_CTL2_REFSRC_MASK);

    return (DL_COMP_REF_SOURCE)(source);
}

__STATIC_INLINE void DL_COMP_setReferenceCompTerminal(
    COMP_Regs *comp, DL_COMP_REF_TERMINAL_SELECT terminal)
{
    DL_Common_updateReg(
        &comp->CTL2, (uint32_t) terminal, COMP_CTL2_REFSEL_MASK);
}

__STATIC_INLINE DL_COMP_REF_TERMINAL_SELECT DL_COMP_getReferenceCompTerminal(
    COMP_Regs *comp)
{
    uint32_t terminal = (comp->CTL2 & COMP_CTL2_REFSEL_MASK);

    return (DL_COMP_REF_TERMINAL_SELECT)(terminal);
}

__STATIC_INLINE void DL_COMP_setBlankingSource(
    COMP_Regs *comp, DL_COMP_BLANKING_SOURCE source)
{
    DL_Common_updateReg(
        &comp->CTL2, (uint32_t) source, COMP_CTL2_BLANKSRC_MASK);
}

__STATIC_INLINE DL_COMP_BLANKING_SOURCE DL_COMP_getBlankingSource(
    COMP_Regs *comp)
{
    uint32_t source = (comp->CTL2 & COMP_CTL2_BLANKSRC_MASK);

    return (DL_COMP_BLANKING_SOURCE)(source);
}

__STATIC_INLINE void DL_COMP_setDACControl(
    COMP_Regs *comp, DL_COMP_DAC_CONTROL control)
{
    DL_Common_updateReg(
        &comp->CTL2, (uint32_t) control, COMP_CTL2_DACCTL_MASK);
}

__STATIC_INLINE DL_COMP_DAC_CONTROL DL_COMP_getDACControl(COMP_Regs *comp)
{
    uint32_t control = (comp->CTL2 & COMP_CTL2_DACCTL_MASK);

    return (DL_COMP_DAC_CONTROL)(control);
}

__STATIC_INLINE void DL_COMP_setDACInput(
    COMP_Regs *comp, DL_COMP_DAC_INPUT input)
{
    DL_Common_updateReg(&comp->CTL2, (uint32_t) input, COMP_CTL2_DACSW_MASK);
}

__STATIC_INLINE DL_COMP_DAC_INPUT DL_COMP_getDACInput(COMP_Regs *comp)
{
    uint32_t input = (comp->CTL2 & COMP_CTL2_DACSW_MASK);

    return (DL_COMP_DAC_INPUT)(input);
}

__STATIC_INLINE void DL_COMP_setDACCode0(COMP_Regs *comp, uint32_t value)
{
    DL_Common_updateReg(&comp->CTL3, value, COMP_CTL3_DACCODE0_MASK);
}

__STATIC_INLINE uint32_t DL_COMP_getDACCode0(COMP_Regs *comp)
{
    return (comp->CTL3 & COMP_CTL3_DACCODE0_MASK);
}

__STATIC_INLINE void DL_COMP_setDACCode1(COMP_Regs *comp, uint32_t value)
{
    DL_Common_updateReg(&comp->CTL3, (value << COMP_CTL3_DACCODE1_OFS),
        COMP_CTL3_DACCODE1_MASK);
}

__STATIC_INLINE uint32_t DL_COMP_getDACCode1(COMP_Regs *comp)
{
    return ((comp->CTL3 & COMP_CTL3_DACCODE1_MASK) >> COMP_CTL3_DACCODE1_OFS);
}

__STATIC_INLINE DL_COMP_OUTPUT DL_COMP_getComparatorOutput(COMP_Regs *comp)
{
    uint32_t output = (comp->STAT & COMP_STAT_OUT_MASK);

    return (DL_COMP_OUTPUT)(output);
}

__STATIC_INLINE void DL_COMP_enableSampledMode(COMP_Regs *comp)
{
    comp->CTL2 |= COMP_CTL2_SAMPMODE_ENABLE;
}

__STATIC_INLINE bool DL_COMP_isSampledModeEnabled(COMP_Regs *comp)
{
    return (
        (comp->CTL2 & COMP_CTL2_SAMPMODE_MASK) == COMP_CTL2_SAMPMODE_ENABLE);
}

__STATIC_INLINE void DL_COMP_disableSampledMode(COMP_Regs *comp)
{
    comp->CTL2 &= ~(COMP_CTL2_SAMPMODE_MASK);
}

__STATIC_INLINE void DL_COMP_setSubscriberChanID(
    COMP_Regs *comp, DL_COMP_SUBSCRIBER_INDEX index, uint8_t chanID)
{
    volatile uint32_t *pReg = &comp->FSUB_0;

    *(pReg + (uint32_t) index) = (chanID & COMP_FSUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_COMP_getSubscriberChanID(
    COMP_Regs *comp, DL_COMP_SUBSCRIBER_INDEX index)
{
    volatile uint32_t *pReg = &comp->FSUB_0;

    return ((uint8_t)(*(pReg + (uint32_t) index) & COMP_FSUB_0_CHANID_MASK));
}

__STATIC_INLINE void DL_COMP_enableInterrupt(
    COMP_Regs *comp, uint32_t interruptMask)
{
    comp->CPU_INT.IMASK |= interruptMask;
}

__STATIC_INLINE void DL_COMP_disableInterrupt(
    COMP_Regs *comp, uint32_t interruptMask)
{
    comp->CPU_INT.IMASK &= ~(interruptMask);
}

__STATIC_INLINE uint32_t DL_COMP_getEnabledInterrupts(
    COMP_Regs *comp, uint32_t interruptMask)
{
    return (comp->CPU_INT.IMASK & interruptMask);
}

__STATIC_INLINE uint32_t DL_COMP_getEnabledInterruptStatus(
    COMP_Regs *comp, uint32_t interruptMask)
{
    return (comp->CPU_INT.MIS & interruptMask);
}

__STATIC_INLINE uint32_t DL_COMP_getRawInterruptStatus(
    COMP_Regs *comp, uint32_t interruptMask)
{
    return (comp->CPU_INT.RIS & interruptMask);
}

__STATIC_INLINE DL_COMP_IIDX DL_COMP_getPendingInterrupt(COMP_Regs *comp)
{
    return (DL_COMP_IIDX)(comp->CPU_INT.IIDX);
}

__STATIC_INLINE void DL_COMP_clearInterruptStatus(
    COMP_Regs *comp, uint32_t interruptMask)
{
    comp->CPU_INT.ICLR = interruptMask;
}

__STATIC_INLINE void DL_COMP_setPublisherChanID(
    COMP_Regs *comp, uint8_t chanID)
{
    comp->FPUB_1 = (chanID & COMP_FPUB_1_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_COMP_getPublisherChanID(COMP_Regs *comp)
{
    return ((uint8_t)((comp->FPUB_1) & COMP_FPUB_1_CHANID_MAXIMUM));
}

__STATIC_INLINE void DL_COMP_enableEvent(COMP_Regs *comp, uint32_t eventMask)
{
    comp->GEN_EVENT.IMASK |= (eventMask);
}

__STATIC_INLINE void DL_COMP_disableEvent(COMP_Regs *comp, uint32_t eventMask)
{
    comp->GEN_EVENT.IMASK &= ~(eventMask);
}

__STATIC_INLINE uint32_t DL_COMP_getEnabledEvents(
    COMP_Regs *comp, uint32_t eventMask)
{
    return ((comp->GEN_EVENT.IMASK) & (eventMask));
}

__STATIC_INLINE uint32_t DL_COMP_getEnabledEventStatus(
    COMP_Regs *comp, uint32_t eventMask)
{
    return ((comp->GEN_EVENT.MIS) & eventMask);
}

__STATIC_INLINE uint32_t DL_COMP_getRawEventsStatus(
    COMP_Regs *comp, uint32_t eventMask)
{
    return ((comp->GEN_EVENT.RIS) & eventMask);
}

__STATIC_INLINE void DL_COMP_clearEventsStatus(
    COMP_Regs *comp, uint32_t eventMask)
{
    comp->GEN_EVENT.ICLR |= (eventMask);
}

/* clang-format on */

#ifdef __cplusplus
}
#endif

#endif /* __MSPM0_HAS_COMP__ */

#endif /* ti_dl_m0p_dl_comp__include */