38 #ifndef __DRIVERLIB_I2C_H__ 39 #define __DRIVERLIB_I2C_H__ 66 #define I2C_INT_MASTER 0x00000001 67 #define I2C_INT_SLAVE 0x00000002 74 #define I2C_MASTER_CMD_SINGLE_SEND \ 76 #define I2C_MASTER_CMD_SINGLE_RECEIVE \ 78 #define I2C_MASTER_CMD_BURST_SEND_START \ 80 #define I2C_MASTER_CMD_BURST_SEND_CONT \ 82 #define I2C_MASTER_CMD_BURST_SEND_FINISH \ 84 #define I2C_MASTER_CMD_BURST_SEND_STOP \ 86 #define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ 88 #define I2C_MASTER_CMD_BURST_RECEIVE_START \ 90 #define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ 92 #define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ 94 #define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ 96 #define I2C_MASTER_CMD_QUICK_COMMAND \ 98 #define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ 100 #define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ 102 #define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ 104 #define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ 106 #define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ 108 #define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ 110 #define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ 112 #define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ 114 #define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ 116 #define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ 118 #define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ 126 #define I2C_MASTER_GLITCH_FILTER_DISABLED \ 128 #define I2C_MASTER_GLITCH_FILTER_1 \ 130 #define I2C_MASTER_GLITCH_FILTER_2 \ 132 #define I2C_MASTER_GLITCH_FILTER_3 \ 134 #define I2C_MASTER_GLITCH_FILTER_4 \ 136 #define I2C_MASTER_GLITCH_FILTER_8 \ 138 #define I2C_MASTER_GLITCH_FILTER_16 \ 140 #define I2C_MASTER_GLITCH_FILTER_32 \ 148 #define I2C_MASTER_ERR_NONE 0 149 #define I2C_MASTER_ERR_ADDR_ACK 0x00000004 150 #define I2C_MASTER_ERR_DATA_ACK 0x00000008 151 #define I2C_MASTER_ERR_ARB_LOST 0x00000010 152 #define I2C_MASTER_ERR_CLK_TOUT 0x00000080 159 #define I2C_SLAVE_ACT_NONE 0 160 #define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data 161 #define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data 162 #define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte 163 #define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave 164 #define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command 165 #define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value 172 #define I2C_MASTER_MAX_RETRIES 1000 // Number of retries 179 #define I2C_MASTER_INT_RX_FIFO_FULL \ 180 0x00000800 // RX FIFO Full Interrupt 181 #define I2C_MASTER_INT_TX_FIFO_EMPTY \ 182 0x00000400 // TX FIFO Empty Interrupt 183 #define I2C_MASTER_INT_RX_FIFO_REQ \ 184 0x00000200 // RX FIFO Request Interrupt 185 #define I2C_MASTER_INT_TX_FIFO_REQ \ 186 0x00000100 // TX FIFO Request Interrupt 187 #define I2C_MASTER_INT_ARB_LOST \ 188 0x00000080 // Arb Lost Interrupt 189 #define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt 190 #define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt 191 #define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt 192 #define I2C_MASTER_INT_TX_DMA_DONE \ 193 0x00000008 // TX DMA Complete Interrupt 194 #define I2C_MASTER_INT_RX_DMA_DONE \ 195 0x00000004 // RX DMA Complete Interrupt 196 #define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt 197 #define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt 204 #define I2C_SLAVE_INT_RX_FIFO_FULL \ 205 0x00000100 // RX FIFO Full Interrupt 206 #define I2C_SLAVE_INT_TX_FIFO_EMPTY \ 207 0x00000080 // TX FIFO Empty Interrupt 208 #define I2C_SLAVE_INT_RX_FIFO_REQ \ 209 0x00000040 // RX FIFO Request Interrupt 210 #define I2C_SLAVE_INT_TX_FIFO_REQ \ 211 0x00000020 // TX FIFO Request Interrupt 212 #define I2C_SLAVE_INT_TX_DMA_DONE \ 213 0x00000010 // TX DMA Complete Interrupt 214 #define I2C_SLAVE_INT_RX_DMA_DONE \ 215 0x00000008 // RX DMA Complete Interrupt 216 #define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt 217 #define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt 218 #define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt 225 #define I2C_SLAVE_TX_FIFO_ENABLE \ 227 #define I2C_SLAVE_RX_FIFO_ENABLE \ 235 #define I2C_FIFO_CFG_TX_MASTER 0x00000000 236 #define I2C_FIFO_CFG_TX_SLAVE 0x00008000 237 #define I2C_FIFO_CFG_RX_MASTER 0x00000000 238 #define I2C_FIFO_CFG_RX_SLAVE 0x80000000 239 #define I2C_FIFO_CFG_TX_MASTER_DMA \ 241 #define I2C_FIFO_CFG_TX_SLAVE_DMA \ 243 #define I2C_FIFO_CFG_RX_MASTER_DMA \ 245 #define I2C_FIFO_CFG_RX_SLAVE_DMA \ 247 #define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 248 #define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 249 #define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 250 #define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 251 #define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 252 #define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 253 #define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 254 #define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 255 #define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 256 #define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 257 #define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 258 #define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 259 #define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 260 #define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 261 #define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 262 #define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 263 #define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 264 #define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 271 #define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ 273 #define I2C_FIFO_RX_FULL 0x00020000 274 #define I2C_FIFO_RX_EMPTY 0x00010000 275 #define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ 277 #define I2C_FIFO_TX_FULL 0x00000002 278 #define I2C_FIFO_TX_EMPTY 0x00000001 285 extern void I2CIntRegister(uint32_t ui32Base,
void(*pfnHandler)(
void));
302 uint32_t ui32Config);
320 uint32_t ui32IntFlags);
322 uint32_t ui32IntFlags);
326 uint32_t ui32IntFlags);
332 uint8_t ui8SlaveAddr,
338 extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
340 uint8_t ui8SlaveAddr);
346 uint32_t ui32IntFlags);
363 #endif // __DRIVERLIB_I2C_H__ bool I2CMasterBusy(uint32_t ui32Base)
Definition: i2c.c:1150
void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr)
Definition: i2c.c:283
void I2CMasterEnable(uint32_t ui32Base)
Definition: i2c.c:329
void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:1969
void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:1669
bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:784
void I2CTxFIFOFlush(uint32_t ui32Base)
Definition: i2c.c:1631
void I2CLoopbackEnable(uint32_t ui32Base)
Definition: i2c.c:2061
bool I2CMasterBusBusy(uint32_t ui32Base)
Definition: i2c.c:1185
uint32_t I2CFIFODataGet(uint32_t ui32Base)
Definition: i2c.c:1826
void I2CMasterIntDisable(uint32_t ui32Base)
Definition: i2c.c:665
void I2CMasterDisable(uint32_t ui32Base)
Definition: i2c.c:384
void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
Definition: i2c.c:1536
uint32_t I2CSlaveStatus(uint32_t ui32Base)
Definition: i2c.c:1510
uint32_t I2CMasterBurstCountGet(uint32_t ui32Base)
Definition: i2c.c:1928
void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:1601
void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:640
void I2CRxFIFOFlush(uint32_t ui32Base)
Definition: i2c.c:1699
void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data)
Definition: i2c.c:1342
void I2CSlaveIntClear(uint32_t ui32Base)
Definition: i2c.c:1023
void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data)
Definition: i2c.c:1757
void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK)
Definition: i2c.c:1460
void I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, bool bReceive)
Definition: i2c.c:1094
void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)
Definition: i2c.c:181
uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:822
void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr)
Definition: i2c.c:248
void I2CSlaveIntEnable(uint32_t ui32Base)
Definition: i2c.c:600
void I2CMasterIntClear(uint32_t ui32Base)
Definition: i2c.c:942
uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:898
uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data)
Definition: i2c.c:1791
void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:2006
void I2CSlaveDisable(uint32_t ui32Base)
Definition: i2c.c:409
void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value)
Definition: i2c.c:1398
void I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:575
void I2CSlaveFIFODisable(uint32_t ui32Base)
Definition: i2c.c:2032
uint32_t I2CFIFOStatus(uint32_t ui32Base)
Definition: i2c.c:1729
void I2CSlaveIntDisable(uint32_t ui32Base)
Definition: i2c.c:722
void I2CMasterIntEnable(uint32_t ui32Base)
Definition: i2c.c:532
void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd)
Definition: i2c.c:1243
uint32_t I2CMasterLineStateGet(uint32_t ui32Base)
Definition: i2c.c:1123
bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:860
uint32_t I2CMasterErr(uint32_t ui32Base)
Definition: i2c.c:1293
uint32_t I2CSlaveDataGet(uint32_t ui32Base)
Definition: i2c.c:1562
uint32_t I2CMasterDataGet(uint32_t ui32Base)
Definition: i2c.c:1368
uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data)
Definition: i2c.c:1861
void I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length)
Definition: i2c.c:1900
void I2CSlaveEnable(uint32_t ui32Base)
Definition: i2c.c:354
void I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:697
void I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:987
void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable)
Definition: i2c.c:1425
void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
Definition: i2c.c:449
void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:1063
void I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:754
void I2CIntUnregister(uint32_t ui32Base)
Definition: i2c.c:493