MSP432E4 DriverLib API Guide
1.11.00.03
tmp
bazel_docapi.z9EuJc
source
ti
devices
msp432e4
driverlib
inc
hw_timer.h
Go to the documentation of this file.
1
//*****************************************************************************
2
//
3
// hw_timer.h - Defines and macros used when accessing the timer.
4
//
5
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
6
// Software License Agreement
7
//
8
// Redistribution and use in source and binary forms, with or without
9
// modification, are permitted provided that the following conditions
10
// are met:
11
//
12
// Redistributions of source code must retain the above copyright
13
// notice, this list of conditions and the following disclaimer.
14
//
15
// Redistributions in binary form must reproduce the above copyright
16
// notice, this list of conditions and the following disclaimer in the
17
// documentation and/or other materials provided with the
18
// distribution.
19
//
20
// Neither the name of Texas Instruments Incorporated nor the names of
21
// its contributors may be used to endorse or promote products derived
22
// from this software without specific prior written permission.
23
//
24
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35
//
36
//*****************************************************************************
37
38
#ifndef __HW_TIMER_H__
39
#define __HW_TIMER_H__
40
41
//*****************************************************************************
42
//
43
// The following are defines for the Timer register offsets.
44
//
45
//*****************************************************************************
46
#define TIMER_O_CFG 0x00000000 // GPTM Configuration
47
#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
48
#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
49
#define TIMER_O_CTL 0x0000000C // GPTM Control
50
#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
51
#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
52
#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
53
#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
54
#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
55
#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
56
#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
57
#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
58
#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
59
#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
60
#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
61
#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
62
#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
63
#define TIMER_O_TAR 0x00000048 // GPTM Timer A
64
#define TIMER_O_TBR 0x0000004C // GPTM Timer B
65
#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
66
#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
67
#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
68
#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
69
#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
70
#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
71
#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
72
#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event
73
#define TIMER_O_ADCEV 0x00000070 // GPTM ADC Event
74
#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
75
#define TIMER_O_CC 0x00000FC8 // GPTM Clock Configuration
76
77
//*****************************************************************************
78
//
79
// The following are defines for the bit fields in the TIMER_O_CFG register.
80
//
81
//*****************************************************************************
82
#define TIMER_CFG_M 0x00000007 // GPTM Configuration
83
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this
84
// value selects the 32-bit timer
85
// configuration
86
#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this
87
// value selects the 32-bit
88
// real-time clock (RTC) counter
89
// configuration
90
#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this
91
// value selects the 16-bit timer
92
// configuration
93
94
//*****************************************************************************
95
//
96
// The following are defines for the bit fields in the TIMER_O_TAMR register.
97
//
98
//*****************************************************************************
99
#define TIMER_TAMR_TCACT_M 0x0000E000 // Timer Compare Action Select
100
#define TIMER_TAMR_TCACT_NONE 0x00000000 // Disable compare operations
101
#define TIMER_TAMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out
102
#define TIMER_TAMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out
103
#define TIMER_TAMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out
104
#define TIMER_TAMR_TCACT_SETTOGTO \
105
0x00008000 // Set CCP immediately and toggle
106
// on Time-Out
107
#define TIMER_TAMR_TCACT_CLRTOGTO \
108
0x0000A000 // Clear CCP immediately and toggle
109
// on Time-Out
110
#define TIMER_TAMR_TCACT_SETCLRTO \
111
0x0000C000 // Set CCP immediately and clear on
112
// Time-Out
113
#define TIMER_TAMR_TCACT_CLRSETTO \
114
0x0000E000 // Clear CCP immediately and set on
115
// Time-Out
116
#define TIMER_TAMR_TACINTD 0x00001000 // One-shot/Periodic Interrupt
117
// Disable
118
#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
119
// Operation
120
#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
121
// Update
122
#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
123
// Enable
124
#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
125
#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
126
#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
127
#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
128
// Enable
129
#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
130
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
131
// Select
132
#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
133
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
134
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
135
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
136
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
137
138
//*****************************************************************************
139
//
140
// The following are defines for the bit fields in the TIMER_O_TBMR register.
141
//
142
//*****************************************************************************
143
#define TIMER_TBMR_TCACT_M 0x0000E000 // Timer Compare Action Select
144
#define TIMER_TBMR_TCACT_NONE 0x00000000 // Disable compare operations
145
#define TIMER_TBMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out
146
#define TIMER_TBMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out
147
#define TIMER_TBMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out
148
#define TIMER_TBMR_TCACT_SETTOGTO \
149
0x00008000 // Set CCP immediately and toggle
150
// on Time-Out
151
#define TIMER_TBMR_TCACT_CLRTOGTO \
152
0x0000A000 // Clear CCP immediately and toggle
153
// on Time-Out
154
#define TIMER_TBMR_TCACT_SETCLRTO \
155
0x0000C000 // Set CCP immediately and clear on
156
// Time-Out
157
#define TIMER_TBMR_TCACT_CLRSETTO \
158
0x0000E000 // Clear CCP immediately and set on
159
// Time-Out
160
#define TIMER_TBMR_TBCINTD 0x00001000 // One-Shot/Periodic Interrupt
161
// Disable
162
#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
163
// Operation
164
#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
165
// Update
166
#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
167
// Enable
168
#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
169
#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
170
#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
171
#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
172
// Enable
173
#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
174
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
175
// Select
176
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
177
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
178
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
179
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
180
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
181
182
//*****************************************************************************
183
//
184
// The following are defines for the bit fields in the TIMER_O_CTL register.
185
//
186
//*****************************************************************************
187
#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
188
#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
189
// Enable
190
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
191
#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
192
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
193
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
194
#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
195
#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
196
#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
197
#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
198
// Enable
199
#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
200
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
201
#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
202
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
203
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
204
#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
205
#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
206
207
//*****************************************************************************
208
//
209
// The following are defines for the bit fields in the TIMER_O_SYNC register.
210
//
211
//*****************************************************************************
212
#define TIMER_SYNC_SYNCT7_M 0x0000C000 // Synchronize GPTM Timer 7
213
#define TIMER_SYNC_SYNCT7_NONE 0x00000000 // GPT7 is not affected
214
#define TIMER_SYNC_SYNCT7_TA 0x00004000 // A timeout event for Timer A of
215
// GPTM7 is triggered
216
#define TIMER_SYNC_SYNCT7_TB 0x00008000 // A timeout event for Timer B of
217
// GPTM7 is triggered
218
#define TIMER_SYNC_SYNCT7_TATB 0x0000C000 // A timeout event for both Timer A
219
// and Timer B of GPTM7 is
220
// triggered
221
#define TIMER_SYNC_SYNCT6_M 0x00003000 // Synchronize GPTM Timer 6
222
#define TIMER_SYNC_SYNCT6_NONE 0x00000000 // GPTM6 is not affected
223
#define TIMER_SYNC_SYNCT6_TA 0x00001000 // A timeout event for Timer A of
224
// GPTM6 is triggered
225
#define TIMER_SYNC_SYNCT6_TB 0x00002000 // A timeout event for Timer B of
226
// GPTM6 is triggered
227
#define TIMER_SYNC_SYNCT6_TATB 0x00003000 // A timeout event for both Timer A
228
// and Timer B of GPTM6 is
229
// triggered
230
#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5
231
#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected
232
#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
233
// GPTM5 is triggered
234
#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
235
// GPTM5 is triggered
236
#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
237
// and Timer B of GPTM5 is
238
// triggered
239
#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4
240
#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected
241
#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
242
// GPTM4 is triggered
243
#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
244
// GPTM4 is triggered
245
#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
246
// and Timer B of GPTM4 is
247
// triggered
248
#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3
249
#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected
250
#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
251
// GPTM3 is triggered
252
#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
253
// GPTM3 is triggered
254
#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
255
// and Timer B of GPTM3 is
256
// triggered
257
#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2
258
#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected
259
#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
260
// GPTM2 is triggered
261
#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
262
// GPTM2 is triggered
263
#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
264
// and Timer B of GPTM2 is
265
// triggered
266
#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1
267
#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected
268
#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
269
// GPTM1 is triggered
270
#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
271
// GPTM1 is triggered
272
#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
273
// and Timer B of GPTM1 is
274
// triggered
275
#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0
276
#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected
277
#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
278
// GPTM0 is triggered
279
#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
280
// GPTM0 is triggered
281
#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
282
// and Timer B of GPTM0 is
283
// triggered
284
285
//*****************************************************************************
286
//
287
// The following are defines for the bit fields in the TIMER_O_IMR register.
288
//
289
//*****************************************************************************
290
#define TIMER_IMR_DMABIM 0x00002000 // GPTM Timer B DMA Done Interrupt
291
// Mask
292
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
293
// Mask
294
#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
295
// Interrupt Mask
296
#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
297
// Interrupt Mask
298
#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
299
// Mask
300
#define TIMER_IMR_DMAAIM 0x00000020 // GPTM Timer A DMA Done Interrupt
301
// Mask
302
#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
303
// Mask
304
#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
305
#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
306
// Interrupt Mask
307
#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
308
// Interrupt Mask
309
#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
310
// Mask
311
312
//*****************************************************************************
313
//
314
// The following are defines for the bit fields in the TIMER_O_RIS register.
315
//
316
//*****************************************************************************
317
#define TIMER_RIS_DMABRIS 0x00002000 // GPTM Timer B DMA Done Raw
318
// Interrupt Status
319
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
320
#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
321
// Raw Interrupt
322
#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
323
// Raw Interrupt
324
#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
325
// Interrupt
326
#define TIMER_RIS_DMAARIS 0x00000020 // GPTM Timer A DMA Done Raw
327
// Interrupt Status
328
#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
329
#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
330
#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
331
// Raw Interrupt
332
#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
333
// Raw Interrupt
334
#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
335
// Interrupt
336
337
//*****************************************************************************
338
//
339
// The following are defines for the bit fields in the TIMER_O_MIS register.
340
//
341
//*****************************************************************************
342
#define TIMER_MIS_DMABMIS 0x00002000 // GPTM Timer B DMA Done Masked
343
// Interrupt
344
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
345
// Interrupt
346
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
347
// Masked Interrupt
348
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
349
// Masked Interrupt
350
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
351
// Interrupt
352
#define TIMER_MIS_DMAAMIS 0x00000020 // GPTM Timer A DMA Done Masked
353
// Interrupt
354
#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
355
// Interrupt
356
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
357
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
358
// Masked Interrupt
359
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
360
// Masked Interrupt
361
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
362
// Interrupt
363
364
//*****************************************************************************
365
//
366
// The following are defines for the bit fields in the TIMER_O_ICR register.
367
//
368
//*****************************************************************************
369
#define TIMER_ICR_DMABINT 0x00002000 // GPTM Timer B DMA Done Interrupt
370
// Clear
371
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
372
// Clear
373
#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
374
// Interrupt Clear
375
#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
376
// Interrupt Clear
377
#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
378
// Clear
379
#define TIMER_ICR_DMAAINT 0x00000020 // GPTM Timer A DMA Done Interrupt
380
// Clear
381
#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
382
// Clear
383
#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
384
#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
385
// Interrupt Clear
386
#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
387
// Interrupt Clear
388
#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
389
// Interrupt
390
391
//*****************************************************************************
392
//
393
// The following are defines for the bit fields in the TIMER_O_TAILR register.
394
//
395
//*****************************************************************************
396
#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
397
// Register
398
#define TIMER_TAILR_S 0
399
400
//*****************************************************************************
401
//
402
// The following are defines for the bit fields in the TIMER_O_TBILR register.
403
//
404
//*****************************************************************************
405
#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
406
// Register
407
#define TIMER_TBILR_S 0
408
409
//*****************************************************************************
410
//
411
// The following are defines for the bit fields in the TIMER_O_TAMATCHR
412
// register.
413
//
414
//*****************************************************************************
415
#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
416
#define TIMER_TAMATCHR_TAMR_S 0
417
418
//*****************************************************************************
419
//
420
// The following are defines for the bit fields in the TIMER_O_TBMATCHR
421
// register.
422
//
423
//*****************************************************************************
424
#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
425
#define TIMER_TBMATCHR_TBMR_S 0
426
427
//*****************************************************************************
428
//
429
// The following are defines for the bit fields in the TIMER_O_TAPR register.
430
//
431
//*****************************************************************************
432
#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
433
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
434
#define TIMER_TAPR_TAPSRH_S 8
435
#define TIMER_TAPR_TAPSR_S 0
436
437
//*****************************************************************************
438
//
439
// The following are defines for the bit fields in the TIMER_O_TBPR register.
440
//
441
//*****************************************************************************
442
#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
443
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
444
#define TIMER_TBPR_TBPSRH_S 8
445
#define TIMER_TBPR_TBPSR_S 0
446
447
//*****************************************************************************
448
//
449
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
450
//
451
//*****************************************************************************
452
#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
453
// Byte
454
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
455
#define TIMER_TAPMR_TAPSMRH_S 8
456
#define TIMER_TAPMR_TAPSMR_S 0
457
458
//*****************************************************************************
459
//
460
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
461
//
462
//*****************************************************************************
463
#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
464
// Byte
465
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
466
#define TIMER_TBPMR_TBPSMRH_S 8
467
#define TIMER_TBPMR_TBPSMR_S 0
468
469
//*****************************************************************************
470
//
471
// The following are defines for the bit fields in the TIMER_O_TAR register.
472
//
473
//*****************************************************************************
474
#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
475
#define TIMER_TAR_S 0
476
477
//*****************************************************************************
478
//
479
// The following are defines for the bit fields in the TIMER_O_TBR register.
480
//
481
//*****************************************************************************
482
#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
483
#define TIMER_TBR_S 0
484
485
//*****************************************************************************
486
//
487
// The following are defines for the bit fields in the TIMER_O_TAV register.
488
//
489
//*****************************************************************************
490
#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
491
#define TIMER_TAV_S 0
492
493
//*****************************************************************************
494
//
495
// The following are defines for the bit fields in the TIMER_O_TBV register.
496
//
497
//*****************************************************************************
498
#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
499
#define TIMER_TBV_S 0
500
501
//*****************************************************************************
502
//
503
// The following are defines for the bit fields in the TIMER_O_RTCPD register.
504
//
505
//*****************************************************************************
506
#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
507
#define TIMER_RTCPD_RTCPD_S 0
508
509
//*****************************************************************************
510
//
511
// The following are defines for the bit fields in the TIMER_O_TAPS register.
512
//
513
//*****************************************************************************
514
#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
515
#define TIMER_TAPS_PSS_S 0
516
517
//*****************************************************************************
518
//
519
// The following are defines for the bit fields in the TIMER_O_TBPS register.
520
//
521
//*****************************************************************************
522
#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
523
#define TIMER_TBPS_PSS_S 0
524
525
//*****************************************************************************
526
//
527
// The following are defines for the bit fields in the TIMER_O_TAPV register.
528
//
529
//*****************************************************************************
530
#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
531
#define TIMER_TAPV_PSV_S 0
532
533
//*****************************************************************************
534
//
535
// The following are defines for the bit fields in the TIMER_O_TBPV register.
536
//
537
//*****************************************************************************
538
#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
539
#define TIMER_TBPV_PSV_S 0
540
541
//*****************************************************************************
542
//
543
// The following are defines for the bit fields in the TIMER_O_DMAEV register.
544
//
545
//*****************************************************************************
546
#define TIMER_DMAEV_TBMDMAEN 0x00000800 // GPTM B Mode Match Event DMA
547
// Trigger Enable
548
#define TIMER_DMAEV_CBEDMAEN 0x00000400 // GPTM B Capture Event DMA Trigger
549
// Enable
550
#define TIMER_DMAEV_CBMDMAEN 0x00000200 // GPTM B Capture Match Event DMA
551
// Trigger Enable
552
#define TIMER_DMAEV_TBTODMAEN 0x00000100 // GPTM B Time-Out Event DMA
553
// Trigger Enable
554
#define TIMER_DMAEV_TAMDMAEN 0x00000010 // GPTM A Mode Match Event DMA
555
// Trigger Enable
556
#define TIMER_DMAEV_RTCDMAEN 0x00000008 // GPTM A RTC Match Event DMA
557
// Trigger Enable
558
#define TIMER_DMAEV_CAEDMAEN 0x00000004 // GPTM A Capture Event DMA Trigger
559
// Enable
560
#define TIMER_DMAEV_CAMDMAEN 0x00000002 // GPTM A Capture Match Event DMA
561
// Trigger Enable
562
#define TIMER_DMAEV_TATODMAEN 0x00000001 // GPTM A Time-Out Event DMA
563
// Trigger Enable
564
565
//*****************************************************************************
566
//
567
// The following are defines for the bit fields in the TIMER_O_ADCEV register.
568
//
569
//*****************************************************************************
570
#define TIMER_ADCEV_TBMADCEN 0x00000800 // GPTM B Mode Match Event ADC
571
// Trigger Enable
572
#define TIMER_ADCEV_CBEADCEN 0x00000400 // GPTM B Capture Event ADC Trigger
573
// Enable
574
#define TIMER_ADCEV_CBMADCEN 0x00000200 // GPTM B Capture Match Event ADC
575
// Trigger Enable
576
#define TIMER_ADCEV_TBTOADCEN 0x00000100 // GPTM B Time-Out Event ADC
577
// Trigger Enable
578
#define TIMER_ADCEV_TAMADCEN 0x00000010 // GPTM A Mode Match Event ADC
579
// Trigger Enable
580
#define TIMER_ADCEV_RTCADCEN 0x00000008 // GPTM RTC Match Event ADC Trigger
581
// Enable
582
#define TIMER_ADCEV_CAEADCEN 0x00000004 // GPTM A Capture Event ADC Trigger
583
// Enable
584
#define TIMER_ADCEV_CAMADCEN 0x00000002 // GPTM A Capture Match Event ADC
585
// Trigger Enable
586
#define TIMER_ADCEV_TATOADCEN 0x00000001 // GPTM A Time-Out Event ADC
587
// Trigger Enable
588
589
//*****************************************************************************
590
//
591
// The following are defines for the bit fields in the TIMER_O_PP register.
592
//
593
//*****************************************************************************
594
#define TIMER_PP_ALTCLK 0x00000040 // Alternate Clock Source
595
#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start
596
#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers
597
#define TIMER_PP_SIZE_M 0x0000000F // Count Size
598
#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
599
// 16 bits each with an 8-bit
600
// prescale counter
601
#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
602
// 32 bits each with a 16-bit
603
// prescale counter
604
605
//*****************************************************************************
606
//
607
// The following are defines for the bit fields in the TIMER_O_CC register.
608
//
609
//*****************************************************************************
610
#define TIMER_CC_ALTCLK 0x00000001 // Alternate Clock Source
611
612
#endif // __HW_TIMER_H__
© Copyright 1995-2019
, Texas Instruments Incorporated. All rights reserved.
Trademarks
|
Privacy policy
|
Terms of use
|
Terms of sale
