MSP432E4 DriverLib API Guide
1.11.00.03
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msp432e4
driverlib
inc
hw_lcd.h
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//*****************************************************************************
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//
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// hw_lcd.h - Defines and macros used when accessing the LCD controller.
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//
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// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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#ifndef __HW_LCD_H__
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#define __HW_LCD_H__
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//*****************************************************************************
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//
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// The following are defines for the LCD register offsets.
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//
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//*****************************************************************************
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#define LCD_O_PID 0x00000000 // LCD PID Register Format
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#define LCD_O_CTL 0x00000004 // LCD Control
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#define LCD_O_LIDDCTL 0x0000000C // LCD LIDD Control
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#define LCD_O_LIDDCS0CFG 0x00000010 // LCD LIDD CS0 Configuration
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#define LCD_O_LIDDCS0ADDR 0x00000014 // LIDD CS0 Read/Write Address
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#define LCD_O_LIDDCS0DATA 0x00000018 // LIDD CS0 Data Read/Write
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// Initiation
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#define LCD_O_LIDDCS1CFG 0x0000001C // LIDD CS1 Configuration
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#define LCD_O_LIDDCS1ADDR 0x00000020 // LIDD CS1 Address Read/Write
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// Initiation
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#define LCD_O_LIDDCS1DATA 0x00000024 // LIDD CS1 Data Read/Write
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// Initiation
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#define LCD_O_RASTRCTL 0x00000028 // LCD Raster Control
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#define LCD_O_RASTRTIM0 0x0000002C // LCD Raster Timing 0
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#define LCD_O_RASTRTIM1 0x00000030 // LCD Raster Timing 1
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#define LCD_O_RASTRTIM2 0x00000034 // LCD Raster Timing 2
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#define LCD_O_RASTRSUBP1 0x00000038 // LCD Raster Subpanel Display 1
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#define LCD_O_RASTRSUBP2 0x0000003C // LCD Raster Subpanel Display 2
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#define LCD_O_DMACTL 0x00000040 // LCD DMA Control
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#define LCD_O_DMABAFB0 0x00000044 // LCD DMA Frame Buffer 0 Base
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// Address
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#define LCD_O_DMACAFB0 0x00000048 // LCD DMA Frame Buffer 0 Ceiling
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// Address
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#define LCD_O_DMABAFB1 0x0000004C // LCD DMA Frame Buffer 1 Base
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// Address
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#define LCD_O_DMACAFB1 0x00000050 // LCD DMA Frame Buffer 1 Ceiling
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// Address
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#define LCD_O_SYSCFG 0x00000054 // LCD System Configuration
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// Register
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#define LCD_O_RISSET 0x00000058 // LCD Interrupt Raw Status and Set
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// Register
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#define LCD_O_MISCLR 0x0000005C // LCD Interrupt Status and Clear
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#define LCD_O_IM 0x00000060 // LCD Interrupt Mask
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#define LCD_O_IENC 0x00000064 // LCD Interrupt Enable Clear
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#define LCD_O_CLKEN 0x0000006C // LCD Clock Enable
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#define LCD_O_CLKRESET 0x00000070 // LCD Clock Resets
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_PID register.
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//
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//*****************************************************************************
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#define LCD_PID_MAJOR_M 0x00000700 // Major Release Number
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#define LCD_PID_MINOR_M 0x0000003F // Minor Release Number
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#define LCD_PID_MAJOR_S 8
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#define LCD_PID_MINOR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_CTL register.
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//
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//*****************************************************************************
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#define LCD_CTL_CLKDIV_M 0x0000FF00 // Clock Divisor
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#define LCD_CTL_UFLOWRST 0x00000002 // Underflow Restart
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#define LCD_CTL_LCDMODE 0x00000001 // LCD Mode Select
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#define LCD_CTL_CLKDIV_S 8
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_LIDDCTL register.
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//
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//*****************************************************************************
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#define LCD_LIDDCTL_DMACS 0x00000200 // CS0/CS1 Select for LIDD DMA
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// Writes
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#define LCD_LIDDCTL_DMAEN 0x00000100 // LIDD DMA Enable
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#define LCD_LIDDCTL_CS1E1 0x00000080 // Chip Select 1 (CS1)/Enable 1(E1)
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// Polarity Control
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#define LCD_LIDDCTL_CS0E0 0x00000040 // Chip Select 0 (CS0)/Enable 0
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// (E0) Polarity Control
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#define LCD_LIDDCTL_WRDIRINV 0x00000020 // Write Strobe (WR) /Direction
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// (DIR) Polarity Control
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#define LCD_LIDDCTL_RDEN 0x00000010 // Read Strobe (RD) /Direct Enable
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// (EN) Polarity Control
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#define LCD_LIDDCTL_ALE 0x00000008 // Address Latch Enable (ALE)
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// Polarity Control
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#define LCD_LIDDCTL_MODE_M 0x00000007 // LIDD Mode Select
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#define LCD_LIDDCTL_MODE_SYNCM68 \
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0x00000000 // Synchronous Motorola 6800 Mode
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#define LCD_LIDDCTL_MODE_ASYNCM68 \
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0x00000001 // Asynchronous Motorola 6800 Mode
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#define LCD_LIDDCTL_MODE_SYNCM80 \
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0x00000002 // Synchronous Intel 8080 mode
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#define LCD_LIDDCTL_MODE_ASYNCM80 \
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0x00000003 // Asynchronous Intel 8080 mode
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#define LCD_LIDDCTL_MODE_ASYNCHIT \
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0x00000004 // Asynchronous Hitachi mode
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_LIDDCS0CFG
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// register.
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//
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//*****************************************************************************
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#define LCD_LIDDCS0CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles
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#define LCD_LIDDCS0CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration
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// Cycles
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#define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles
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#define LCD_LIDDCS0CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles
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#define LCD_LIDDCS0CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles
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#define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles
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#define LCD_LIDDCS0CFG_GAP_M 0x00000003 // Field value defines the number
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// of LCDMCLK cycles (GAP +1)
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// between the end of one CS0
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// (LCDAC) device access and the
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// start of another CS0 (LCDAC)
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// device access unless the two
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// accesses are both reads
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#define LCD_LIDDCS0CFG_WRSU_S 27
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#define LCD_LIDDCS0CFG_WRDUR_S 21
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#define LCD_LIDDCS0CFG_WRHOLD_S 17
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#define LCD_LIDDCS0CFG_RDSU_S 12
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#define LCD_LIDDCS0CFG_RDDUR_S 6
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#define LCD_LIDDCS0CFG_RDHOLD_S 2
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#define LCD_LIDDCS0CFG_GAP_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR
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// register.
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//
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//*****************************************************************************
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#define LCD_LIDDCS0ADDR_CS0ADDR_M \
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0x0000FFFF // LCD Address
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#define LCD_LIDDCS0ADDR_CS0ADDR_S \
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0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_LIDDCS0DATA
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// register.
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//
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//*****************************************************************************
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#define LCD_LIDDCS0DATA_CS0DATA_M \
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0x0000FFFF // LCD Data Read/Write
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#define LCD_LIDDCS0DATA_CS0DATA_S \
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0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_LIDDCS1CFG
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// register.
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//
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//*****************************************************************************
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#define LCD_LIDDCS1CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles
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#define LCD_LIDDCS1CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration
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// Cycles
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#define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles
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#define LCD_LIDDCS1CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles
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#define LCD_LIDDCS1CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles
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#define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles
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#define LCD_LIDDCS1CFG_GAP_M 0x00000003 // Field value defines the number
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// of LCDMCLK cycles (GAP + 1)
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// between the end of one CS1
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// (LCDAC) device access and the
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// start of another CS0 (LCDAC)
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// device access unless the two
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// accesses are both reads
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#define LCD_LIDDCS1CFG_WRSU_S 27
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#define LCD_LIDDCS1CFG_WRDUR_S 21
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#define LCD_LIDDCS1CFG_WRHOLD_S 17
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#define LCD_LIDDCS1CFG_RDSU_S 12
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#define LCD_LIDDCS1CFG_RDDUR_S 6
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#define LCD_LIDDCS1CFG_RDHOLD_S 2
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#define LCD_LIDDCS1CFG_GAP_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR
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// register.
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//
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//*****************************************************************************
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#define LCD_LIDDCS1ADDR_CS1ADDR_M \
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0x0000FFFF // LCD Address Bus
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#define LCD_LIDDCS1ADDR_CS1ADDR_S \
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0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_LIDDCS1DATA
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// register.
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//
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//*****************************************************************************
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#define LCD_LIDDCS1DATA_CS0DATA_M \
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0x0000FFFF // LCD Data Read/Write Initiation
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#define LCD_LIDDCS1DATA_CS0DATA_S \
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0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_RASTRCTL register.
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//
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//*****************************************************************************
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#define LCD_RASTRCTL_TFT24UPCK 0x04000000 // 24-bit TFT Mode Packing
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#define LCD_RASTRCTL_TFT24 0x02000000 // 24-Bit TFT Mode
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#define LCD_RASTRCTL_FRMBUFSZ 0x01000000 // Frame Buffer Select
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#define LCD_RASTRCTL_TFTMAP 0x00800000 // TFT Mode Alternate Signal
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// Mapping for Palettized
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// Framebuffer
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#define LCD_RASTRCTL_NIBMODE 0x00400000 // Nibble Mode
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#define LCD_RASTRCTL_PALMODE_M 0x00300000 // Pallette Loading Mode
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#define LCD_RASTRCTL_PALMODE_PALDAT \
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0x00000000 // Palette and data loading, reset
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// value
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#define LCD_RASTRCTL_PALMODE_PAL \
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0x00100000 // Palette loading only
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#define LCD_RASTRCTL_PALMODE_DAT \
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0x00200000 // Data loading only
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#define LCD_RASTRCTL_REQDLY_M 0x000FF000 // Palette Loading Delay
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#define LCD_RASTRCTL_MONO8B 0x00000200 // Mono 8-Bit
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#define LCD_RASTRCTL_RDORDER 0x00000100 // Raster Data Order Select
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#define LCD_RASTRCTL_LCDTFT 0x00000080 // LCD TFT
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#define LCD_RASTRCTL_LCDBW 0x00000002 // LCD Monochrome
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#define LCD_RASTRCTL_LCDEN 0x00000001 // LCD Controller Enable for Raster
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// Operations
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#define LCD_RASTRCTL_REQDLY_S 12
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_RASTRTIM0
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// register.
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//
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//*****************************************************************************
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#define LCD_RASTRTIM0_HBP_M 0xFF000000 // Horizontal Back Porch Lowbits
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#define LCD_RASTRTIM0_HFP_M 0x00FF0000 // Horizontal Front Porch Lowbits
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#define LCD_RASTRTIM0_HSW_M 0x0000FC00 // Horizontal Sync Pulse Width
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// Lowbits
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#define LCD_RASTRTIM0_PPL_M 0x000003F0 // Pixels-per-line LSB[9:4]
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#define LCD_RASTRTIM0_MSBPPL 0x00000008 // Pixels-per-line MSB[10]
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#define LCD_RASTRTIM0_HBP_S 24
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#define LCD_RASTRTIM0_HFP_S 16
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#define LCD_RASTRTIM0_HSW_S 10
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#define LCD_RASTRTIM0_PPL_S 4
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#define LCD_RASTRTIM0_MSBPPL_S 3
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_RASTRTIM1
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// register.
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//
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//*****************************************************************************
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#define LCD_RASTRTIM1_VBP_M 0xFF000000 // Vertical Back Porch
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#define LCD_RASTRTIM1_VFP_M 0x00FF0000 // Vertical Front Porch
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#define LCD_RASTRTIM1_VSW_M 0x0000FC00 // Vertical Sync Width Pulse
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#define LCD_RASTRTIM1_LPP_M 0x000003FF // Lines Per Panel
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#define LCD_RASTRTIM1_VBP_S 24
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#define LCD_RASTRTIM1_VFP_S 16
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#define LCD_RASTRTIM1_VSW_S 10
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#define LCD_RASTRTIM1_LPP_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_RASTRTIM2
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// register.
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//
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//*****************************************************************************
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#define LCD_RASTRTIM2_HSW_M 0x78000000 // Bits 9:6 of the horizontal sync
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// width field
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#define LCD_RASTRTIM2_MSBLPP 0x04000000 // MSB of Lines Per Panel
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#define LCD_RASTRTIM2_PXLCLKCTL 0x02000000 // Hsync/Vsync Pixel Clock Control
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// On/Off
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#define LCD_RASTRTIM2_PSYNCRF 0x01000000 // Program HSYNC/VSYNC Rise or Fall
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#define LCD_RASTRTIM2_INVOE 0x00800000 // Invert Output Enable
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#define LCD_RASTRTIM2_INVPXLCLK 0x00400000 // Invert Pixel Clock
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#define LCD_RASTRTIM2_IHS 0x00200000 // Invert Hysync
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#define LCD_RASTRTIM2_IVS 0x00100000 // Invert Vsync
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#define LCD_RASTRTIM2_ACBI_M 0x000F0000 // AC Bias Pins Transitions per
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// Interrupt
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#define LCD_RASTRTIM2_ACBF_M 0x0000FF00 // AC Bias Pin Frequency
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#define LCD_RASTRTIM2_MSBHBP_M 0x00000030 // Bits 9:8 of the horizontal back
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// porch field
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#define LCD_RASTRTIM2_MSBHFP_M 0x00000003 // Bits 9:8 of the horizontal front
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// porch field
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#define LCD_RASTRTIM2_HSW_S 27
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#define LCD_RASTRTIM2_MSBLPP_S 26
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#define LCD_RASTRTIM2_ACBI_S 16
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#define LCD_RASTRTIM2_ACBF_S 8
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#define LCD_RASTRTIM2_MSBHBP_S 4
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#define LCD_RASTRTIM2_MSBHFP_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_RASTRSUBP1
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// register.
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//
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//*****************************************************************************
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#define LCD_RASTRSUBP1_SPEN 0x80000000 // Sub Panel Enable
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#define LCD_RASTRSUBP1_HOLS 0x20000000 // High or Low Signal
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#define LCD_RASTRSUBP1_LPPT_M 0x03FF0000 // Line Per Panel Threshold
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#define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF // Default Pixel Data LSB[15:0]
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#define LCD_RASTRSUBP1_LPPT_S 16
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#define LCD_RASTRSUBP1_DPDLSB_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_RASTRSUBP2
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// register.
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//
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//*****************************************************************************
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#define LCD_RASTRSUBP2_LPPTMSB 0x00000100 // Lines Per Panel Threshold Bit 10
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#define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF // Default Pixel Data MSB [23:16]
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#define LCD_RASTRSUBP2_DPDMSB_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_DMACTL register.
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//
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//*****************************************************************************
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#define LCD_DMACTL_FIFORDY_M 0x00000700 // DMA FIFO threshold
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#define LCD_DMACTL_FIFORDY_8 0x00000000 // 8 words
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#define LCD_DMACTL_FIFORDY_16 0x00000100 // 16 words
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#define LCD_DMACTL_FIFORDY_32 0x00000200 // 32 words
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#define LCD_DMACTL_FIFORDY_64 0x00000300 // 64 words
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#define LCD_DMACTL_FIFORDY_128 0x00000400 // 128 words
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#define LCD_DMACTL_FIFORDY_256 0x00000500 // 256 words
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#define LCD_DMACTL_FIFORDY_512 0x00000600 // 512 words
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#define LCD_DMACTL_BURSTSZ_M 0x00000070 // Burst Size setting for DMA
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// transfers (all DMA transfers are
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// 32 bits wide):
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#define LCD_DMACTL_BURSTSZ_4 0x00000020 // burst size of 4
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#define LCD_DMACTL_BURSTSZ_8 0x00000030 // burst size of 8
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#define LCD_DMACTL_BURSTSZ_16 0x00000040 // burst size of 16
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#define LCD_DMACTL_BYTESWAP 0x00000008 // This bit controls the bytelane
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// ordering of the data on the
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// output of the DMA module
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#define LCD_DMACTL_BIGDEND 0x00000002 // Big Endian Enable
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#define LCD_DMACTL_FMODE 0x00000001 // Frame Mode
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_DMABAFB0 register.
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//
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//*****************************************************************************
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#define LCD_DMABAFB0_FB0BA_M 0xFFFFFFFC // Frame Buffer 0 Base Address
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// pointer
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#define LCD_DMABAFB0_FB0BA_S 2
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_DMACAFB0 register.
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//
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//*****************************************************************************
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#define LCD_DMACAFB0_FB0CA_M 0xFFFFFFFC // Frame Buffer 0 Ceiling Address
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// pointer
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#define LCD_DMACAFB0_FB0CA_S 2
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_DMABAFB1 register.
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//
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//*****************************************************************************
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#define LCD_DMABAFB1_FB1BA_M 0xFFFFFFFC // Frame Buffer 1 Base Address
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// pointer
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#define LCD_DMABAFB1_FB1BA_S 2
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_DMACAFB1 register.
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//
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//*****************************************************************************
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#define LCD_DMACAFB1_FB1CA_M 0xFFFFFFFC // Frame Buffer 1 Ceiling Address
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// pointer
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#define LCD_DMACAFB1_FB1CA_S 2
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409
//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_SYSCFG register.
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//
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//*****************************************************************************
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#define LCD_SYSCFG_STDBY_M 0x00000030 // Standby Mode
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#define LCD_SYSCFG_STDBY_FORCE 0x00000000 // Force-standby mode: local
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// initiator is unconditionally
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// placed in standby state. Backup
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// mode, for debug only
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#define LCD_SYSCFG_STDBY_NONE 0x00000010 // No-standby mode: local initiator
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// is unconditionally placed out of
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// standby state. Backup mode, for
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// debug only
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#define LCD_SYSCFG_STDBY_SMART 0x00000020 // Smart-standby mode: local
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// initiator standby status depends
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// on local conditions, that is,
426
// the module's functional
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// requirement from the initiator.
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// IP module shall not generate
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// (initiator-related) wakeup
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// events
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#define LCD_SYSCFG_IDLEMODE_M 0x0000000C // Idle Mode
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#define LCD_SYSCFG_IDLEMODE_FORCE \
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0x00000000 // Force-idle mode: local target's
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// idle state follows
435
// (acknowledges) the system's idle
436
// requests unconditionally, that
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// is, regardless of the IP
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// module's internal requirements.
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// Backup mode, for debug only
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#define LCD_SYSCFG_IDLEMODE_NONE \
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0x00000004 // No-idle mode: local target never
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// enters idle state. Backup mode,
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// for debug only
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#define LCD_SYSCFG_IDLEMODE_SMART \
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0x00000008 // Smart-idle mode: local target's
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// idle state eventually follows
447
// (acknowledges) the system's idle
448
// requests, depending on the IP
449
// module's internal requirements.
450
// IP module shall not generate
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// (IRQ- or DMA-requestrelated)
452
// wakeup events
453
454
//*****************************************************************************
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//
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// The following are defines for the bit fields in the LCD_O_RISSET register.
457
//
458
//*****************************************************************************
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#define LCD_RISSET_EOF1 0x00000200 // DMA End-of-Frame 1 Raw Interrupt
460
// Status and Set
461
#define LCD_RISSET_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt
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// Status and Set
463
#define LCD_RISSET_PALLOAD 0x00000040 // DMA Palette Loaded Raw Interrupt
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// Status and Set
465
#define LCD_RISSET_FIFOU 0x00000020 // DMA FIFO Underflow Raw Interrupt
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// Status and Set
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#define LCD_RISSET_ACBS 0x00000008 // AC Bias Count Raw Interrupt
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// Status and Set
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#define LCD_RISSET_SYNCS 0x00000004 // Frame Synchronization Lost Raw
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// Interrupt Status and Set
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#define LCD_RISSET_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt
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#define LCD_RISSET_DONE 0x00000001 // Raster or LIDD Frame Done
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// (shared, depends on whether
474
// Raster or LIDD mode enabled) Raw
475
// Interrupt Status and Set
476
477
//*****************************************************************************
478
//
479
// The following are defines for the bit fields in the LCD_O_MISCLR register.
480
//
481
//*****************************************************************************
482
#define LCD_MISCLR_EOF1 0x00000200 // DMA End-of-Frame 1 Enabled
483
// Interrupt and Clear
484
#define LCD_MISCLR_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt
485
// and Clear
486
#define LCD_MISCLR_PALLOAD 0x00000040 // DMA Palette Loaded Enabled
487
// Interrupt and Clear
488
#define LCD_MISCLR_FIFOU 0x00000020 // DMA FIFO Underflow Enabled
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// Interrupt and Clear
490
#define LCD_MISCLR_ACBS 0x00000008 // AC Bias Count Enabled Interrupt
491
// and Clear
492
#define LCD_MISCLR_SYNCS 0x00000004 // Frame Synchronization Lost
493
// Enabled Interrupt and Clear
494
#define LCD_MISCLR_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt
495
#define LCD_MISCLR_DONE 0x00000001 // Raster or LIDD Frame Done
496
// (shared, depends on whether
497
// Raster or LIDD mode enabled)
498
// Enabled Interrupt and Clear
499
500
//*****************************************************************************
501
//
502
// The following are defines for the bit fields in the LCD_O_IM register.
503
//
504
//*****************************************************************************
505
#define LCD_IM_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt
506
// Enable Set
507
#define LCD_IM_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt
508
// Enable Set
509
#define LCD_IM_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt
510
// Enable Set
511
#define LCD_IM_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt
512
// Enable Set
513
#define LCD_IM_ACBS 0x00000008 // AC Bias Count Interrupt Enable
514
// Set
515
#define LCD_IM_SYNCS 0x00000004 // Frame Synchronization Lost
516
// Interrupt Enable Set
517
#define LCD_IM_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt
518
// Enable Set
519
#define LCD_IM_DONE 0x00000001 // Raster or LIDD Frame Done
520
// (shared, depends on whether
521
// Raster or LIDD mode enabled)
522
// Interrupt Enable Set
523
524
//*****************************************************************************
525
//
526
// The following are defines for the bit fields in the LCD_O_IENC register.
527
//
528
//*****************************************************************************
529
#define LCD_IENC_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt
530
// Enable Clear
531
#define LCD_IENC_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt
532
// Enable Clear
533
#define LCD_IENC_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt
534
// Enable Clear
535
#define LCD_IENC_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt
536
// Enable Clear
537
#define LCD_IENC_ACBS 0x00000008 // AC Bias Count Interrupt Enable
538
// Clear
539
#define LCD_IENC_SYNCS 0x00000004 // Frame Synchronization Lost
540
// Interrupt Enable Clear
541
#define LCD_IENC_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt
542
// Enable Clear
543
#define LCD_IENC_DONE 0x00000001 // Raster or LIDD Frame Done
544
// (shared, depends on whether
545
// Raster or LIDD mode enabled)
546
// Interrupt Enable Clear
547
548
//*****************************************************************************
549
//
550
// The following are defines for the bit fields in the LCD_O_CLKEN register.
551
//
552
//*****************************************************************************
553
#define LCD_CLKEN_DMA 0x00000004 // DMA Clock Enable
554
#define LCD_CLKEN_LIDD 0x00000002 // LIDD Submodule Clock Enable
555
#define LCD_CLKEN_CORE 0x00000001 // LCD Core Clock Enable
556
557
//*****************************************************************************
558
//
559
// The following are defines for the bit fields in the LCD_O_CLKRESET register.
560
//
561
//*****************************************************************************
562
#define LCD_CLKRESET_MAIN 0x00000008 // Software Reset for the entire
563
// LCD module
564
#define LCD_CLKRESET_DMA 0x00000004 // Software Reset for the DMA
565
// submodule
566
#define LCD_CLKRESET_LIDD 0x00000002 // Software Reset for the LIDD
567
// submodule (character displays)
568
#define LCD_CLKRESET_CORE 0x00000001 // Software Reset for the Core,
569
// which encompasses the Raster
570
// Active Matrix and Passive Matrix
571
// logic
572
573
#endif // __HW_LCD_H__
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