MSP432E4 DriverLib API Guide
1.11.00.03
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msp432e4
driverlib
inc
hw_gpio.h
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//*****************************************************************************
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//
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// hw_gpio.h - Defines and Macros for GPIO hardware.
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//
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// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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#ifndef __HW_GPIO_H__
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#define __HW_GPIO_H__
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//*****************************************************************************
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//
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// The following are defines for the GPIO register offsets.
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//
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//*****************************************************************************
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#define GPIO_O_DATA 0x00000000 // GPIO Data
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#define GPIO_O_DIR 0x00000400 // GPIO Direction
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#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
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#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
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#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
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#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
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#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
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#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
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#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
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#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
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#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
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#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
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#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
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#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
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#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
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#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
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#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
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#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
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#define GPIO_O_LOCK 0x00000520 // GPIO Lock
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#define GPIO_O_CR 0x00000524 // GPIO Commit
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#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
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#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
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#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
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#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
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#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
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#define GPIO_O_DR12R 0x0000053C // GPIO 12-mA Drive Select
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#define GPIO_O_WAKEPEN 0x00000540 // GPIO Wake Pin Enable
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#define GPIO_O_WAKELVL 0x00000544 // GPIO Wake Level
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#define GPIO_O_WAKESTAT 0x00000548 // GPIO Wake Status
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#define GPIO_O_PP 0x00000FC0 // GPIO Peripheral Property
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#define GPIO_O_PC 0x00000FC4 // GPIO Peripheral Configuration
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_IM register.
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//
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//*****************************************************************************
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#define GPIO_IM_DMAIME 0x00000100 // GPIO uDMA Done Interrupt Mask
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// Enable
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#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
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#define GPIO_IM_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_RIS register.
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//
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//*****************************************************************************
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#define GPIO_RIS_DMARIS 0x00000100 // GPIO uDMA Done Interrupt Raw
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// Status
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#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
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#define GPIO_RIS_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_MIS register.
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//
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//*****************************************************************************
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#define GPIO_MIS_DMAMIS 0x00000100 // GPIO uDMA Done Masked Interrupt
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// Status
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#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
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#define GPIO_MIS_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_ICR register.
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//
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//*****************************************************************************
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#define GPIO_ICR_DMAIC 0x00000100 // GPIO uDMA Interrupt Clear
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#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
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#define GPIO_ICR_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_LOCK register.
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//
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//*****************************************************************************
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#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
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#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
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// and may be modified
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#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
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// and may not be modified
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#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_SI register.
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//
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//*****************************************************************************
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#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_DR12R register.
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//
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//*****************************************************************************
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#define GPIO_DR12R_DRV12_M 0x000000FF // Output Pad 12-mA Drive Enable
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#define GPIO_DR12R_DRV12_12MA 0x00000001 // The corresponding GPIO pin has
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// 12-mA drive. This encoding is
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// only valid if the GPIOPP EDE bit
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// is set and the appropriate
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// GPIOPC EDM bit field is
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// programmed to 0x3
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_WAKEPEN register.
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//
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//*****************************************************************************
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#define GPIO_WAKEPEN_WAKEP4 0x00000010 // P[4] Wake Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_WAKELVL register.
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//
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//*****************************************************************************
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#define GPIO_WAKELVL_WAKELVL4 0x00000010 // P[4] Wake Level
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_WAKESTAT
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// register.
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//
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//*****************************************************************************
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#define GPIO_WAKESTAT_STAT4 0x00000010 // P[4] Wake Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_PP register.
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//
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//*****************************************************************************
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#define GPIO_PP_EDE 0x00000001 // Extended Drive Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_PC register.
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//
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//*****************************************************************************
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#define GPIO_PC_EDM7_M 0x0000C000 // Extended Drive Mode Bit 7
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#define GPIO_PC_EDM6_M 0x00003000 // Extended Drive Mode Bit 6
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#define GPIO_PC_EDM5_M 0x00000C00 // Extended Drive Mode Bit 5
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#define GPIO_PC_EDM4_M 0x00000300 // Extended Drive Mode Bit 4
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#define GPIO_PC_EDM3_M 0x000000C0 // Extended Drive Mode Bit 3
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#define GPIO_PC_EDM2_M 0x00000030 // Extended Drive Mode Bit 2
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#define GPIO_PC_EDM1_M 0x0000000C // Extended Drive Mode Bit 1
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#define GPIO_PC_EDM0_M 0x00000003 // Extended Drive Mode Bit 0
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#define GPIO_PC_EDM0_DISABLE 0x00000000 // Drive values of 2, 4 and 8 mA
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// are maintained. GPIO n Drive
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// Select (GPIODRnR) registers
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// function as normal
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#define GPIO_PC_EDM0_6MA 0x00000001 // An additional 6 mA option is
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// provided
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#define GPIO_PC_EDM0_PLUS2MA 0x00000003 // A 2 mA driver is always enabled;
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// setting the corresponding
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// GPIODR4R register bit adds 2 mA
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// and setting the corresponding
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// GPIODR8R of GPIODR12R register
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// bit adds an additional 4 mA
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#define GPIO_PC_EDM7_S 14
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#define GPIO_PC_EDM6_S 12
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#define GPIO_PC_EDM5_S 10
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#define GPIO_PC_EDM4_S 8
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#define GPIO_PC_EDM3_S 6
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#define GPIO_PC_EDM2_S 4
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#define GPIO_PC_EDM1_S 2
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#endif // __HW_GPIO_H__
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, Texas Instruments Incorporated. All rights reserved.
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